IES930255A2 - Method and apparatus for broken line detection in echo¹cancelling modems - Google Patents

Method and apparatus for broken line detection in echo¹cancelling modems

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Publication number
IES930255A2
IES930255A2 IES930255A IES930255A2 IE S930255 A2 IES930255 A2 IE S930255A2 IE S930255 A IES930255 A IE S930255A IE S930255 A2 IES930255 A2 IE S930255A2
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Ireland
Prior art keywords
data bits
bits
modem
outgoing
echo
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Inventor
Michael Mclaughlin
Gerard Kelly
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Taldat Ltd
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Publication date
Application filed by Taldat Ltd filed Critical Taldat Ltd
Priority to IES930255 priority Critical patent/IES930255A2/en
Publication of IES58197B2 publication Critical patent/IES58197B2/en
Publication of IES930255A2 publication Critical patent/IES930255A2/en

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Abstract

An apparatus for broken line detection in echo cancelling modems comprises a register 31 for storing successive 48-bit sets of consecutive outgoing data bits each for a time at least as long as the round trip delay. A comparator 33 compares each set of stored bits with the incoming data bits passing through a shift register 32. A broken line is detected by the provision of a signal 34 if the incoming data bits are the same or substantially the same as the stored data bits.

Description

METHOD AND APPARATUS FOR BROKEN LINE DETECTION IN ECHO CANCELLING MODEMS OPEN TO PUBLIC INSPECTIO UNGER SECTION 23 AND RULE 23 JNL No . Cr Y.6./7/?J This invention relates to a method and apparatus for broken line detection in echo cancelling modems, for example but not limited to modems complying with the CCITT V.32 and V.32 bis recommendations for full duplex data transmission at speeds of up to 14400 bps.
According to the present invention there is provided a method of broken line detection for echo cancelling modems including storing outgoing data bits for a time greater than or equal to the round trip delay and comparing them with incoming data bits to determine if the outgoing and incoming data is the same or substantially the same.
The invention further provides an apparatus for performing the above method.
An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: IE 930255 _ Figure 1 is a block schematic diagram of a known digital telecommunications system using modems; Figure 2 is a block diagram of one of the modems of Figure 1; and Figure 3 shows part of the modem of Figure 2 including broken line detection apparatus according to the embodiment of the invention.
Digital data cannot be transmitted directly over 2-wire analog telecommunications lines, be they special quality leased lines or part of the public switched telephone network (PSTN), as a theoretically infinite bandwidth would be required. The digital signals must first be converted to analog form, by using them to modulate a carrier tone within the voice band, which is then transmitted over the analog network. The received signal, which is distorted by the non-ideal nature of the network, must be demodulated to recover the digital data. These functions are performed by a modem (modulator-demodulator).
In order to simultaneously transmit data in both directions, known as full-duplex transmission, there are two possible techniques. The first is for each of the modems to transmit its modulated signal in a different part of the available bandwidth, known as frequency division multiplexing. The data rate is limited by the bandwidth used, so it would be preferable to use the whole of the channel bandwidth in each direction. This is achieved by the second technique, known as echo cancelling. Each modem uses the whole bandwidth for data transmission, thus maximising the data rate.
IE 930255 _ 3 Figure 1 shows two modems, modem A and modem B, in communication over a channel 10 such as a PSTN. On the transmission side 11 of each modem the outgoing digital data TxA or TxB is converted to analog form A or B respectively, and each analog signal is transmitted via a respective hybrid transformer 12 to the other modem. At the receiving side 13 of the other modem the incoming analog signal is re-converted to digital form RxA or RxB.
In the ideal system there would be no interference between the signals from the two modems, as the modems' own hybrid transformers would separate the transmitted and received signals. However, in any real network there are impedance mismatches at the hybrid transformers, and this causes each modem to receive an echo of its own outgoing signal, as well as the incoming signal transmitted by the other modem.
There are two major sources of echo in the system - the local hybrid transformer, which gives rise to near echo, and the remote hybrid transformer, which generates far echo. Thus, as shown in Figure 1, the signal received by the modem A comprises not only the signal B transmitted by the remote modem B but also near and far echo components An and Af respectively of its own outgoing signal A. Similarly the signal received at the modem B includes near and far echo components Bn and Bf respectively of its own outgoing signal B.
An echo cancelling modem must therefore cancel out that part of the received signal which is an echo of its own transmitted signal in order to correctly recover the received data, and for this purpose it has two echo IE 930255 cancellers to remove the spurious echo signals received from the near and far hybrid transformers. This is shown in Figure 2, which is a block diagram of the main components of a CCITT V.32 and V.32 bis echo cancelling modem. Figure 2 shows modem A, but modem B is essentially the same.
The transmission side 11 of the modem includes a scrambler 14 to spread the signal energy over the available bandwidth, an encoder 15 to map the data bits to symbols for transmission, a pulse shaping filter 16, a modulator 17 and an amplifier 18. The receiving side 13 includes an automatic gain control unit 19, a demodulator 20, a pulse shaping filter 21, an equaliser 22 and phase locked loop 23 to compensate for channel distortion, a decoder 24 and a descrambler 25. Near and far echo cancellers 26 and 27 respectively derive from the outgoing signal A an echo cancelling signal (An+Af) which is subtracted from the incoming signal (B+An+Af) at a subtraction circuit 28. It is to be understood that Figure 2 represents an entirely conventional echo cancelling modem whose construction and operation is well known. Thus no further description is thought necessary.
During the establishment of a link between echo cancelling modems, such as modems A and B in Figure 1, the modems train their echo cancellers 26 and 27 by transmitting known signals one at a time, so that the received signal consists entirely of echo. Thereafter during full duplex data transmission the modems continue to adapt their echo cancellers, but at a much slower rate.
IE 930255 - 5 A consequence of this is that the echo cancellers cannot adapt quickly enough to effectively remove the echo when the echo path is suddenly changed. Such a situation arises when the physical connection between the modems is broken. In this case the modem stops receiving a signal from the remote modem, the network becomes unbalanced, and much of the transmit signal is reflected into the receiver. This echo signal is often enough to prevent the modem's line energy monitor from detecting the loss of the true received signal, so the modem remains online and the receiver treats the echo signal as a genuine received signal.
Eventually, the echo cancellers will adapt to remove the echo signal, so that the line energy detector causes the modem to drop offline. However this typically takes a long time to occur, during which time the modem is unable to perform normal data transfer in either direction, unknown to the host system. This situation is costly in terms of time wasted, the loss of transmit data which is not backed up locally, and the effects of the reception of invalid data from extended periods.
A commonly implemented diagnostic feature for full duplex modems is the analog loop test. In this test the modem is not connected to the transmission network, and its hybrid transformer is deliberately unbalanced so that the transmitted signal is perfectly reflected back to the receiver. In this way both the transmission and receiving sides of the modem are exercised, and transmitted data is received unchanged.
IE 930255 In a broken line situation, the network is unbalanced, so a situation similar to analog loop exists. Thus the receiving side will adapt its equaliser 22 and phase locked loop 23 to correctly receive the echo of its own transmit signal, before the echo cancellers 26 and 27 adapt sufficiently to remove it. (The echo canceller convergence factors are very small because the adapting signal consists of the residual echo signal and the received signal). This provides the basis for broken line detection, since before the echo cancellers adapt one can detect a broken line by comparing the outgoing and incoming data streams to see if they are the same.
In V.32 and V.32 bis modems the calling and answering modems use different scrambler polynomials, so the scrambler 14 and descrambler 25 in each modem use different polynomials. This means that the transmitted and received echo bit streams at the data interface between the modem and host (i.e. at the extreme left in Figure 2) are different. Thus a broken line cannot be detected by comparing these data streams. Instead, the bit streams at the output of the scrambler and the input to the descrambler are compared - these will be identical in the broken line situation.
Referring now to Figure 3, the additional apparatus for broken line detection is shown. In Figure 3 the direction of data flow is from left to right in both the transmission and receiving sides so that the shift registers have the same orientation. Also, the various signals there shown are: lE 930255 TXDCLK = Transmit bit rate clock.
RXDCLK = Receive bit rate clock.
RXBCLK = Receive symbol rate clock.
RTDxy = Round trip delay between points x and y.
All the above signals are standard and already provided in a V.32 and V.32 bis modem. RTDxy consists of a series of pulses whose period is the round trip delay, as measured during the initial V.32/V.32 bis handshake.
A 48-bit shift register 30 is inserted between the scrambler 14 and the encoder 15 on the transmission side of the modem, and the outgoing data bits are shifted serially through this under the control of the transmit bit rate clock TXDCLK. A 48-bit storage register 31 is clocked with the round trip delay pulses RTDxy, such that on each occurrence of an RTDxy pulse the 48 consecutive outgoing bits then in the shift register 30 are copied in parallel into the register 31, overwriting the previous contents of the register 31.
A second 48-bit shift register 32 is inserted between the decoder 24 and the descrambler 25 on the receiving side of the modem, and the incoming data bits are shifted serially through this under the control of the receive bit rate clock RXDCLK. A comparator 33 is connected between the storage register 31 and the shift register 32 and this is clocked with the receive symbol rate clock RXBCLK. On each occurrence of an RXBCLK pulse the comparator 33 compares the 48 bits stored in the storage register 31 with the 48 bits then in the shift register 32. If all 48 bits are the same, a signal is IE 930255 provided on the line 34 to indicate that a broken line has been detected, and in known manner such signal may be used to automatically place the modem offline.
Thus, in summary, 48 consecutive outgoing data 5 bits are sampled and stored at intervals of the round trip delay, and the stored bits are compared with the incoming bits every symbol interval.
Instead of placing the shift register 30 in series between the scrambler 14 and the encoder 15, it is alternatively possible to have the shift register 30 arranged in parallel with the encoder 15 so that the scrambler 14 supplies the outgoing data bits both directly to the encoder 15, as shown in Figure 2, and at the same time also to the input of the shift register . Of course, in such a case the output of the shift register 30 would not be needed, so that the data bits would just be discarded after they had been shifted through all 48 bit positions of the shift register. Naturally, the shift register 32 can be similarly arranged in parallel with the descrambler 25, there being a direct connection between the decoder 24 and the descrambler 25 and the incoming data bits being supplied both to the descrambler 25 and the shift register 32.
The effect of this embodiment is that a broken line will be detected as soon as the receiving side of the modem has trained its equaliser on the echo signal, which normally takes a short time to occur. (If the equaliser cannot train quickly, then the signal to noise ratio will drop, and a retrain will be initiated - no response will be obtained, so the modem will go offline, as required).
IE 930255 _ 9 _ Variations of the above embodiment are possible.
For example, any number of bits could be used for the comparison, but the greater the number of bits used the less the probability of a spurious detection, as the detection criterion is essentially the comparison of two random bit patterns. For example, 48-bit random sequences would only be identical once every 3719 years at 2400 baud, while for 24-bit sequences this reduces to 2 hours.
Further, while the same stored bits should be used in the comparison for a time no less than the round trip delay, because the echo point could be anywhere in the intervening network, a longer bit storage period could be used. Also, the actual comparison could be effected more or less often than defined by the receive symbol rate clock RXBCLK, for example at the receive bit rate or multiples of the symbol interval, although if the comparison is made less often than the symbol rate there is a chance that a match will be missed. However, it is sufficient to compare the bit streams every symbol interval, as the transmit and receive symbol rate clocks are also synchronised in a broken line situation.
In modems where the scrambler and descrambler polynomials are the same, one can compare the unscrambled outgoing data TxA with the descrambled incoming data RxA. In general the comparison can be performed at any point where the incoming and outgoing data is expected to be the same in the event of a broken line.
Finally, it should be understood that the comparator 32 could be designed to provide an output on line 34 not only when all 48 bits in each of the IE 930255 - 10registers 31 and 32 compare as being precisely the same, but also when substantially all the 48 bits in the two registers compare as being the same. This would allow for detection of a broken line when the reflection at the break is not perfect.
In summary the invention provides a simple, reliable and fast means of broken line detection for echo cancelling modems, thus reducing the impact of line breaks on overall modem performance.

Claims (5)

CLAIMS:
1. A method of broken line detection for echo cancelling modems including storing outgoing data bits for a 5 time greater than or equal to the round trip delay and comparing these with incoming data bits to determine if the outgoing and incoming data is the same or substantially the same. 10
2. A method as claimed in claim 1, wherein the transmission side of the modem includes a scrambler and an encoder and the receiving side of the modem includes a descrambler and decoder, and wherein the outgoing data bits are taken from between the scrambler and the encoder and the 15 incoming data bits are taken from between the descrambler and the decoder.
3. A method as claimed in claim 1 or 2, wherein successive sets of outgoing data bits are each stored for a 20 time greater than or equal to the round trip delay and compared with incoming data bits.
4. A method as claimed in claim 3, wherein each successive set of outgoing data bits comprises a plurality 25 of consecutive outgoing bits which are compared with a similar plurality of consecutive incoming data bits of predetermined intervals.
5. A method as claimed in claim 3 or 4, wherein each 30 set of outgoing data bits is stored in a register and replaced after a time greater than or equal to the round trip delay by the next set, and the incoming data bits are passed into a shift register, the contents of the shift register being compared with the stored set of bits at 35 predetermined intervals.
IES930255 1992-06-22 1993-03-30 Method and apparatus for broken line detection in echo¹cancelling modems IES930255A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
IES930255 IES930255A2 (en) 1992-06-22 1993-03-30 Method and apparatus for broken line detection in echo¹cancelling modems

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IE922011 1992-06-22
IES930255 IES930255A2 (en) 1992-06-22 1993-03-30 Method and apparatus for broken line detection in echo¹cancelling modems

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IES58197B2 IES58197B2 (en) 1993-07-28
IES930255A2 true IES930255A2 (en) 1993-07-28

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