IE910093A1 - Signal level converter - Google Patents

Abstract

A signal level converter for conversion of CMOS logic input signal levels on CML input signal levels to CML or ECL output signal levels comprises a differential amplifier arrangement serving as a current switch with a first and a second amplifier branch. The first amplifier branch has a control transistor (ST) and the second amplifier branch has a reference transistor (RT). In order to be able to use the signal level converter to form logic, the control transistor (ST) is designed as a field effect transistor, since field effect transistors, unlike bipolar transistors, have no saturation response.

Description

The invention relates to a signal level converter according to the pre-characterizing clause of Claim 1.

Such signal level converters are generally intended for identifying the binary value represented by a CMOS logic signal level in accordance with CMOS definitions and to generate a corresponding signal level intended for the representation of this binary value as determined by the current mode logic (CML) or emitter-coupled logic (ECL).

Compared with the signal levels of CMOS logic in which the voltage values for the digital L and H levels correspond to the values of the supply voltage potential, the digital H level in current mode logic (CML) is at the more positive value of the two supply voltage potentials and the digital L level is at a voltage value which is more negative by only approximately 0.5 volt. In the case of the emitter-coupled logic (ECL), the digital H level is approximately 0.9 volt and the digital L level is approximately 1.7 volts more negative than the more positive value of the two supply voltage potentials.

Assuming a supply voltage potential difference of approximately 5 volts, a signal level converter for converting CMOS logic input signal levels to CML or to ECL output signal levels must convert an input signal level excursion of 5 volts to an output signal level excursion of I IE 9193 0.5 volts for CML and ECL taking into consideration respective signal/noise ratios.

A known signal level converter for converting CMOS logic input signal levels to CML or ECL output signal levels, called CMOS - CML/ECL level converter in the text which follows, consists of a slightly modified switching stage of the CML or ECL circuit technology.

Such a switching stage of the CML or ECL circuit technology is formed of a constant-current-fed differential amplifier with a first and a second amplifier branch which in each case exhibit a control or reference transistor constructed as NPN transistor. The emitter electrodes of the two NPN transistors are connected to one another and connected to the constant current source.

The base electrode of the control transistor is used as switching stage input, to that of the reference transistor a constant reference voltage potential is applied which determines the switching threshold of the switching stage and thus has the voltage value above or below which the voltage at the switching stage input must extend for the switching stage to switch over.

The collector electrodes of both NPN transistors provide complementary switching stage outputs and are connected via one load resistor each to the more positive potential of the two supply voltage potentials which is also called level reference potential since it represents a digital qiE 9193 CML and CMOS H level.

To form the known CMOS-CML/ECL level converter, such a switching stage is supplied with a reference voltage potential which has a value which is in the middle between the two voltage values for the digital levels of the CMOS circuit technology (accordingly, the reference voltage potential has the value of - 2.5 volts with 0 volt for the digital H level and - 5 volts for the digital L level).

In addition, the load resistor of the control transistor must be omitted since the switching stage input is used as signal level converter input and the control transistor in its conducting state has already a very low collector-emitter voltage so that the saturation of the control transistor can only be reliably prevented without load resistor. It is known that a saturation of the control transistor leads to an unwanted increase in signal transit time.

Thus, the known signal level converter does not provide any complementary signal level converter outputs. For the same reason neither can a series circuit of several control transistors be implemented in the first amplifier branch for forming a logical AND combination. Several control transistors can also not be connected in parallel for forming a logical OR combination circuit since the maximum base-emitter voltage of a non-conducting control IE 9193___ transistor is exceeded with input signal levels of opposite phase.

It is therefore the object of the present invention to 5 develop a signal level converter according to the precharacterizing clause of Claim 1 in such a manner that the developed signal level converter can be modified with little expenditure so that logic functions can also be implemented in addition to level conversion.

According to the invention, the object is achieved by the characterizing features of Claim 1.

Compared with a bipolar transistor, a control transistor constructed as field-effect transistor provides the significant advantage with respect to the subject matter of the invention that its drain-source voltage can be as low as is desired without a saturation state occurring as in a bipolar transistor.

In a signal level converter constructed according to the invention it must be considered to be advantageous that the reference voltage potential does not necessarily have to have a value located in the middle between the two voltage values for the digital CMOS levels. The expenditure for forming the reference voltage potential can thus be reduced, especially since the reference voltage potential formed for establishing the switching threshold for switching stages of the CML or ECL circuit technology can also be used as reference voltage potential.

If the control transistor is constructed as P-channel 5 field-effect transistor, the switching threshold of the signal level converter is not influenced by the amplitude of the reference voltage potential.

Advantageous further developments of the invention are specified in the subclaims.

Since a signal level converter constructed in accordance with the invention can be expanded with little circuit engineering means for implementing logic functions, elaborate logic switching stages for forming these functions can be saved. As a result, the gate density in an integrated circuit is increased and the signal transit time and the power dissipation is reduced.

With a reference transistor constructed as field-effect transistor, it is not necessary to supply a reference voltage potential generated outside the signal level converter. Thus, there is also no need for components for generating the reference voltage potential.

In the text which follows, several illustrative embodiments of the invention are explained in greater detail with reference to the drawing, in which: 9193 Figure 1 shows a known CMOS-CML/ECL signal level converter , Figure 2 shows a CMOS-CML signal level converter 5 developed in accordance with the invention for forming a logical AND/OR combination of several CMOS input signals and having complementary signal level converter outputs, Figure 3 shows a CMOS-CML signal level converter 10 developed in accordance with the invention for forming a logical combination of two CMOS input signals having an enable input, Figure 4 shows a CMOS-CML signal level converter 15 developed in accordance with the invention for forming a l-of-3 decoder logic, Figure 5 shows a CMOS-CML signal level converter developed in accordance with the invention for forming a signal selection logic, Figure 6 shows a CMOS-CML signal level converter developed in accordance with the invention, using the level reference potential as reference voltage potential in a reference transistor constructed as field-effect transistor.

Figure 7 shows a CMOS-CML signal level converter developed in accordance with the invention for forming an Ί ΙΕ 9193 AND combination, using CMOS input signals as reference voltage potentials for reference transistors constructed as field-effect transistors, and Figure 8 shows a CMOS-CML signal level converter developed in accordance with the invention, using the CML output signal level available at a further signal level converter output as reference voltage potential for a reference transistor constructed as field-effect transis10 tor.

Figure 1 shows a circuit diagram for a known CMOS-CML/ECL signal level converter. The known signal level converter is formed of a switching stage of CML circuit technology and consists of a differential amplifier arrangement used as current switch comprising a first and a second amplifier branch fed from a common constant current source. To supply the switching stage with voltage, two supply voltage potentials VEE, VCC having a voltage value of - 5 volts and 0 volt respectively are provided. As a constant current source, a current source transistor ST constructed in the form of an NPN transistor is used the emitter electrode of which is connected via an emitter resistor to the more negative potential of the two supply voltage potentials VEE. The base electrode of the current source transistor Q is supplied with a constant voltage VSI the voltage value of which determines the collector current of the current source transistor Q in dependence on the emitter resistance. nrni-nn»· IE 9193 The first amplifier branch leads from the collector electrode of the current source transistor Q via the emitter-collector path of a control transistor ST constructed as NPN transistor to the more positive potential of the two supply voltage potentials VCC (0 volt) which, at the same time, is used as level reference potential for CMOS H levels and CML H levels.

The base electrode of the control transistor ST is used 10 as signal level converter input E-CMOS for CMOS input signal levels which are represented by the voltage values of the two supply voltage potentials VCC, VEE.

The second amplifier branch leads from the collector 15 electrode of the current source transistor Q via the emitter-collector path of a reference transistor RT constructed as NPN transistor and via a load resistor R, connected to its collector electrode, also to the more positive potential of the two supply voltage potentials VCC.

A tap connected to the collector electrode of the reference transistor RT and thus to the load resistor R forms a signal level converter output A-CML for CML output signal levels and, if necessary, is connected to the base electrode of an emitter follower constructed as NPN transistor. The collector electrode of the emitter follower is connected to the more positive potential of the two supply voltage potentials VCC, its emitter IE 9193 electrode is used as signal level converter output A-ECL for ECL output signal levels.

To the base electrode of the reference transistor RT a 5 reference voltage potential is applied which is generated with the aid of a bypassed CMOS inverter.

The bypassed CMOS inverter (kept apart from the signal level converter by means of a dashed line in the figure) consists of a series circuit of a P-channel and an Nchannel MOS field-effect transistor the drain and gate electrodes of which are connected with one another and exhibit a connecting line to the base of the reference transistor RT.

The bypassed CMOS inverter is used for generating a voltage value aligned in the middle between the two supply voltage potentials VCC, VEE (that is to say - 2.5 volts) so that the switching threshold of the signal level converter is exactly in the middle between the two voltage values for the digital CMOS level.

If the voltage value of the CMOS input signal is more positive by at least approximately 100 millivolts than the reference voltage potential, the current generated by the constant current source, for example 1 milliampere, completely flows through the first amplifier branch, if the voltage value of the CMOS input signal is more negative at least by 100 millivolts, the current ί IE 9193 completely flows through the second amplifier branch.

A CMOS H level at the signal level converter input E-CMOS thus does not lead to a voltage drop across the load resistor R in the second amplifier branch. At the signal level converter output A-CML, a CML H level is thus available. With a CMOS L level at the signal converter input E-CMOS, the reference transistor RT is conducting and a voltage drop of about 0.5 volts which amount corresponds to the CML L level, forms across the load resistor R which has, for example, an ohmic value of approximately 500 ohms.

When a CMOS H level is present at the signal level converter input E-CMOS, no saturation of the control transistor ST can occur because the collector-emitter voltage cannot become less than 0.7 volt (corresponding to the base-emitter voltage) and is thus far above the saturation voltage of approximately 0.2 volt because of a missing load resistor in the first amplifier branch.

Figure 2 shows a circuit diagram for a CMOS-ECL level converter developed in accordance with the invention which, like the known signal level converter according to Figure 1, consists of a differential amplifier arrangement used as current switch which is formed by means of a first and by means of a second amplifier branch fed from a common constant current source. The constant current source is constructed to be identical with that IE 9193 of the known signal level converter and is shown in the form of a current source symbol to simplify the drawing.

The first amplifier branch exhibits three control trans5 istors ST1, ST2, ST3 constructed as self-inhibiting Pchannel MOS field-effect transistors. Since these fieldeffect transistors, which will be designated as PMOS FETs in the text which follows, are constructed to be symmetrical with respect to their drain-source electrode arrangement, the electrode which is at the more positive voltage potential is always the source electrode.

In detail, the first amplifier branch is composed as follows. The current source SQ is connected to the drain electrodes of a second and of a third control transistor ST2, ST3. The source electrodes, which are connected to one another, of the second and third control transistor ST2, ST3 are conducted to the drain electrode of a first control transistor ST1 the source electrode of which exhibits a tap used as signal level converter output ACML and is connected via a further load resistor to the more positive potential of the two supply voltage potentials VCC. The gate electrodes of the three control transistors ST1, ST2, ST3 are used as signal level converter inputs El-CMOS, E2-CMOS, E3-CMOS for CMOS input signal levels.

The second amplifier branch consists of a reference transistor RT which is constructed as NPN transistor and IE 9193 the emitter electrode of which is connected to the current source SQ and the collector electrode of which is connected via a load resistor R to the more positive potential of the two supply voltage potentials VCC. In addition, there is a tap at the collector electrode of the reference transistor RT which is used as logically complementary signal level converter output A-CML for CML signal levels. To the base electrode of the reference transistor RT a reference voltage potential of a magnitude of about - 0.25 volt is supplied, which is also needed for defining the switching threshold in CML switching stages and, as a rule, is already available.

A logical combination of digital input values is imple15 mented by means of the series and parallel connection of the three control transistors ST1, ST2, ST3 since current only flows in the first amplifier branch when a CMOS L level is present both at the base electrode of the first control transistor ST1 and at at least one of the base electrodes of the second or third control transistor ST2, ST3. Since both amplifiers have a load resistor and a tap used as signal level converter output, the digital values at the two signal level converter outputs A-CML, A-CML/ are complementary to one another.

A CMOS H level at the gate electrode of a control transistor achieves a gate-source voltage of 0 volt and the relevant control transistor thus has an extremely high impedance. With a CMOS L level at the gate electrode the relevant control transistor is switched to conduct. If the current (e.g. 1 milliampere) flows from the constant current source SQ through the first amplifier branch, a voltage drop of 0.5 volt, which amount corresponds to a CML L level, forms across the load resistor of the first amplifier branch.

The control transistors ST1, ST2, ST3 are dimensioned with respect to their threshold point in such a manner that the switching threshold of the signal level converter approximately lies in the middle between the two voltage values for the digital CMOS signal levels.

Figure 3 shows a circuit diagram for a CMOS-CML signal level converter which is modified in accordance with the invention for carrying out logic functions and which has an enable input for supplying a CML signal level.

This signal level converter also consists of a first and a second amplifier branch fed by a common constant current source SQ. The first amplifier branch exhibits two parallel-connected control transistors ST1, ST2 constructed as PMOS FETs, for forming a logical OR combination, which control transistors are connected with their drain electrodes to the constant current source SQ and with their source electrodes to the more positive potential of the two supply voltage potentials VCC.

An input transistor ET constructed as NPN transistor is IE 9^93 ) connected with its emitter electrode to the constant current source SQ and with its collector electrode to the more positive potential of the two supply voltage potentials VCC and is thus connected in parallel with the first amplifier branch.

The base electrode of the input transistor is used as enable input E-CML of the signal level converter and has applied to it CML signal levels. The gate electrodes of the two control transistors ST1, ST2 are used as signal level converter inputs El-CMOS and E2-CMOS for CMOS signal levels.

The second amplifier branch is constructed to be identi15 cal with that of the signal level converter according to Figure 2.

In the case where a CML H level (0 volt) is present at the enable input E-CML of the signal level converter, no current flows through the reference transistor RT. There is thus a CML H level present at the signal level converter output A-CML of the second amplifier branch.

With a CML L level at the enable input E-CML, the current 25 of the constant current source only flows through the second amplifier branch (i.e. a CML L level occurs at the signal level converter output A-CML) when a CMOS H level is present at both signal level converter inputs El-CMOS, E2-CMOS. The signal level converter thus carries out a E9193 logical NOT-OR combination.

Figure 4 shows a circuit diagram for a CMOS-CML signal level converter, complemented in accordance with the invention with a l-of-3 decoding logic.

This signal level converter also exhibits a first and a second amplifier branch fed from a common constant current source SQ. In the first amplifier branch, a control transistor ST constructed as PMOS FET is arranged which is connected with its drain electrode to the constant current source SQ and with its source electrode via a load resistor to the more positive potential of the two supply voltage potentials VCC. A tap connected to the source electrode forms a signal level converter output Al-CML for CML signal levels. The gate electrode of the control transistor ST is used as a signal level converter input E-CMOS for CMOS signal levels.

The second amplifier branch is constructed to be identical with that of the signal level converter according to Figure 2 or Figure 3.

A third amplifier branch forms a bridge transistor BT constructed as NPN transistor, the emitter electrode of which is connected to the constant current source SQ and the collector electrode of which is connected via a third load resistor R3 to the more positive potential of the two supply voltage potentials VCC.

IE 9193 A tap at the collector electrode of the bridge transistor BT is used as third signal level converter output A3-CML for CML output signal levels.

The base of the bridge transistor BT is connected to a further current source SQ1 connected to the more negative potential of the two supply voltage potentials and via the emitter-collector path of an input transistor ET constructed as NPN transistor and operating as emitter follower to the more positive potential of the two supply voltage potentials VCC. To the base electrode of the input transistor ET, CML input signal levels are applied and the base electrode is used as selection input for the l-of-3 decoding logic formed by means of the signal level converter.

The input transistor ET in conjunction with the further current source SQ1 is used for not allowing the base voltage at the bridge transistor BT to become so positive in the conducting state, that is to say with a CML H level present, that the bridge transistor BT goes into saturation due to the voltage drop across the third load resistor R3.

For the better understanding of the logic function of a l-of-3 coding logic, a value table is specified in the text which follows which, in dependence on the digital input signal level combinations at the selection input E-CML and at the signal level converter input E-CMOS, IE 9193 specifies the digital output signal levels occurring at the signal level converter outputs Al-CML, A2-CML, A3CML.

E-CML L L H H C-CMOS L H L H Al-CML L H L H A2-CML H L H H A3-CML H H H L Figure 5 shows a circuit diagram for a CMOS-CML signal level converter constructed in accordance with the invention for forming a signal selection logic. This signal level converter consists of a base-differential amplifier with a first and a second base amplifier branch fed by a common constant current source, in which a subsequent differential amplifier is arranged in each case.

In the first base amplifier branch, a base control transistor BST constructed as PMOS FET is located the drain electrode of which is connected to the constant current source SQ and the source electrode of which is connected to the two amplifier branches of the subsequent differential amplifier arranged in the first base amplifier branch.

The second base amplifier branch exhibits a base reference transistor BRT constructed as NPN transistor, the IE 9193 emitter electrode of which is connected to the constant current source SQ and the collector electrode of which is connected to the two amplifier branches of the subsequent differential amplifier arranged in the second base amplifier branch.

The subsequent differential amplifiers are of identical construction and in each case consist of a first and a second amplifier branch with a control transistor ST1; ST2, constructed as PMOS FET in the first amplifier branch and a reference transistor RT1; RT2, constructed as NPN transistor, in the second amplifier branch.

In the subsequent differential amplifier of the first base amplifier branch, the drain electrode of the control transistor ST1 is connected to the emitter electrode of the reference transistor RT1 and connected to the source electrode of the base control transistor BST. Analogously to this, the drain electrode of the control transistor ST2 in the subsequent differential amplifier of the second base amplifier branch is connected to the emitter electrode of the reference transistor RT2 and connected to the collector electrode of the base reference transistor BRT.

The control transistors ST1, ST2 are connected with their source electrodes to the more positive potential of the two supply voltage potentials VCC. The reference transistors RT1, RT2 of the two subsequent differential IE 9193 amplifiers are connected to one another at their collector electrodes and also connected via a load resistor R to the more positive potential of the two supply voltage potentials VCC. A tap at the collector electrode of the reference transistors RT1, RT2 and thus at the load resistor R is used as signal level converter output A-CML for CML signal levels.

The base electrodes of the two reference transistors RT1, 10 RT2 in the subsequent differential amplifiers are connected to one another and a first reference voltage potential VSVX is applied to them the voltage value of which is approximately between the two voltage values for the digital CML levels, that is to say approximately - 0.25 volt.

To the base electrode of the base reference transistor BRT, a second reference voltage potential VSVY is supplied, the voltage value of which, compared with that of the first reference, voltage potential VSVX, is more negative at least by the saturation voltage of the base reference transistor BRT, that is to say is approximately - 1.0 volt.

The gate electrode of the base control transistor BST is used as selection input E-CMOS for CMOS signal levels and the gate electrodes of the control transistors ST1, ST2 belonging to the subsequent differential amplifiers are used as signal level converter inputs El-CMOS, E2-CMOS IE 9193 - 20 for CMOS signal levels.

For understanding of the logic function of the signal selection logic implemented in the signal level converter, a value table is listed in the text which follows which, in dependence on the digital input signal level combinations at the selection input E-CMOS and at the two signal level converter inputs El-CMOS, E2-CMOS, specifies the associated digital output signal level at the signal level converter output A-CML.

E-CMOS El-CMOS E2-CMOS A-CML L L L H L L H H 15 L H L L L H H L H L L H H L H L H H L H 20 H H H L This value table shows that, with a L level at the selec- tion input E-CMOS, the level values present at the signal level converter input El-CMOS and, with a H level at the 25 selection input E-CMOS , the level values present at the signal level converter input E2-CMOS, are switched through, logically inverted, to the signal level converter output A-CML.

IE 9193 Figure 6 shows a circuit diagram for a CMOS-CML signal level converter provided in accordance with the invention with a reference transistor constructed as field-effect transistor. This signal level converter also consists of a first and a second amplifier branch fed by a common constant current source. The first amplifier branch exhibits, for forming a logical AND combination, two series-connected control transistors ST1, ST2 constructed as PMOS FETs, the gate electrodes of which are used as signal level converter inputs El-CMOS, E2-CMOS for CMOS signal levels.

In the second amplifier branch, a reference transistor RT, constructed as self-inhibiting N-channel or MOS FET, abbreviated N-MOS FET in the text which follows, is arranged the source electrode of which is connected to the constant current source SQ and the drain electrode of which is connected via a load resistor R to the more positive potential of the two supply voltage potentials VCC. A tap at the drain electrode, and thus at the load resistor R, is used as signal level converter output ACML for CML signal levels. The gate electrode of the reference transistor RT is connected to the more positive potential of the two supply voltage potentials VCC.

The current of the constant current source SQ only flows through the first amplifier branch when an L level is present at both signal level converter inputs El-CMOS, E2-CMOS. This is because the two control transistors ST1, IE 9193 ST2 then have a low impedance and, at the same time, the gate-source voltage at the reference transistor RT has dropped below the threshold point of the reference transistor RT as a result of which the reference transis5 tor RT becomes high-impedance.

If a H level is present at one of the signal level converter inputs El-CMOS, E2-CMOS, the first amplifier branch has a high impedance and the gate-source voltage at the reference transistor RT is above the threshold point of the reference transistor RT. A voltage value of - 0.5 volt corresponding to a CML L level occurs at the signal level converter output A-CML.

Figure 7 shows a circuit diagram for a CMOS-CML signal level converter provided with complementary reference transistors according to the invention. In distinction from the signal level converter of Figure 6, each control transistor ST1, ST2 in the first amplifier branch in this signal level converter is unambiguously associated with a reference transistor RT, constructed as N-MOS FET in the second amplifier branch. The switching network formed by the reference transistors RT1, RT2 is constructed to be complementary to that of the control transistors ST1, ST2 . In the present example, the control transistors ST1, ST2 for forming an AND combination are series connected which is why the reference transistors RT1, RT2 are connected in parallel for forming the complementary switching network, that is to say for an OR combination.

IE 9193 - 23 The gate electrodes of the control transistors ST1, ST2 are used as signal level converter inputs El-CMOS, E2CMOS for CMOS signal levels and each reference transistor RT1, RT2 is connected with its gate electrode to that of its associated control transistor ST1, ST2.

'I The current of the constant current source SQ only flows through the first amplifier branch when L levels are present at the two signal level converter inputs El-CMOS, E2-CMOS because the gate-source voltage at the two reference transistors RT1, RT2 then has become 0 as a result of which these become high-impedance.

In the case where at least one CMOS H level is present at the signal level converter inputs El-CMOS, E2-CMOS, the first amplifier branch has a high impedance and the current completely flows through the second amplifier branch since at least one of the reference transistors RT1, RT2 becomes low-impedance due to a high gate-source voltage.

In comparison with the signal level converter according to Figure 6, the signal level converter according to Figure 7 has a steeper transfer curve which is thus more advantageous for the switching behaviour.

Figure 8 shows a circuit diagram for a CMOS-CML signal level converter provided with a reference transistor constructed as field-effect transistor in accordance with IE 9193 - - 24 the invention. The configuration of this signal level converter is similar to the signal level converter of Figure 6. Compared with the signal level converter according to Figure 6, a load resistor Rl is provided in the first amplifier branch, which connects the series circuit of the control transistors ST1, ST2 and thus the source electrode of the control transistor ST1 facing away from the constant current source SQ to the more positive potential of the two supply voltage potentials VCC. In addition, there is a tap at the load resistor Rl and thus at the source electrode of the control transistor ST1 which is connected to the gate electrode of the reference transistor.

If at least one H level is present at one of the two signal level converter inputs El-CMOS, E2-CMOS, the current of the constant current source SQ flows through the second amplifier branch since the voltage present at the gate electrode of the reference transistor RT cor20 responds to the more positive potential of the two supply voltage potentials VCC and the reference transistor RT becomes low-impedance due to the source electrode being at the more negative potential.

In the case where L levels are present at both signal level converter inputs El-CMOS, E2-CMOS, the current of the constant current source SQ flows through the first amplifier branch and the reference transistor RT becomes high-impedance due to its gate voltage becoming more negative.

Having regard to the quality of the transfer curve, this signal level converter is situated approximately between that of the signal level converter according to Figure 6 and that according to Figure 7.

In conclusion, it must be pointed out that the signal level converters shown in the drawing only represent illustrative embodiments and can be expanded for forming any logic combinations. Instead of each control transistor constructed as field-effect transistor, a parallel AND/OR series circuit of control transistors can be provided.

Although the control transistors in the illustrative embodiments are constructed as self-inhibiting P-channel MOS field-effect transistors, the control transistors can also be constructed, for example, as self-conducting N20 channel MOS field-effect transistors.

Each signal level converter output A-CML for CML signal levels can be followed by an emitter follower for forming signal level converter outputs A-ECL for ECL signal levels.

Claims (10)

1. Patent claims

1. Signal level converter for converting CMOS logic input signal levels to CML or ECL output signal levels, respectively, using a differential amplifier arrangement used as current switch comprising a first amplifier branch which exhibits a control transistor the control electrode of which is used as signal level converter input for CMOS input signal levels and having a second amplifier branch in which a reference transistor is located the control electrode of which is connected to a reference potential, characterized in that the control transistor (ST) is constructed as field-effect transistor.

2. Signal level converter according to Claim 1, characterized in that the first and/or second amplifier branch exhibits a load resistor (Rl) which is connected at the input to the level reference potential and is connected at the output to a tap which is used as signal level converter output (A-CML/) for CML output signal levels or is connected, respectively, to an emitter follower for forming a signal level converter output for ECL output signal levels.

3. Signal level converter according to Claim 1 or 2, characterized in that the first amplifier branch exhibits at least one further control transistor constructed as field-effect transistor, the drain-source path of which, IE 9193 - 27 for forming a logical OR combination, is connected in parallel with that of the control transistor or, for forming a logical AND combination, is connected in series and the gate electrode of which is used as further signal level converter input for CMOS input signal levels.

4. Signal level converter according to Claim 1 or 3, characterized in that the collector-emitter path of an input transistor ET constructed as bipolar transistor is connected in parallel with the first amplifier branch, the base electrode of which is used as enable input E-CML of the signal level converter for CML input signal levels.

5. Signal level converter according to one of the preceding claims, characterized in that, for forming a 1of-3 decoding logic, a third amplifier branch is provided which is formed by a bridge transistor (BT) constructed as bipolar transistor and a third load resistor (R3) connected to the level reference potential, in that the connection facing away from the level reference potential of the third load resistor (R3) exhibits a tap which is used as third signal level converter output (A3-CML) for CML output signal levels or, respectively, is used via an emitter follower as third signal level converter output for ECL output signal levels, in that the base electrode of the bridge transistor (BT) is connected to a further current source (SQ1) and is connected via the switching path of an input transistor (ET) constructed as bipolar IE 9193 *, V transistor and connected as emitter follower, and in that the base electrode of the input transistor (ET) is used as selection input (E-CML) for CML input signal levels.

6. Signal level converter according to one of the preceding claims, characterized in that, for forming a signal selection logic, the first and/or second amplifier branch is connected via one subsequent differential amplifier arrangement each, constructed to form a signal level converter according to one of the preceding claims, to the level reference potential.

7. Signal level converter according to at least one of Claims 1 to 6, characterized in that the reference transistor is constructed as field-effect transistor and that the level reference potential is used as reference potential.

8. Signal level converter according to at least one of Claims 1 to 6, characterized in that the control transistor or transistors are constructed as P-channel field-effect transistors, in that each control transistor is associated with a reference transistor constructed as N-channel field-effect transistor, in that the reference transistors form a switching network which is complementary to that of the control transistors and in that the gate electrode of each control transistor is connected to its associated reference transistor. IE 9193 ?.--Signal level converter according to at least one of Claims 1 to 6, characterized in that the reference transistor is constructed as field-effect transistor and that its gate electrode is connected to the tap of the load resistor arranged in the first amplifier branch.

9.

10. A signal level converter according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings .