IE43367B1 - Method and apparatus for establishing a plurality of simultaneous conferences in a pcm switching system - Google Patents

Abstract

1529106 Automatic exchange systems NORTHERN TELECOM Ltd 2 April 1976 [23 April 1975] 13469/76 Heading H4K A pcm conference circuit is arranged to deal simultaneously with a plurality of three or more party conferences, the circuit introducing a delay of two frames. An interface and control 10 extracts from the pcm highways of the system pcm speech samples in time slots concerned with conference calls and presents the speech samples over an 8 channel serial highway to the conference circuit in isochronous (interleaved bit) form, i.e. each channel comprises 32 bits, with the first bit of each of 32 pcm words being transmitted in channel 0, and the eighth bit in channel 7 etc. The conference circuit includes two 32 word, 8 bit, RAM memories I and II, one of the memories being fed with the incoming serial bit stream during one frame, whilst information fed into the other memory during the previous frame is being processed, the units MUX, 11, 111, enabling the 32 speech samples to be stored in the RAM's in 8 bit parallel form. The processing frame of the conference circuit is divided into eight periods, period 0 not being used. During period 1 each 8 bit word in the RAM e.g. RAM1 written during the previous frame is used to address a read only memory 14 to convert the word into a 14 bit linear PCM word, and each linear word is added to a location of an accumulator 16 corresponding to the conference to which the word relates. During period 2, the 8 bit words are again supplied to address ROM 14, but with their sign bit changed such that a 14 bit word in 2's complement form is produced at the output of ROM, 14. This word is then added to the accumulator contents value for the corresponding conference (hence effectively subtracting the word of the subscriber) and the first 8 bits of the total are written into the location of RAM I corresponding to the read 8 bit word and the remaining 6 bits are stored in a corresponding location of an additional memory RAM III. The accumulator contents remain unchanged. During period 3, the 14 bit words stored jointly in RAM I and RAM III are converted back into companded 8 bit form using compressor 18 and are fed back into the corresponding locations of RAM I. During periods 4-7 RAM III and accumulator 16 are cleared, and in the following frame the contents of RAM I are read out via interface 10 to the subscriber time slots, thereby providing each subscriber of a conference with a PCM word representing the total speech of all the other subscribers of the conference. Where the number of conferees is between 6 and 12 the ROM 14 may be enabled to produce attenuated linearly coded words. The circuit may also be switched to a public address mode by causing the ROM 14 to produce words comprising logical 1's for all except a designated speaker.

Description

The present invention relates to time division switching systems in genera' and to conferencing in pulse code modulation (PCM) systems in particular.

In a time division multiplexing system sampled or encoded speech signals originated by a subscriber occupy assigned time slots in a repetitive, ordered group of time slots termed a frame. Connection of two subscribers is achieve' by a number of techniques the end result of which is that the information conta' in the respective timeslots of the two subscribers are bilaterally exchanged. Should three or more subscribers desire simultaneous multilateral connection, i a conference connection, more complicated processing of the timeslot informatioi is necessary.

Given a PCM system, the obvious way to realize a conference between subscr' is to algebraically sum the PCM words of the participants except one, and to transmit the sum to the one participant excepted. If this procedure is perform! once every frame for each conference participant, a conference connection would have been established. Should the PCM signals be a result of nonlinear encodini (which is usually the case), it would be necessary to linearize the PCM words before they can be summed and to convert each resultant sum to the nonlinear co< again prior to its transmission to the appropriate conference participant. Sue) a procedure is exemplified in British Patent Specification No. 1,201,967.

It is because of the foregoing complications and the required expensive circuitry that the prior art, for example U.S. Patent 3,699,264 issued October 17, 1972 to Pitroda et al, generally shies away from such techniques. In the -243367 Pitroda patent a simpler approach is chosen; namely, the participant with the numerically largest binary PCM word is chosen as speaker by a multilateral comparator circuit. While this simple approach may be less costly, it is often inadequate in that it does not permit natural multilateral conferencing.

The present invention provides a method and circuit for realizing conference connections in a PCM switching system, that permits sharing of that circuit by a plurality of simultaneous conferences, each having an arbitrary number of participants limited in principle only by the number of channels within one frame. However, other practical limitations will be discussed later on.

According to the invention, there is provided in a time division switching system wherein a plurality of incoming channels carry pulse code modulated speech signals and are arranged in time sequential frames, a method for establishing a plurality of simultaneous conferences each between at least three predetermined channels, comprising storing an incoming frame; simultaneously processing the stored frame and storing the next incoming frame; storing intermediate processing results for each conference to be established; storing final processing results for each channel; and transmitting the final results starting with the beginning of the frame following said next incoming frame and ending with the end thereof.

PCM systems often utilize companded or nonlinear encoding, hence the processing of the stored frame would not, in most systems, consist only of arithmetric operations. Rather, the contents of each channel, before arithmetic processing, must be expanded or linearized. After the arithmetic processing is completed the final result for each channel is reconverted to the nonlinear form, and then stored finally for transmission.

The method outlined above introduces a minimum delay of two full frames.

The first delay occurs during the storing of an incoming frame, while the second frame delay occurs in processing the stored frame. While the actual processing may not require or last for one full frame the final result must be kept in storage that long before they can be transmitted. It should be noted that for first level PCM systems, such as the 24 channel Tl system in North America or the 32 channel system in Europe one full frame is more than sufficient in -343367 duration to permit complete processing of a frame with present state of the a processing circuitry using off the shelf components.

An apparatus, according to the present invention, for establishing a plurality of simultaneous conferences each between at least three predetermi ni channels in an incoming frame of pulse code modulated speech signals arranged individual timeslots constituting said frame, comprises two interchangeable storage means, each adapted to receive and store said incoming frame, one of 1 two storage means receiving said incoming frame and simultaneously transmittir its previously stored contents, while the other storage means cooperating with arithmetic processing means for processing the stored information and for storing therein the result of said processing; said two interchangeable storag means and said arithmetic processing means being responsive to timing and control means for clocking, initiating and terminating of operations, includin interchanging said two interchangeable storage means at the end of every incoming data frame.

An example embodiment of the invention will now be described in conjunctii with the accompanying drawings in which: Figure 1 is a block schematic of a conferencing circuit according to an embodiment of the present invention; Figure 2 is an illustration showing subperiods of a PCM frame in relation: at various points of the circuit in Figure 1; and Figure 3 is a portion of the circuit in Figure 1 shown in functional detai Figure 1 shows a block diagram of the example embodiment of the present invention. An interface and control unit 10, instructed from the Central Proce ing Unit (CPU) of the switching system, selects predetermined timeslots from the PCM highways of the system and assembles them serially into a serial PCM frame, which is the input to the conference circuit. The selected timeslots ar those occupied by channels involved in a conference. The serial PCM input accesses via multiplexer switches 11 and IT one of two random-access memories RAMI and RAMII. The one memory that receives the PCM input is termed the In/Ou memory, and is shown in Figure 1 to be the memory RAMI. While the In/Out memory RAMI is receiving the serial PCM input, it is simultaneously outputting -443367 its contents to an Ιη/Out multiple bit latch 12, which in turn is clocked to deliver a serial PCM stream to the interface and control unit 10, that during predetermined timeslots accesses one of the PCM highways of the system.

The operational memory RAMII, containing one frame of PCM data, accesses a read-only memory expander (nonlinear-to-linear PCM code converter) 14 via an operational latch 13. The linear output of the expander 14 is one input to an adder 15, the other input of which is the output of any one of independent storage locations in an addressable accumulator store 16. The storage location in the accumulator 16 is overwritten by the addition result which accesses the accumulator 16 via an accumulator latch 17. The output of the accumulator latch is also the input to an additional random-access memory RAMIII and a multiplexer switch 19, which connects either that output or the output of a compressor (1 inear-to-nonlinear PCM code converter) 18 to the multiplexers 11 and IT, which in turn access either one of the memories RAMI and RAMII. The compressor receives its input from the operational latch 13 and from the additional memory RAMIII.

In Figure 1 all control connections from the control unit 10 were omitted in order not to clutter the schematic. The control unit 10 controls the multiplexers 11 and IT and 19, addresses the memories RAMI, II and III and the accumulator 16, and generally times the function of the remaining components of the circuit. Its functions will become apparent in the context of the description of the circuit operation. The circuit is also clocked by two clocks, one at 2.048 MHz is the normal bit rate clock of the switching system, and the second is a clock at twice that rate and synchronous therewith. The second clock is necessary to be able to divide the basic system timeslot into four quarters and perform certain consecutive operations within one timeslot, that would otherwise require two time slots or more. In addition, there is also the system frame synchronization clock.

The general characteristics of the PCM system of the example embodiment are as follows: Number of channels 32 -5£3367 NUmber of bits/channel Coding format Linear equivalent Multiplexing format Bit rate (MSB is sign bit) companded PCM, a-law («=255) bits including a sign and a fraction bit isochronous (interleaved) 2.048 Mbits/sec.

In Figure 2 of the drawings one serial PCM frame is shown to have eight bit groups 0 to 7, with each bit group having 32 timeslots 0 to 31. The bits of each channel are processed' in the conference circuit in parallel. The Ιη/Out memory, therefore, while receiving the isochronous PCM frame serially must present the j eight bits of each channel in a single timeslot for processing. This is accomplished by means of the multiple bit feedback path from the output of the Ιη/Out latch 12 lo the input of the multiplexers 11 and 11' and through them to the input of the Ιη/Out memory. The word bits of the channels become available in parallel at the output of the operational memory so that by addressing the timeslots of that memory consecutively, all channels are output in a single bit group period; this is also illustrated in Figure 2.

One processing cycle of the conference circuit has eight periods 0 to 7, during each of which each channel is available once. In fact, only three periods of a frame are essential for processing all channels in the conference circuit. Briefly summarized, one processing cycle proceeds as follows: Period 0: No operation Period 1: The 8 bit PCM channel word in each timeslot is linearized and and added to the accumulator storage location associated with its conference (after each addition, the sum is stored back in the accumulator location); Period 2: The PCM word in each timeslot is linearized and subtracted from the accumulator storage location associated with its conference; the resultant 14 bits are stored partly in the operational memory replacing its original contents, and the remaining 6 bits are stored in the additional memory, the accumulator contents are unchanged; Period 3: The 14 linear bits of each channel in the operational and -643367 additional memories are converted to the companded PCM format in the compressor and stored back into the operational memory replacing the contents from the previous step; and Periods 4 to 7: The additional memory and the accumulator are cleared. At the end of the frame (bit 31 of period 7) the In/out memory becomes the operational memory and vice versa.

The processing routes in the above cycle are indicated in the circuit of Figure 1. The heavily traced connections starting from the operational memory RAMII and ending in the accumulator 16 correspond to processing during period 1; the first route extended by the doubly traced connections ending in the memories RAMII and III correspond to processing during period 2: and finally the dotted connections correspond to processing during period 3.

Referring now to Figure 3 in conjunction with Figure 1, the operation Of the conference circuit will be discussed in more detail. The circuit captures a full frame of PCM serial data supplied by the interface and control unit 10.

Each channel extracted from the PCM highways of the system is associated with a conference. Since the multiplexing format of the present system is isochronous (i.e. the channel bits are interleaved rather than lumped together), the 8 bits of a channel are reconfigured to be available in parallel for processing. To illustrate how this is accomplished, reference is made to Figure 3 which shows the connections of the memories RAMI and II with the associated latches 12 and 13 as well as multiplexer switches 11 and 11' in functional detail. The In/Out memory and the operational memory (RAMI and RAMII in Figures 1 and 3, respectively) are organized as 32 word by 8 bit memories. They are addressed by timeslot number, being read during the second quarter of a timeslot and written during the third quarter. This arrangement permits the simple parallel connection of the outputs of the memories without the need of an external multiplexer switch. The latches 12 and 13 then permit the readout data to be held as long as necessary.

As may be ascertained from Figure 3, the data is skewed so that data read from bit position X of timeslot Y is written into bit position X+l of the same timeslot. Bit position 0, timeslot Y at the input of RAMI is receiver of serial PCM input data; while bit position 7 of the timeslot Y at the output of RAMI -743367 transmits the previously (during the previous frame) processed PCM data serially.

By the end of a frame, the data is arranged in the Ιη/Out memory (RAMI in Figure 3 such that all 8 bits of a timeslot (i.e. channel) appear in parallel at the output of that memory when it becomes the operational memory. Hence, clocking the operational memory through 32 timeslots (=1 bit group) produces every channel sample once at the output, (the readout is nondestructive).

In Figure 3 the multiplexer switches 11 and IT are shown functionally in one unit; the dotted lines indicate the alternate position of connections, whereby the memory RAMI becomes the operational memory and the memory RAMII the In/Out memory. At the end of every frame of incoming serial PCM data, i.e. at the end of timeslot 31 of bit group 7, the multiplexers 11 and IT are switched to their alternate position, interchanging the memories RAMI and II. Due to the previously explained reading arrangement of the memories RAMI and II, no such interchange is necessary at the output (provided, that is, memory units chosen make this possible) The data captured in the previous frame is presently available for processing in the operational memory RAMII. During group bit period 1 the 8 bit channel word from a timeslot is latched at the end of the first quarter of the timeslot in the operational latch 13. This data addresses the ROM expander 14, which expander produces a 14 bit linear word including a fraction bit and a sign bit. Such expanders are well known in the art and the only requirement placed thereon is that they produce the linear word in a single clocking operation. The linear word is added in the adder 15 to the contents of the storage location for the associated conference in the accumulator 16. The result of the addition is latched in accumulator latch 17 at the end of the third quarter of the timeslot. The new sum is then written in the accumulator 16 into the same location. Note that during any one timeslot, the accumulator is addressed by a 4-bit conference number bus which causes only the appropriate conference storage location to be accessible for read/write operations. By the end of bit group period 1, each conference location in the accumulator 16 contains the total sum of the linear words of channels participating in that conference. (The accumulator storage locations have a capacity for 16 bit words in order to accommodate any overflow -8over 14 bits as a result of addition).

In the following bit group period 2, the above process is repeated, except that instead of adding, the channel word is subtracted from the associated conference total. The subtraction is achieved by changing the sign bit in the 8 bit input word to the ROM expander 14, which produced (in response to the new address) the 2's complement of the linear word as output. The change of the sign bit (which is the most significant bit) is initiated by a command from the controller 10 that is sustained during bit group period 2. The result of adding the 2's complement of the original word to the total conference words in the accumulator 16 plus 1, is equivalent to the result of subtracting the original word from the total conference words.

The 8 most significant bits of the subtraction result are written into the same timeslot location of the operational memory RAMII erasing the previous contents of that location, while the remaining 6 bits of the 14 bit word are written into a corresponding location in the additional memory RAMIII. At the end of bit group period 2, the memories RAMII and III contain the linear conference words.

During bit group period 3, in each timeslot, the 14 bit linear conference words stored in the memories RAMII and III are converted to the nonlinear form (i.e. compressed) in the compressor 18. Again, such compressors are well known in the art and the function of compression may be partly or wholly accomplished by table look-up as in the case of the expander 14. During bit group periods 3, the multiplexer switch 19 connects multiplexers 11 and IT with the output of the compressor 18 rather than with the accumulator latch 17 as during other bit group periods. The compressed 8 bit PCM words are now stored into the operational memory RAMII by overwriting the therein previously stored information.

Thus, at the end of bit group period 3, the processing of the PCM words has ended. During the following periods the accumulator 16 is cleared.

At the end of bit group period 7, i.e. at the end of a frame, multiplexers 11 and 11' are switched to the alternate position by a command from the controller 10 exchanging the memories RAMI and II. The whole cycle of processing is repeated on the new frame. -913367 As mentioned before, all timeslots not associated with a conference are assigned conference number zero by the controller 10. This is simply achieved by not addressing the accumulator 16 during these channels, so that the four addressing bits are all zero. During these Same timeslots the output of the compressor 18 is forced to zero so that the memory RAMII would not contain any data in these timeslot locations. Of course, the suppression of data during unused timeslots could be achieved at any other suitable point In the circuit.

In fact, the controller 10 itself accesses the PCM highway only at those timeslots participating in a conference.

Depending on the system in which the conferencing circuit is used, it may be necessary to delay the serial PCM output from the In/Out latch 12 by one or. more timeslots. This is easily accomplished by a delay memory, which may be integral with the interface and control unit 10.

It was mentioned earlier that practical limitations may restrict the number of conferees in any single conference. One such limitation is the trans-hybrid loss in the line circuits of the conferee stations. There is, however, no welldefined cut-off number of conferees beyond which operations would be impossible.

One way to mitigate some of the limitations (trans-hybrid loss, overload, etc.) is to introduce attenuation if the number of conferees exceeds a predetermined number. This could be achieved in the ROM expander 14, which would have sufficient storage capacity to generate either of two sets of linear words, one without attenuation and one (or more) with attenuation. It has been found that a 6 dB attenuation is suitable for between 6 and 12 conferees per conference. A one bit command from the control unit 10 is sufficient to instruct the ROM expander 14 whether the unattenuated linear word, or that with 6 dB attenuation should be retrieved. Both sets of linear words (two corresponding to one of 256 possible addresses) are, of course, permanently stored in the ROM expander 14.

The conference circuit may be also used in a public address mode. This is accomplished by a one bit command from the control unit 10, which forces the output of the ROM expander 14 to logical 1's, during all timeslots in a conference except that of the announcer. The lowest order carry in the adder 15 is also -104 3367 forced to logical 1. The announcer's word is thereby unchanged in the conference location in the accumulator 16. This operation is simply illustrated in the following example: announcer's word in the accumulator 16: add all l's from the expander 14 (overflow over 14 bits is ignored) add carry + 1 announcer's word unchanged 00101101011001 11111111111111 0 10 ΪΊ 0 10 1 10 0 '0' 00101101011001 Hence only the announcer's word reaches the listener.

Claims (16)

1. In a. time-division switching system wherein a plurality of incoming channels carry pulse code modulated speech signals and are arranged in time sequential frames, a method for establishing a plurality of simultaneous conferences each between at least three predetermined channels, comprising: storing an incoming frame; Simultaneously processing the stored frame and storing the next incoming frame; storing intermediate processing results for each conference; storing final processing results for each channel; and transmitting the final results starting with the beginning of the frame following said next incoming data frame and ending with the end thereof.

2. The method of claim 1 wherein said final processing results are stored by replacing said incoming frame stored in its original store.

3. The method of claim 1 wherein said incoming frame is stored in a first store, said next incoming frame is stored in a second store, and wherein the final processing results replace the incoming data frame in said first store.

4. The method of claim 3 wherein said first and second stores are interchangeable and are interchanged at the end of each one of said time sequential frames.

5. An apparatus for establishing a plurality of simultaneous conferences each between at least three predetermined channels in an incoming frame of pulse code modulated speech signals arranged in individual timeslots constituting said frame, comprising two interchangeable storage means, each adapted to receive and store said incoming frame, one of the two storage means receiving said incoming frame and simultaneously transmitting its previously stored contents, while the other storage means cooperating with arithmetic processing means for processor the stored information and for storing therein the result of said processing; said two interchangeable storage means and said arithmetic processor means being responsive to timing and control means for clocking, initiating and terminating of operations therein; and said initiating and terminating -1243367 of operations including interchanging said two interchangeable storage means substantially at the end of every incoming data frame.

6. The apparatus of claim 5, said timing and control means including an alterable memory for associating each number of predetermined channels with one conference.

7. The apparatus of claim 5, said arithmetic processing means adapted to respond to information associating each number of predetermined channels with one conference.

8. The apparatus of claim 6 for establishing conferences in a time-division switching system wherein the speech signals are encoded in binary pulse code modulation (PCM), and further comprising: interface means for arranging said predetermined channels in time sequential frames; said arithmetic processor means alternately responsive to one of said first and second storage means to produce a conference signal for each of said predetermined channels stored therein; first switching means for diverting said conference signals to one of said two interchangeable storage means to be stored therein; second switching means for interchanging said two interchangeable storage means at the end of each of said frames.

9. The apparatus of claim 8 in a switching system wherein said encoding in binary PCM being nonlinear, further comprising: non!inear-to-1inear PCM convertor means alternately responsive to the contents of one of said first and second storage means and driving said arithmetic processor means; and 1inear-to-nonlinear PCM converter means responsive to the output of said arithmetic processor means and driving said first switching means.

10. The apparatus of claim 9 further comprising additional storage means for storing the output of said arithmetic processor means prior to its transmittal to said linear-to-nonlinear PCM converter means.

11. The apparatus of claim 10 wherein said arithmetic processor means comprises -1343367 a parallel binary adder adapted to add two binary linear PCM words, and an addressable memory having a plurality of separate storage locations each adapted to receive and store a linear PCM word having a predetermined minimum number of bits; said addressable memory being addressed by said control means by a conference address during processing of any channel associated with that conference.

12. The apparatus of claim 11, said nonlinear-to-1inear converter being prestored conversion tables, and responds to an input PCM word by outputting its linear equivalent.

13. The apparatus of claim 12, said prestored conversion tables also containing the 2's complement of said linear equivalents and said 2's complement is output in response to a signal from said control means.

14. The apparatus of claim 13, said prestored conversion tables also containing an attenuated version of said linear equivalent and of said 2‘s complement.

15. The apparatus substantially as described herein in conjunction with the accompanying drawings.

16. A method for establishing a plurality of simultaneous conference connections substantially as hereinbefore described.