IE42621B1 - Digital multifrequency signals receiver - Google Patents

Abstract

1492310 Signal receivers INTERNATIONAL STANDARD ELECTRIC CORP 2 Dec 1975 [18 Dec 1974] 49404/75 Heading G4H [Also in Division H4] A digital receiver for a multifrequency signal has a digital filter formed by a processor to act as a band-pass filter and as two filters for each possible frequency the first having a wider pass band than the second, the outputs of the possible-frequency filters being rectified, timeaveraged and supplied to a digital recognition device which looks for signal beginning and signal end in turn. A digital filter receives a sequence of digitized samples of a 2-out-of-6 multifrequency signal and includes a special-purpose processor which carries out on a time-shared basis the calculations to simulate a network as in Fig. 1 of secondorder filter cells (shown as squares), cells C1-C4 forming a wide-band-pass filter and the pairs of cells C11-C12, C21-C22,...C61-C62 relating to the 6 possible frequencies respectively, the second cell of each pair having a narrower pass-band than the first. The twelve outputs aij shown (from C11-C62) are rectified (by dropping the sign bit) and time-averaged (over a period T1=n1.T where T is the sample period) to obtain quantities aij k where k represents the period T1, and these quantities are then stored in a random-access memory 5 of a digital processor (Fig. 5) which also includes a programme control unit 16 (which also supplies weights and other constants), an ALU 6 with buffer register 8, a ROM 10, a shift circuit 14, an output register 15 and gates 9, 11, 12, 17, The ALU has an output V to specify the sign of the difference when operating as a subtractor, and an output W which is 1 when the result from the ALU is all-zeroes. The processor (Fig. 5) performs the following operations. It operates in a signal appearance recognition phase until a multi-frequency signal is recognized as present, and then in a signal disappearance recognition phase until it is recognized as being absent, and so on. In the signal appearance recognition phase; The quantities a# k are weighted to form quantities A# k . In each of k1 consecutive intervals T1, the greatest of the six quantities A# k is taken, and the average Mk of these over the k1 intervals is computed and, provided this average is not less than a predetermined constant, two threshold values are obtained by multiplying it by constants. The six quantities A# k are thresholded against each threshold. Two should be above the higher threshold and the rest below the lower, to constitute a multifrequency signal, a signal being recognized as present if the same one is so detected in each of k2 consecutive time intervals T1 (or in k3 of the k2) and provided a transient state is absent. A transient state is taken to be present if any of the said greatest of the quantities A# k differs proportionately too much from M k . In the signal disappearance recognition phase: The quantities a# k are weighted to form quantities A# k . A threshold value is obtained by multiplying the most recent value Mk obtained in the preceding appearance recognition phase by a constant. The quantities A# k are thresholded against this threshold. Provided they are all below it for each of k4 consecutive intervals T1, disappearance of the multifrequency signal is taken to have been recognized. The multifrequency code may consist of one of four high frequencies together with one of four low frequencies, and in this case there would be a band-pass filter for each of the two groups of frequencies, and M k and the transient state test could be based on their outputs instead of on the outputs of the individual-frequency filters (to improve protection against interfering speech signals). Applications to telephone systems are mentioned. A number of different channels could be processed in succession.

Description

This invention relates to a receiver using digital techniques to detect digital signals each representing a combination of several frequencies, and especially to the recognition device of such a receiver for the detection of multifrequency (MF) signals by digital techniques in such a way as to eliminate confusion with noise.

An MF receiver is used, inter alia, in automatic telephone central offices using MF signalling codes, e.g. the CCITT No. 5 or R2 codes for signalling between central offices, or the so-called pushbutton” code for signalling between a subscriber's set and a central office. Such codes may consist of a combination of two frequencies selected from among six or eight frequencies.

An MF receiver is usually in two main sections: a first or filtering section, including a band pass prefiltering circuit and filters resonant at the different frequencies of the code used, and a second recognition section for distinguishing between true MF signals and noise or speech signals. MF receivers of older designs use analog filtering and recognition devices, but often these devices do not offer a high immunity to noise. In addition^ they are susceptible to variations in component characteristics, temperature and aging, and usually need adjustments during manufacture and maintenance One object of this invention is an MF receiver; - 2 42631 According to the invention, there is provided a digital receiver for multifrequency (MF) signal combinations each consisting of a plurality of frequencies selected from a set said receiver of predetermined frequencies forming an MF code,/including a arranged digital filter formed by a special-purpose processor/to act as a band pass filter and a set of resonant filters Cij divided into groups each consisting of two resonant filters connected in cascade, in which the first filter (j = 1) and the second filter (j = 2) of each group are resonant at the same frequency, each group resonant respectively at one of the said predetermined frequencies, i representing the order number of thio frequency, in which each of the resonant filters Cij delivers in every period T a dialtai signal of value a13, in which a digital nl being an integer greater than 1 recognition device receives in every period Τ' (Τ' = ηΙ.Ί/) the digital signals of value aj^ corresponding to the signals of - 3 3621 - 4 value rectified and averaged over nl periods T, k representing the order number of the period Τ’, in which the first filter (j = 1) of each group has a wider pass hand than the second filter (j = 2), in which the digital recognition device includes first means for recognizing the appearance of an MF signal and second means for recognizing the disappearance of this MF signal, in which the use of the first means starts from the instant at which the digital recognition device has recognized the disappearance of an MF signal and until it . recognizes the appearance of a further such signal, and in which the use of the second means starts from the instant at which the appearance of an MF signal has been recogized and until it recognizes the disappearance of this signal.

An embodiment of the invention will now be described in relation to the attached drawings in which s Figure 1 is an example of the filtering arrangement for detecting the presence of six predetermined frequencies; Figure 2 is a block diagram of a circuit for computing the average value of several signals; Figures 3 and 4 are diagrams of the amplitude of six signals, two of which form an MF code example; Figure 5 is a block diagram of a digital recognition device embodying the invention.

The MF signals are filtered in typical form by a special-purpose processor used as a digital filter. For this purpose, the received analog signals are sampled and coded linearly in binary form, with a number of bits depending upon the volume of the MF signal to be processed, e.g. ten. bits for a volume of 30 dB. The first bit of each word starting from the left represents the sign of the sampled value. A sampling - 4 42621 - 5 period T of 125^us is commonly used for VF signals, but is not mandatory. The receiver can also receive MF signals sent as coded samples, in which case the coding operation is not necessary. However, if the samples were compressed before transmission, they must be expanded after reception to obtain linear codes. Of course, the receiver can have several inputs connected to different MF signal transmission channels, the special-purpose, computer then processing the signals of the different channels successively. , The familiar realization of a given filtering arrangement having specific filtering characteristics is obtained by combining a certain number of second order filter cells, each arranged to solve the system of equations of the type : (1) W(nT) = X(nT) + Bl.W(nT - T) + B2.W{nT - 2T) (2) Y(nT) = Ao[w(nT) + Al.W(nT - T) + A2,W(nT - 2T)j in which : T is the sampling period; n is the order number of the sample; X(nT) is the signal at the input to the filter cell; Y(nT) is the signal at the output of the filter cell; W(nT) is an intermediate digital signal; Al, A2, BI, B2 are constants defining the characteristics of the filter cell .(poles and zeros); AO is a constant permitting the filter cell gain to be controlled.

Figure 1 is an exanple of a filter arrangement for detecting the presence of six frequencies Fl to F6 forming a given MF code. It contains a first group of second order filter cells, Cl to C4 in cascade and forming a wide band filter - 5 521 - 6 which attenuates signals of frequencies lower than Fl or higher than F6, a second group of six second order filter cells Cll, C21, ..., C61 connected in parallel to the output of the cells Ci to C4 and forming six filters resonant at frequencies Fl to F6 respectively, and a third group of six second order filter cells C12, C22, .,.., C62 connected respectively to the output of cells Cll, C21, ...., C61 and forming a set of six filters respectively resonant to the same frequencies Fl to F6 as the preceding filters, but having a narrower pass band.

We call the twelve resonant filters Cij, with : i = 1 to 6 j = 1 and 2 i representing the frequency’s order number (Fl-FS) within the MF code; j representing the order number of the filter resonant at a given frequency.

Let a^ (i = 1 to 6, j =1 and 2) be the instantaneous amplitude of the signals appearing successively at the output of the various filters Cij during a sampling period T.

The special-purpose processor carries out on a timeshared basis all calculations relating to the different filter cells, the constants AO, Al, A2, BI, B2 associated with each cell as well as the instructions relating to the configuration of the filter arrangement and to the operations executed by each cell being stored in a memory, e.g. a read-only memory. Thus, during a sampling period of order n and duration T, we have successively in time, at the output of the filter network, twelve digital signals a1·^, namely a11, a12, ...., a61, a62.

Each a1-1 signal, for given i's and j's, successively forms as a function of the order number n a series of values - 6 43631 Which represent the instantaneous amplitude of a signal having a preponderant sine wave component of frequency Fi.

The operation of recognizing the appearance or disappearance of an MF signal are carried out on a set of averaged values of signals defined as follows : let |a^| be the absolute value of the instantaneous amplitude of each sample , the series of values | ai:* | therefore representing the rectified signal. Let nl be successive samples Ja^ J (for example nl = 16) produced during a time interval Τ' such as Τ' = nl.T (for example Τ’ = 16 X 125컣 = 2 ms). Let k be the order number of the time interval Τ', and let u be the order number of a sample in the time interval or order k. The average TT value a£ , calculated on nl successive samples of the time interval Τ' of order k, may be written : nl-1 z u=o nl.k+u Figure 2 is a block diagram of the circuit to compute averages a^. It consists of an adder 1 connected via an accumulator register 4 to a shift storage 2 having as many compartments as there are resonant filters, and whose output is connected to a divide-by-nl circuit 3 on the one hand and to one input of the adder 1 on the other hand, the other input of this adder receiving in parallel form the bits of the rectified signals of value from the digital filter. Rectification occurs in effect by simple elimination of the conductor transmitting the sign bit, the adder 1 thus receiving only the nine amplitude'bits from the digital filter. Connections between the portions of the processor are in parallel form. Instructions 1 coming from a storage (not shown) control this processor. - 8 The 12 rectified signals a^, successively present once per period T.at the input of the processor, are aad°d respectively in adder 1 to the sum cf the corresponding signals a·*··1 of the preceding periods available by reading the corresponding section of the shift storage 2, and the new sum obtained is then stored on the same section of this shift storage 2, in place of the previous sum. This is done successively for the twelve rectified signals a3'·’ and is repeated during nl periods. Τ» At the end of these nl periods T, the results thus obtained in shift storage 2 are transferred to the divide-by-nl circuit 3 instead of being entered in adder 1. The divide-by-nl circuit thus delivers twelve signals a^-1 (i = lto6, j=l and 2) at each time interval T1.

The system formed by the special-purpose digital processor to solve the system of equations with differences above (1) and (2)/ followed by the average values circuit shown in figure 2 is called a digital filtering unit. The use of two separate processing circuits for filtering and calculation of averages respectively is not the only solution. In fact, these circuits can be combined if the speed of the equipment used permits it, or if the number of MF channels to be processed is not too high.

The purpose of the digital recognition device which follows the digital filtering unit, is to extract the maximum data from the series of a^ signals to recognize the presence or absence of MF signals w?th the minimum of confusion with noise Signals. Its operation is divided into two distinct phases s 1. RECOGNITION OF THE APPEARANCE OF AN MF SIGNAL; 2. RECOGNITION OF THE DISAPPEARANCE OF AN MF SIGNAL. - 8 426»1 - 9 It operates in the MP signal appearance recognition phase from the moment it recognized the disappearance of an MF signal and until it recognizes tho appearance of a new MF signal. Conversely, it operates in the MF signal disappearance recognition phase from the moment it recognized the appearance of an MF signal and until it recognizes the disappearance of this signal.

The digital recognition circuit processes in timedivision multiplex the filtered signals from different transmission channels. However, to simplify the description of the recognition device, we consider only MF signals transmitted over a single channel. As an example, it is assumed that the filter arrangement used is the one shown in figure 1 and that the code combinations consist of two frequencies out of six.

The two phases of operation of the digital recognition circuit will be explained one after the other s 1.. MF SIGNAL APPEARANCE RECOGNITION PHASE This phase includes the following successive operations ί (A) Weighting of the twelve values aj^ (i = 1 to 6, j = and 2) of the rectified and averaged signals from the resonant filters Cij; (ii) Determination of two amplitude discrimination thresholds; (iii) Amplitude discrimination on the six weighted signals of 772 value A^* (i = 1 to 6); (iv) (v) (vi) Detection of the absence of transient state; Decision; Locking.

This set of operations is carried out once per. time interval T1 and repeated during .several time intervals Τ' until an MF signal is recognized. Each of these operations will now - 9 -lObe oxplained in detail. (i) Weighting of the twelve values (i = 1 to 6, j = and 2) The second order filter cells forming the digital filter 5 have different gains according to the coefficients Al, A2, BI, B2 associated with them. The gains are approximately equalized at the level of the digital filter by using the coefficient AO in equation (2) of the system of equations described above. This equalization is approximate and consists only of a series of shifts, so as to reduce the time of the operation within the digital filter. The twelve amplitudes are weighted at the level of the digital recognition circuit to correct the remaining inequality in gain of the filters Cij (i = 1 to 6, j = 1 and 2), and to compensate for variations in the frequency response curve of the band pass filter within its pass band. This weighting is obtained by multiplying each Signal of the value aj^ (i = 1 to 6, j = and 2) by an appropriate constant g1-’ (i = 1 to 6, j = 1 and 2) We thus obtain : Aj^ = aj^ . g^ (i = 1 to 5, j = 1 and 2), γτ --1 V where A^ represents the weighted value of the signals a^-1.

Note that this operation is shorter than a precise weighting would be when made directly at the digital filter output for signals of value a1-1, since the rate of multiplications to be carried out on the averages aj^ is nl times smaller, or, in the present case 16 times smaller. (ii). Determination of the two amplitude discrimination thresholds Two thresholds A01 and A02 are determined to effect an amplitude discrimination designed, as we shall see later, to detect two frequencies among the six frequencies of the MF code. These two thresholds are chosen as a function of a reference signal of value Mj. obtained by taking the average of the signals of value max over kl consecutive intervals of time Τ', Aj^ max representing the greatest of the six signals of value A^ (i » 1 to 6) obtained during the time interval Τ' of order k. The reference signal may be written : kl-1 «k = v=0 A, “ max k-v kl will for example be equal to four.

Depending upon the value of the reference signal, two possibilities can occur : (a) Mk <^L (b) L where L is a given constant, tied to the specifications. (a) MR We conclude that the value of the reference signal is too small and that the MF signal, if it exists, should not be detected, as it is due to crosstalk. No threshold is determined, and the sequence of operations of this recognition phase is stopped.

U.1 ^>1 The presence of an MF signal 'is possible.

The thresholds A01 and A02 are automatically variable as a function of the value Mj^ of the reference signal. Thus : A01 = f.Mfc . A02 = q.M^, where f and q are two givsn constants, tied to the specifications .

Note, that the reference signal of value is calculated from the rectified and averaged output signals from the six filters Cil (i = 1 to 6) and not from those coming from the six I - 12 filters Ci2 (i = 1 to 6) because, as mentioned previously, the first ones have a wider pass band. Thus the thresholds A01 and A02 will be virtually constant whatever the position of each frequency within the narrower pass band of the filters Ci2 (1 = 1 to 6) from which the amplitude discrimination will be carried out. (iii) Amplitude discrimination on the six weighted signals of value Aj^2 (j = 1 to 6) ,n 42 The six signals of value A^ related to the six filter cells Ci2 are compared to the previously defined thresholds A01 and A02.. A condition C to recognize the presence of an MF signal needs the simultaneous conditions that two signals are above the threshold A01, and that four signals are below the threshold A02.

Figure 3 shows a group of six signals of value A^2 (i = 1 to 6) corresponding to Fl to F6, compared with the thresholds A01 and A02. This example Includes two signals of 42 value and A^ , corresponding to the frequencies F3 and F4, 12 22 above the threshold AOl, and four signals of value , / g2 and Αζ , corresponding to the frequencies Fl, F2, F5 and F6, below the threshold A02. (iv) Detection of the absence of transient state Another condition D for recognizing the presence of an MF signal is the absence of transient state. Transient state means any variation of the signals A^-1 during the time coming either from the establishment of an MF signal, or from any noise pulse. A transient state can be detected, for example, TT by measuring the variations of the signal A^ max. In this case, we say that no transient state exists if the relative variation of the signals of Value A^1 max with respect to the - 13 reference signal of value Mk during the last kl time intervals •f is less in absolute value than a value t such as t t « x.M* in which r is a given constant.

Condition D is satisfied if : (3) h^v maX ” Mkl r for v “ 0 t0 To simplify, we write : max = av Each term of expression (3) is written : (4) |av - Mk|cr.Mk If: ay - Mj, 0, expression (4) is written : av “k Cr>Mk or : (5) ay - (r+DMfc-^O Let pv = 0 if the expression (5) is satisfied and pv = 1 in the opposite case.

If: ay - MJc-avk or: (6) (1-r)^ - av <0 Let ny = 0 is expression (6) is satisfied and ny = 1 in the opposite case.

The absence of a transient state is detected if : pv = 0 and nv = 0 for v=0 to kl-1. (v) Decision The purpose of the decision process is to determine if, at a given instant, an MF code is recognised or nor. To conclude that an MF code is present : (a) condition D as to the absence of transient state must 621 be metj (b) the present of the same MF code must be observed on a number k2 of consecutive time intervals Τ' : condition G.

The presence of an MF code is determined, as mentioned before, from the amplitude discrimination of the six signals “12 Afc with respect to the thresholds A01 and A02. Condition G may be replaced by a majority decision ϊ in this ca3e, it is only necessary for the presence of the same MF code be observed over a number k3 of time intervals Τ' out of the last k2 time k3 intervals (k3< k2), the ratio defining che chosen degree of majority.

A result P, of the decision process appears at each time interval T'k· This result, called the decision indicator, is 1 or 0 depending upon whether conditions D and G are satisfied or not. (vi) Locking During the recognition phase, the decision indicator Pfc at the end of each time interval Τ', is in the 0 state in the k — following cases : (a) when there is no MF signal at the receiver input; (b) when the receiver is in a transient state due to the front edge of an MF signal or a noise pulse.

As soon as the presence of an MF signal is recognized, Ρ^ changes from the 0 state to the 1 state and the receiver goes to the locked state. At this instant, the recognized MF code, e.g. R^, is stored in an output register, and the receiver changes automatically to the MF signal disappearance recognition phase.' The code R^ is composed of six binary variables Fi (i = 1 to 6), called frequency indicators, which assume the 42021 values 1 or 0 depending upon whether the corresponding frequency is present or not (e.g. R^ = 001100), and is retained in the output register until the disappearance of the signal is recognized. 2. MF SIGNAL DISAPPEARANCE RECOGNITION PHASE This phase includes the following successive operations : (i) Weighting of the six values aj^ (i = 1 to 6) of the rectified and averaged output signals from the six resonant filters Ci2 (i = 1 to 6). 10 (ill Determination of a single amplitude discrimination threshold. (iii) Amplitude discrimination on the six weighted signals of ~T2 value Α^ (i = 1 to 6). (iv) Decision. 15 (v) Unlocking. This set of operations is carried out once per time inter- val Τ', and repeated during several time intervals T* until the disappearance of a signal is recognized. Each of these operations will now be explained in detail. (i) Weighting of the six values a^ (1 = 1 to 6) This operation was explained in the description of the recognition phase, and is here limited to the six signals of value a^ associated with the six resonant filters Ci2 (i = to 6).

We obtain six weighted signals of value A^ , such as : .12 i2 12 ,. .

Ak = ak ’ g (i = 1 to 6) (11) Determination Of a single amplitude discrimination threshold A single threshold A03 is determined to effect an “Ϊ2 amplitude discrimination on the six signals of value A^ . This threshold is computed from the last reference signal of valuo obtained during the preceding recognition phase. Thus : A03 = s.Mfc (preceding phase) in which s is a given constant. This threshold thus remains constant during the entire disappearance recognition phase. (iii) Amplitude discrimination on the six signals A^2 (i = 1 to 6) 2 The six signals of value A^ relating to the six filter cells Ci2 are compared with the single threshold A03. It is considered that there is no MF signal if the six signals are below the threshold A03. Figure 4 shows a group of six signals of value.A^2, all below the threshold A03. (iv) Decision Condition N, for recognising the disappearance of an MF signal, is that a signal has been absent for a certain time at the output of all resonant circuits Ci2. The purpose of this is to prevent the error called double numbering, due to a noise phenomenon whose effect simulates a momentary interruption of the MF signal. Condition N is confirmed by the digital recognition circuit if the six signals of value A^2 are below the threshold A03 for k4 consecutive time intervals Τ'.

The reference signal of value M^, computed during the preceding signal appearance recognition phase, is a function of the amplitude of the MF signal then received. Now the threshold A03 is also a function of this value M^, and thus of the amplitude of this received MF signal. Thence, the time elapsed until the six signals of value A^2 drop below threshold A03 is independent of the amplitude of the MF signal which was present until then. - 17 (v) Unlocking When condition N obtains, it can be concluded with some degree of certainty that the MF signal has disappeared. The receiver then goes to the unlocked state. At this Instant, the receiver output register containing the received MF code is reset to 2ero, and the receiver changes automatically to the signal presence recognition phase, so as to be ready to receive the next MF signal.

If the receiver receives several MF signals simultaneously 10 on several inputs, they are processed successively in time, and each one independently of the others, by the digital recognition device.

Figure 5 is a block diagram of the digital recognition device which carries out the various operations of the two phases. It includes a random access memory 5 addressed row by row and a typical universal arithmetic and logical unit 6 (e.g. integrated circuit SN 74181) having two groups of inputs El and E2 and one group of outputs S and executing in particular the operations of addition, subtraction', right of left shift, as well as logical functions such as AND and OR. An output V Indicates, depending upon its logical condition, the sign of the difference between the values of the two binary signals present on its two groups of inputs El and E2.when the unit is operating as a subtractor. Another output W presents the 1 state when all the outputs of the group S present a 0 state.

A multi-conductor bus line 7 receives in parallel form the nine bits of the digital signals of value a^·3 from the divide-by-nl circuit 3, figure 2, and connects the inputs to the memory 5, giving access to all but the last column, to the group of inputs E2 of the arithmetic and logical unit 6. A - 17 - 18 eat 7, to the memory 5 and An output register 15, delivers the indicator buffer register 8 stores the binary result on tho outputs S of unit 6 which can be transmitted to the group of inputs El, to the bus 7 through a logic gate 9, and to a special-purpose processor 10 connected to the bus 7 whose design and function is explained below. The outputs V and W of the unit 6 are connected, through logic gates 11 and 12 and a single-conductor bus 13, to the input of a shifting circuit 14 and to the input of memory 5 permitting access to the last column. The parallel outputs of the shifting circuit 14 are connected, through bus to the group of inputs E2 of the unit 6. whose inputs are connected to bus 7, signals of the frequencies received.

The selection of the operating mode in which the arithmetic and logic unit 6 should operate (addition, subtraction, ....), addressing and read and write commands of memory 5, and the control of the other elements (registers, logic gates, .,..), are controlled from a programmed control unit 16, which also includes the various constants necessary for the processing.

These constants are transmitted over bus 7 through a logic gate 17 also controlled by the unit 16. For greater clarity, the control connections between the control unit 16 and other components mentioned are not shown. Instruction jumps in the control unit 16 are commanded, through a flip-flop 18, by signals on bus 13. All operations are timed by clock signals.

We now describe the operation of the digital recognition device, examining the sequence of operations carried out during the MF signal appearance recognition phase, although of course the method described below is only an example which could be executed differently by simply modifying the instruction program. The twelve binary signals of value aj^ (i = 1 to 6, j υ 1 or 2) from the averages computer circuit, figure 2, and which are present on bus 7 are stored on twelve rows of memory 5 by order of the control unit 16, in order to be available for the various operations to be carried out, as explained below : ii (i) Weighting of the twelve values a;,J The first of the twelve signals stored in memory 5, i.e. “TT the signal of value a£ , is read and transmitted to inputs 32 of the arithmetic and logical unit 6 over bus 7, the unit then performing a transparency function, i.e. delivering to the group of outputs S the same signal as the one present at the group of inputs 32. Then it is transmitted to the group of inputs El via the buffer register 8. This signal of value “TT «k present at the inputs El is then multiplied by the corresponding weighting factor, i.e. g11, the multiplication being done in the usual way by a series of shifts and possibly “TT additions. Thus the binary signal of value at the inputs El is shifted to the left and the result at the outputs S replace the previous result at the inputs El. Then this shifted signal at El is added or not to the signal of value from memory 5 on the inputs E2, depending upon whether the last bit of g^ is 1 or 0. The new result then present at the outputs S is sent to the inputs El to be shifted, etc.... When the multiplication is finished, the final result, of value Aj^, present at the outputs S, is transferred to memory 5 through the buffer register 8, the logic gate 9 which is open and the bus 7. All this is of course controlled by the unit 16.

This weighting operation is repeated for the other eleven signals of value a^3, and therefore twelve weighted signals of value A^3 (i = 1 to 6, j = 1 and 2) will finally be available in memory 5. at - 20 •ii) Determination of the two amplitude discrimination thresholds As mentioned above, the first step in this operation is \ £ ·»' to search for the value A^ max of the highest amplitude signal among the six signals of value Aj^ (i = 1 to 6)., To do this, the first of these six signals, namely the signal of value Aj^\ is read from memory 5 and sent to the inputs E2 of the unit 6 via the bus 7, the unit being transparent and thus allowing this signal, through buffer register 8, to appear on op , tlie inputs El. The second signal, of value A^ , is read xn its turn from memory 5 and sent r.o the inputs E2 of the unit 6 via bus 7, the unit performing the subtraction function.

Two cases can then arise : 7ΪΪ 721 v>7 A^1, output V of the arithA-- and If we have the case metic and logical unit 6 goes to level 0, which does not cause a jump of instructions within the program. The following instruction is then executed; it consists in keeping the signal of value A^1 on the inputs El, reading the third signal of VT value A^ stored in memory 5 and sending it to the inputs E2 of the unit 6 which carries out the. subtraction function.

If we move now to the case Aj) output V of the unit 6 goes to level 1, causing, through the open gate 11 and bus 13, a jump of instructions in the programmed control unit 16, so as to replace the signal of value A^1 on the inputs 2i El of the unit 6 with the signal of higher value A^ . Then, as before, the third signal of value stored in memory 5 is sent tc the inputs E2 of the arithmetic and logical unit 6, etc.... Each time, therefore, we have at'the output of buffer register 8 and on the inputs El of the unit 6 the largest of the signals processed until then, and at the end of the operation the signal of value A.^ max, which is then sent to memory 5 via the open gate 9 and bus 7.

Now, we must calculate the value Mj, of the reference signal corresponding to the average of the kl signals of value £_v max (v=0 to kl-1) obtained over kl consecutive time intervals T1, these signals being stored in memory 5, the last 11 one, namely the signal of value Afc max, having just been entered into it. To do this, the oldest of the kl signals is sent from memory 5 to the inputs E2 of unit 6 through bus 7. This signal is then transferred to the inputs El through the buffer register 8, the arithmetic and logical unit operating in transparency. Then the following signal is in its turn sent from memory 5 to the group of inputs E2 to be added to the previous signal present at El. The result of the addition is in its turn transferred to the inputs El, and the next signal, stored in memory 5, added to it, etc.... Thus at the end of the operation, we have, on the group of inputs El, the sum of the kl signals of value A^v max (v=0 to kl-1). If we choose a value for kl that corresponds to a power of two, for example four, this sum of signals will be divided by kl, to obtain Mj^, by simple right shifts of the signal on the inputs El. The reference signal of value is then stored in memory 5 via the buffer register 8, the open logic gate 9 and bus 7.

As mentioned, the two thresholds A01 and A02 are determined from the value and the constant L stored in the programmed control unit 16. The signal of value M^, stored in memory 5, is sent to the group of inputs El of the unit 6 then operating in transparency, as explained before. The signal of value L is sent from the control unit 16 to the inputs E2 via tho gate 17, the unit 6 then operating as a subtractor.

Where Mk<^L, the output V of the arithmetic and logical unit is a level 1 which, sent via the gate 11, bus 13 and flip-flop 16, stops the program sequence until the next time interval Τ'. However, If the output V of the arithmetic and logical unit is a 0 which causes no instruction jump in the control unit 16. The unit 16 thus causes the calculation of the variable thresholds of values and q.M, , which will be calculated by the unit 6 in the same way as for the weighting of signals of value aj^ by the signals of value g'*’^. The two thresholds A01 and A02 are stored in memory 5.

(Iii) Amplitude discrimination on the six weighted signals of value Aj^2 (i = 1 to 6) The six signals of value A^ relating to the six filter cells Ci2 are first of all compared with the first threshold A01. The signal representing the value of this threshold is sent from memory 5 to the inputs El of the unit 6 operating in transparency. Then the six signals of value A^2 are successively sent from memory 5 to the inputs E2 of the unit 6 then operating as a subtractor. Each time, the output V is 1 if £2' the signal of value A^ present on the inputs E2 is above the threshold A01, or 0 in the opposite case. The shift circuit 14 thus receives at its-input, via the gate 11 and bus 13, the different signals delivered in sequence by the output V of the unit 6 and converts them into parallel form by a series of shifts. We thus obtain at the output of the shift circuit 14 a six-bit word Kl, in which the 1-bits represent the signals ~l2 whose value A^ is above the threshold A01, the position of the 3. bits permitting the corresponding frequencies to bo identified. This six-bit word Kl is transferred from the shift circuit 14 it is stored on one row.

“TT signals of value A^ are compared with the as before, and the six bits obtained in V of the unit δ are converted into shift circuit 14. A second six-bit word is stored on one row of memory 5.

)M. are to be calculated, to memory 5 in which Then, the six second threshold A02 series at the output parallel form by the K2 is obtained which (iv) Detection of the absence of transiant state First of all, (1+γ)Μ^ and (1-r which is done by the unit 6 in the same way as the other addition, subtraction and multiplication operations. The results are stored in the memory 5.

Then the unit 6 makes the kl comparisons : ay - (r+l)MJi«c 0 and the kl comparisons : (l-r)Mk - av<;0 The successive results Pv and ny are converted into parallel form by the shift circuit 14 and stored on one row of memory 5. (v) Decision TO'Verify the condition G, the recognition device first verifies the presence of an MF code on the last k2 time intervals Τ', without considering the mutual identity of the codes.

The six-bit word Kl stored in memory 5 is passed through the unit 6 and buffer register 8, to the special-purpose processor 10, which consists of a read-only memory addressed by the six-bit words Kl. Each row of the memory contains a four-bit word, which includes at least one 1. bit for the rows addressed by a code containing two 1 bits and four 0 bits.

The combination of the four bits of this word identifies the six-bit address code. Rows addressed by a six-bit code 531 containing more or less than two 1 bits/contain four 0 bits.

The four-bit word K3 in the row of the read-only memory addressed by the word KI is transferred, through bus 7, to memory 5. This addressing operation of the processor 10 is carried our. in the same way with the word K2. The special-purpose processor 10 then delivers a four-bit word K4 to memory 5.

The words K4 and K3 are then transferred in succession from the memory 5 to the unit 6 to see if they contain at least one 1 bit, in which case a 0 bit is present at the output W.

The bit at W is transferred to the shift circuit 14 whose different outputs have previously received from memory 5 the 1 or 0 bits relating to the presence or absence of an MF code during the preceding k2 time intervals Τ'. The shift circuit 14 then, shifts one position to the left, thus permitting the bit present at the output W of unit 6, and relating to the word K3, to appear on the first output to the right, whereas the bit present on the first output to the left, relating to the word K3 of the oldest time interval Τ', is eliminated. The same operation is performed again with the word K4. The result present at the outputs of the shift circuit is transferred to memory 5.

After the device has confirmed the presence of an MF code in the last k2 time intervals Τ', it must be verified that this code is identical in these k2 time intervals. To do this, the last six-bit word Kl or K2 is compared, by the unit 6, with the K2-1 words Kl and K2 of the preceding time intervals stored in memory 5. The output W delivers a 1 bit when two comjjared words are identical. The different bits from W during successive comparisons are transferred, via the shift circuit 14, to memory 5. - 24 42621 - 25 Now we must see if the condition G, presence of the same Hi' code during k2 consecutive time intervals Τ*, and condition I), the absence of transient state, are confirmed. To do this, tha result bits relating to condition D stored in a row of memory 5 are transferred to the unit 6 to be compared with the bits that would be obtained if condition D were obtained, which bits come from the control unit 16, The output W of unit 6 delivers a 1 bit if the condition D is realized. The same is true for the result bits relating to condition G.

The different output bits from W of the unit 6 are then transferred on bus 7 via the shift circuit 14, then compared, in unit 6, with the bits that should be obtained to confirm the presence of an MF signal, these bits coming from the control unit 16. Output W then delivers a 1. bit to the flip-flop 18, and to the last column of memory 5 so that it will be stored. Flip-flop 18 then delivers a signal Pj, - 1. (vi) Locking The effect of the appearance of the signal P^ = 1^ is to enter the recognized MF signal (two out of six frequencies, e.g. 001100) and the four-bit code identifying this combination in the output register 15 and also in memory 5, and to switch the recognition device to the MF signal disappearance recognition phase.

The control unit 16 then causes the execution of the recognition phase of the disappearance of this signal. The operations concerning this phase are similar to those cf the preceding phase for signal recognition s additions, multiplications, comparisons, etc.... Therefore, they are not described. If the condition N, recognition of the disappearance of the MF signal, is confirmed, the output register 15 delivers no signal. 13621 -Ik, Otherwise, it delivers the two binary signals corresponding to the two previously received signals as well as the code corresponding to the combination of these two frequencies.

It is clear that the csigj tai recognition device which has just been described can be used for recognizing MF signals sent over several signalling channels. Each channel is then processed in succession and the MF signals from the output register 15 are then stored in components proper to each channel, ι The receiver operation has been described with a particular example of MF code (two out of six frequencies), but it is applicable to other MF codes, in particular to the pushbutton code for which each piece of information is sent by a combination of a low frequency chosen from a group of four low frequencies and of a high frequency chosen from a group of four high frequencies. The receiver circuits are identical, and only the programs and constants are changed. The value of the reference signal M^ as well as the condition of absence of transient state could be determined from the signals coming from the band pass filter allowing the group of low frequencies to pass, and from the band pass filter allowing the group of high frequencies to pass, instead of from the signals coming from filters resonant respectively at different frequencies, in order to improve protection against interfering speech signals.

Claims (11)

1. A digital receiver for multifrequency (MF) signal combinations each consisting of a plurality of frequencies selected said receiver from a set of predetermined frequencies forming an MF code, / arranged including a digital filter formed by a special-purpose processor/ to act as a band pass filter and a set of resonant filters Cij each consisting divided into groups/ of two resonant filters connected in cascade, in which the first filter (j = 1) and the second filter (j =

2. ) of each group are resonant at the same frequency, each group resonant respectively at one of the said predetermined frequencies, i representing the order number of this frequency, in which each of the resonant filters Cij delivers in every period T a digital signal of value a 1 · 5 , in which a digital ni being an integer greater than 1 recognition device receives in every period Τ* (Τ' = nl.T/)the digital signals of value a^ 3 corresponding to the signals of value a^ 3 rectified and averaged over nl periods T, k representing the order numbef of the period Τ', in which the first filter (j - 1) of each group has a wider pass band than the second filter (j = 2), in which the digital recognition device includes first means for recognizing the appearance of an MF signal and second means for recognizing the disappearance of this MF signal, in which the use of the first means starts from the instant at which the digital recognition device has recognized the disappearance of an MF signal and until it recognizes the appearance of a further such signal, and in which the use of the second means starts from the instant at which the appearance of an MF signal has been recognized and until it 27 11 - 28 recognizes the disappearance of this signal. in which each said MF signal consists of two different frequencies, and 2. A receiver according to claim 1,/in which the said first means for recognizing the appearance of an MF signal include means to determine amplitude discrimination thresholds A01 and i2 A02, means of amplitude discrimination of the signals A^ with respect to the thresholds AO1 and AO2, means to detect a condition D indicating the absence of a transient state, means for decision permitting confirmation of the appearance or not of an MF signal, and means for locking identifying nhe two frequencies of the MF signal received and switching the recognition device to the MF signal disappearance recognition phase.

3. A receiver according to claim 1 or 2, in which the said second means for recognizing the disappearance of an MF signal includes means for weighting the signals of value a^ 2 by coi2 i2 efficients g permitting weighted signals of value A^ to be obtained, means to determine a single amplitude discrimination threshold A03, means for amplitude discrimination on the signals of value A^ 2 with respect to the threshold A03, means of decision permitting confirmation of the disappearance or not of the MF signal, and means of unlocking eliminating the identification of the MF signal previously received and switching the recognition device to the MF signal appearance recognition phase.

4. A receiver according to claim 2 or 3, and in which the said means for determining the two amplitude discrimination over i for a given value k thresholds’ A01 and A02 includes means to search for the strongest/ of the signals of value Α^\ means to compute the value M^ of a reference signal so that it is equal to the average value of 28 43621 - 29 where kl is an integer greater than 1 the kl strongest signals during the last kl time intervals Τ’, / means tc compare the said reference signal of value to a constant L, and means to determine the two thresholds AOl and AO2 rrom if : M^^L.

5. 5. A receiver according to claim 2, 3 or 4, and in which said means of amplitude discrimination, of the signals A^ include means to compare the signals of value A^ with the thresholds AOl and AO2 and to deliver, for each signal compared to a threshold, a level 1 or 0 depending upon whether the 10 compared signal is above or below the threshold.

6. A receiver according to claim 4 or 5, and in which said means for detecting the condition D, indicating the absence of •a transient state, include means for computing a value t, t = r.M. in which r is a constant, means for computing the K over i for a given value of k 15 absolute value of the difference between the highest value/ of ' £ Υ the signals of value Aj, and the value on the last kl time intervals Τ', and means for comparing the obtained results with the value t, with the condition D satisfied if the obtained results are less than the value t. 20

7. A receiver according to claim 6, and in which the said means of decision for appearance detection include means to detect a condition G indicating, from the results of the operation of amplitude discrimination with respect to the thresholds AOl and A02, the presence of the same MF signal k2 being an integer greater than 1, 25 during k2 consecutive time intervals Τ',/and means to detect the presence of both conditions D and G.

8. A receiver according tc claim 4 er any claim appendant thereto in which saJd means to determine, a single amplitude discrimination threshold A03 includes calculation means to multiply 30 s.Mj. - n w hich s is a constant and represents the last value - 30 of the reference signal during the preceding recognition phase of the presence of an MF signal, the result s.M^ corresponding to the threshold A03.

9. A receiver according to any one of the claims 3 to 8, and in which said means of decision for disappearance detection include means to detect a condition N indicating, from the i results of the operation of amplitude discrimination with respect to the single threshold Λ03, the absence of an MF signal if all signals of value A^ are below the threshold A03.for k4 consecutive time intervals Τ', k4 being an integer greater than 1.

10. A receiver according to any one of the preceding claims, in which the said digital recognition device includes a proghaving 2 groups of inputs rammed control unit and an arithmetic ahd logical unit/of which one group of inputs is connected to a random access memory, and of which the other group of inputs is connected, through a buffer register, to a group of outputs, which are also connected to the multi-conductor bus line and to a special-purpose processor consisting of a read-only memory whose outputs are connected to the bus line, the said arithmetic and logical unit having other outputs connected, through a shift circuit with series input and parallel outputs, to the random access memory.

11. A digital receiver for multi-frequency signals, substantially as described with reference to the accompanying drawings.