HK1140031A1 - Adaptive memory device and method for enhancing the performance of an external computing device - Google Patents

Adaptive memory device and method for enhancing the performance of an external computing device

Info

Publication number
HK1140031A1
HK1140031A1 HK10106121.7A HK10106121A HK1140031A1 HK 1140031 A1 HK1140031 A1 HK 1140031A1 HK 10106121 A HK10106121 A HK 10106121A HK 1140031 A1 HK1140031 A1 HK 1140031A1
Authority
HK
Hong Kong
Prior art keywords
memory
computing device
external computing
memory type
performance
Prior art date
Application number
HK10106121.7A
Other languages
English (en)
Inventor
Mohammad S Ahmadnia
Louis Cameron Fisher
Stephen V R Hellriegel
Original Assignee
Mobile Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mobile Semiconductor Corp filed Critical Mobile Semiconductor Corp
Publication of HK1140031A1 publication Critical patent/HK1140031A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/225—Hybrid cache memory, e.g. having both volatile and non-volatile portions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/602—Details relating to cache prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
HK10106121.7A 2007-01-10 2010-06-21 Adaptive memory device and method for enhancing the performance of an external computing device HK1140031A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88437807P 2007-01-10 2007-01-10
PCT/US2008/050787 WO2008086488A2 (en) 2007-01-10 2008-01-10 Adaptive memory system for enhancing the performance of an external computing device

Publications (1)

Publication Number Publication Date
HK1140031A1 true HK1140031A1 (en) 2010-09-30

Family

ID=39609376

Family Applications (1)

Application Number Title Priority Date Filing Date
HK10106121.7A HK1140031A1 (en) 2007-01-10 2010-06-21 Adaptive memory device and method for enhancing the performance of an external computing device

Country Status (7)

Country Link
US (4) US8135933B2 (xx)
EP (1) EP2122473B1 (xx)
KR (1) KR101469512B1 (xx)
CN (1) CN101611387B (xx)
HK (1) HK1140031A1 (xx)
TW (2) TWI463321B (xx)
WO (1) WO2008086488A2 (xx)

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009026296A (ja) * 2007-06-21 2009-02-05 Toshiba Corp 電子デバイス、メモリデバイス、ホスト装置
IL187044A0 (en) * 2007-10-30 2008-02-09 Sandisk Il Ltd Fast secure boot implementation
US8307180B2 (en) 2008-02-28 2012-11-06 Nokia Corporation Extended utilization area for a memory device
US20090300399A1 (en) * 2008-05-29 2009-12-03 International Business Machines Corporation Profiling power consumption of a plurality of compute nodes while processing an application
US8095811B2 (en) * 2008-05-29 2012-01-10 International Business Machines Corporation Reducing power consumption while synchronizing a plurality of compute nodes during execution of a parallel application
US8195967B2 (en) * 2008-05-29 2012-06-05 International Business Machines Corporation Reducing power consumption during execution of an application on a plurality of compute nodes
US8533504B2 (en) * 2008-05-29 2013-09-10 International Business Machines Corporation Reducing power consumption during execution of an application on a plurality of compute nodes
US8458722B2 (en) * 2008-06-09 2013-06-04 International Business Machines Corporation Thread selection according to predefined power characteristics during context switching on compute nodes
US8291427B2 (en) * 2008-06-09 2012-10-16 International Business Machines Corporation Scheduling applications for execution on a plurality of compute nodes of a parallel computer to manage temperature of the nodes during execution
US8296590B2 (en) * 2008-06-09 2012-10-23 International Business Machines Corporation Budget-based power consumption for application execution on a plurality of compute nodes
US8250389B2 (en) * 2008-07-03 2012-08-21 International Business Machines Corporation Profiling an application for power consumption during execution on a plurality of compute nodes
US8069300B2 (en) * 2008-09-30 2011-11-29 Micron Technology, Inc. Solid state storage device controller with expansion mode
JP2010165249A (ja) * 2009-01-16 2010-07-29 Sony Corp 情報処理装置、情報処理方法およびプログラム
US8874824B2 (en) 2009-06-04 2014-10-28 Memory Technologies, LLC Apparatus and method to share host system RAM with mass storage memory RAM
US20110128766A1 (en) * 2009-11-30 2011-06-02 Ward Parkinson Programmable Resistance Memory
US8914568B2 (en) * 2009-12-23 2014-12-16 Intel Corporation Hybrid memory architectures
US8436720B2 (en) 2010-04-29 2013-05-07 International Business Machines Corporation Monitoring operating parameters in a distributed computing system with active messages
US8537618B2 (en) 2010-08-26 2013-09-17 Steven Jeffrey Grossman RAM memory device with NAND type interface
KR101736384B1 (ko) * 2010-09-29 2017-05-16 삼성전자주식회사 비휘발성 메모리 시스템
KR20120079682A (ko) * 2011-01-05 2012-07-13 삼성전자주식회사 디램 캐시를 포함하는 메모리 장치 및 이를 포함하는 시스템
US8725978B2 (en) 2011-06-30 2014-05-13 Red Hat, Inc. Using symbol information for categorization of dynamic memory allocations
US8719539B2 (en) * 2011-06-30 2014-05-06 Red Hat, Inc. Using heuristics for field types of a structure to categorize dynamic memory allocations
US9417998B2 (en) 2012-01-26 2016-08-16 Memory Technologies Llc Apparatus and method to provide cache move with non-volatile mass memory system
US10096350B2 (en) 2012-03-07 2018-10-09 Medtronic, Inc. Memory array with flash and random access memory and method therefor, reading data from the flash memory without storing the data in the random access memory
US9311226B2 (en) 2012-04-20 2016-04-12 Memory Technologies Llc Managing operational state data of a memory module using host memory in association with state change
US9317087B2 (en) 2012-04-26 2016-04-19 Ravindraraj Ramaraju Memory column drowsy control
US9026808B2 (en) * 2012-04-26 2015-05-05 Freescale Semiconductor, Inc. Memory with word level power gating
CN102722444A (zh) * 2012-05-23 2012-10-10 北京百纳威尔科技有限公司 扩展内部存储空间的方法、装置及终端
US9164804B2 (en) 2012-06-20 2015-10-20 Memory Technologies Llc Virtual memory module
US20130346673A1 (en) * 2012-06-25 2013-12-26 Yi-Chou Chen Method for improving flash memory storage device access
KR101975528B1 (ko) 2012-07-17 2019-05-07 삼성전자주식회사 패스트 어레이 영역을 갖는 반도체 메모리 셀 어레이 및 그것을 포함하는 반도체 메모리
US9128845B2 (en) 2012-07-30 2015-09-08 Hewlett-Packard Development Company, L.P. Dynamically partition a volatile memory for a cache and a memory partition
US9116820B2 (en) * 2012-08-28 2015-08-25 Memory Technologies Llc Dynamic central cache memory
US20140156252A1 (en) * 2012-11-30 2014-06-05 International Business Machines Corporation Hybrid platform-dependent simulation interface
CN103019624B (zh) * 2012-12-11 2015-07-15 清华大学 一种相变内存装置
CN103020551B (zh) * 2012-12-21 2015-12-02 清华大学 一种内存架构
WO2014107154A1 (en) * 2013-01-03 2014-07-10 Icelero Inc. System and method for host-processor communication over a bus
US9489204B2 (en) * 2013-03-15 2016-11-08 Qualcomm Incorporated Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
US10042750B2 (en) 2013-03-15 2018-08-07 Micron Technology, Inc. Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor
GB2516435A (en) 2013-04-05 2015-01-28 Continental Automotive Systems Embedded memory management scheme for real-time applications
KR102070626B1 (ko) 2013-06-26 2020-01-30 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
US10185515B2 (en) * 2013-09-03 2019-01-22 Qualcomm Incorporated Unified memory controller for heterogeneous memory on a multi-chip package
WO2015089488A1 (en) 2013-12-12 2015-06-18 Memory Technologies Llc Channel optimized storage modules
CN104166147A (zh) * 2014-01-08 2014-11-26 芜湖市振华戎科智能科技有限公司 基于北斗二和gps的双模芯片
WO2015126518A2 (en) * 2014-02-20 2015-08-27 Rambus Inc. High performance persistent memory
US9804979B2 (en) * 2014-12-29 2017-10-31 Sandisk Technologies Llc Ring bus architecture for use in a memory module
USD764620S1 (en) 2015-01-14 2016-08-23 Sig Sauer, Inc. Firearm
JP2016167215A (ja) * 2015-03-10 2016-09-15 株式会社東芝 メモリ装置
US20180218317A1 (en) * 2015-03-25 2018-08-02 Joseph Marsh Ryan, III System and method for determining product movement using a sensor
US9720604B2 (en) 2015-08-06 2017-08-01 Sandisk Technologies Llc Block storage protocol to RAM bypass
CN106383775B (zh) * 2015-08-18 2019-03-08 上海景格科技股份有限公司 设备使用时间记录方法及其装置
TWI553478B (zh) * 2015-09-23 2016-10-11 瑞昱半導體股份有限公司 能夠使用外部揮發性記憶體的裝置以及能夠釋放內部揮發性記憶體的裝置
US9904636B2 (en) * 2015-10-22 2018-02-27 John Boyd Modular ultra-wide internal bus mainframe processing units
US10430081B2 (en) * 2016-06-28 2019-10-01 Netapp, Inc. Methods for minimizing fragmentation in SSD within a storage system and devices thereof
US10216685B1 (en) * 2017-07-19 2019-02-26 Agiga Tech Inc. Memory modules with nonvolatile storage and rapid, sustained transfer rates
KR102340446B1 (ko) * 2017-09-08 2021-12-21 삼성전자주식회사 스토리지 장치 및 그것의 데이터 트레이닝 방법
KR102433549B1 (ko) 2017-11-17 2022-08-19 에스케이하이닉스 주식회사 통합 메모리 디바이스 및 그의 동작 방법
KR102414047B1 (ko) 2017-10-30 2022-06-29 에스케이하이닉스 주식회사 통합 메모리 디바이스 및 그의 동작 방법
US11544168B2 (en) 2017-10-30 2023-01-03 SK Hynix Inc. Memory system
KR20190085642A (ko) * 2018-01-11 2019-07-19 에스케이하이닉스 주식회사 메모리 시스템
US11416395B2 (en) * 2018-02-05 2022-08-16 Micron Technology, Inc. Memory virtualization for accessing heterogeneous memory components
US11099789B2 (en) 2018-02-05 2021-08-24 Micron Technology, Inc. Remote direct memory access in multi-tier memory systems
US10782908B2 (en) 2018-02-05 2020-09-22 Micron Technology, Inc. Predictive data orchestration in multi-tier memory systems
US10831393B2 (en) 2018-02-08 2020-11-10 Micron Technology, Inc. Partial save of memory
US10880401B2 (en) 2018-02-12 2020-12-29 Micron Technology, Inc. Optimization of data access and communication in memory systems
US10877892B2 (en) 2018-07-11 2020-12-29 Micron Technology, Inc. Predictive paging to accelerate memory access
WO2020061098A1 (en) * 2018-09-17 2020-03-26 Micron Technology, Inc. Cache operations in a hybrid dual in-line memory module
JP2020047340A (ja) * 2018-09-19 2020-03-26 キオクシア株式会社 不揮発性メモリ及びメモリシステム
US10852949B2 (en) 2019-04-15 2020-12-01 Micron Technology, Inc. Predictive data pre-fetching in a data storage device
US20210097184A1 (en) * 2019-09-27 2021-04-01 Advanced Micro Devices, Inc. Secure buffer for bootloader
CN111767508B (zh) * 2020-07-09 2024-02-23 地平线(上海)人工智能技术有限公司 计算机实现张量数据计算的方法、装置、介质和设备
KR20220053973A (ko) 2020-10-23 2022-05-02 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그 동작 방법
CN116955241B (zh) * 2023-09-21 2024-01-05 杭州智灵瞳人工智能有限公司 兼容多类型存储介质的存储芯片
CN117519802B (zh) * 2024-01-08 2024-04-30 之江实验室 基于存算一体单元的数据处理装置

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459846A (en) * 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
EP0617363B1 (en) * 1989-04-13 2000-01-26 SanDisk Corporation Defective cell substitution in EEprom array
JP2862948B2 (ja) * 1990-04-13 1999-03-03 三菱電機株式会社 半導体記憶装置
DE69324508T2 (de) * 1992-01-22 1999-12-23 Enhanced Memory Systems Inc DRAM mit integrierten Registern
JP3904244B2 (ja) * 1993-09-17 2007-04-11 株式会社ルネサステクノロジ シングル・チップ・データ処理装置
US6029224A (en) * 1995-06-07 2000-02-22 Lucent Technologies Inc. Self-contained memory apparatus having diverse types of memory and distributed control
US6230235B1 (en) * 1996-08-08 2001-05-08 Apache Systems, Inc. Address lookup DRAM aging
GB2317722B (en) * 1996-09-30 2001-07-18 Nokia Mobile Phones Ltd Memory device
US6212597B1 (en) * 1997-07-28 2001-04-03 Neonet Lllc Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like
US6336174B1 (en) * 1999-08-09 2002-01-01 Maxtor Corporation Hardware assisted memory backup system and method
US6427196B1 (en) * 1999-08-31 2002-07-30 Intel Corporation SRAM controller for parallel processor architecture including address and command queue and arbiter
US6694380B1 (en) * 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
JP3871853B2 (ja) * 2000-05-26 2007-01-24 株式会社ルネサステクノロジ 半導体装置及びその動作方法
US6836839B2 (en) * 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
JP2003006041A (ja) * 2001-06-20 2003-01-10 Hitachi Ltd 半導体装置
GB0123416D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Non-volatile memory control
US6986021B2 (en) * 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
TWI282513B (en) * 2002-06-12 2007-06-11 Mediatek Inc A pre-fetch device of instruction for an embedded system
US7478031B2 (en) * 2002-11-07 2009-01-13 Qst Holdings, Llc Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information
US8276135B2 (en) * 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
CN1717662B (zh) * 2002-11-28 2010-04-28 株式会社瑞萨科技 存储器模块、存储器***和信息仪器
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US20050050261A1 (en) * 2003-08-27 2005-03-03 Thomas Roehr High density flash memory with high speed cache data interface
US7657706B2 (en) * 2003-12-18 2010-02-02 Cisco Technology, Inc. High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory
US7173863B2 (en) * 2004-03-08 2007-02-06 Sandisk Corporation Flash controller cache architecture
US20050220115A1 (en) * 2004-04-06 2005-10-06 David Romano Method and apparatus for scheduling packets
US20060095622A1 (en) * 2004-10-28 2006-05-04 Spansion, Llc System and method for improved memory performance in a mobile device
TWM286985U (en) * 2005-08-22 2006-02-01 Regulus Technologies Co Ltd Memory module with smart-type power-saving and fault-tolerance
US7376034B2 (en) * 2005-12-15 2008-05-20 Stec, Inc. Parallel data storage system
US20070143547A1 (en) * 2005-12-20 2007-06-21 Microsoft Corporation Predictive caching and lookup
US20070147115A1 (en) * 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
US7996600B2 (en) * 2007-08-30 2011-08-09 Unity Semiconductor Corporation Memory emulation in an electronic organizer
US7802057B2 (en) * 2007-12-27 2010-09-21 Intel Corporation Priority aware selective cache allocation
US8108614B2 (en) * 2007-12-31 2012-01-31 Eric Sprangle Mechanism for effectively caching streaming and non-streaming data patterns
US8615499B2 (en) * 2012-01-27 2013-12-24 International Business Machines Corporation Estimating data reduction in storage systems

Also Published As

Publication number Publication date
KR20090108707A (ko) 2009-10-16
EP2122473A2 (en) 2009-11-25
CN101611387A (zh) 2009-12-23
KR101469512B1 (ko) 2014-12-05
TWI463321B (zh) 2014-12-01
CN101611387B (zh) 2013-03-13
US9424182B2 (en) 2016-08-23
TWI530791B (zh) 2016-04-21
TW200839519A (en) 2008-10-01
TW201523261A (zh) 2015-06-16
WO2008086488A2 (en) 2008-07-17
US8918618B2 (en) 2014-12-23
US20090024819A1 (en) 2009-01-22
US20140013039A1 (en) 2014-01-09
US8504793B2 (en) 2013-08-06
US20150074344A1 (en) 2015-03-12
EP2122473B1 (en) 2012-12-05
US20120131269A1 (en) 2012-05-24
WO2008086488B1 (en) 2008-10-23
WO2008086488A3 (en) 2008-09-04
EP2122473A4 (en) 2011-06-08
US8135933B2 (en) 2012-03-13

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