HK1028831A1 - Apparatus and method for fabric ordering load/store to input/output device and direct memory access peer-to-peer transactions - Google Patents

Apparatus and method for fabric ordering load/store to input/output device and direct memory access peer-to-peer transactions

Info

Publication number
HK1028831A1
HK1028831A1 HK00108160A HK00108160A HK1028831A1 HK 1028831 A1 HK1028831 A1 HK 1028831A1 HK 00108160 A HK00108160 A HK 00108160A HK 00108160 A HK00108160 A HK 00108160A HK 1028831 A1 HK1028831 A1 HK 1028831A1
Authority
HK
Hong Kong
Prior art keywords
peer
store
input
output device
memory access
Prior art date
Application number
HK00108160A
Other languages
English (en)
Inventor
Danny Marvin Neal
Steven Mark Thurber
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of HK1028831A1 publication Critical patent/HK1028831A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
HK00108160A 1998-12-28 2000-12-18 Apparatus and method for fabric ordering load/store to input/output device and direct memory access peer-to-peer transactions HK1028831A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/221,936 US6347349B1 (en) 1998-12-28 1998-12-28 System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction

Publications (1)

Publication Number Publication Date
HK1028831A1 true HK1028831A1 (en) 2001-03-02

Family

ID=22830047

Family Applications (1)

Application Number Title Priority Date Filing Date
HK00108160A HK1028831A1 (en) 1998-12-28 2000-12-18 Apparatus and method for fabric ordering load/store to input/output device and direct memory access peer-to-peer transactions

Country Status (6)

Country Link
US (1) US6347349B1 (xx)
CN (1) CN1135479C (xx)
HK (1) HK1028831A1 (xx)
MY (1) MY124338A (xx)
SG (1) SG87866A1 (xx)
TW (1) TW460787B (xx)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6976115B2 (en) * 2002-03-28 2005-12-13 Intel Corporation Peer-to-peer bus segment bridging
US7077838B2 (en) 2002-05-30 2006-07-18 Visx, Incorporated Variable repetition rate firing scheme for refractive laser systems
US7529875B2 (en) * 2003-08-20 2009-05-05 International Business Machines Corporation Assigning interrupts for input/output (I/O) devices among nodes of a non-uniform memory access (NUMA) system
US7725618B2 (en) * 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
US7712096B2 (en) * 2004-12-21 2010-05-04 International Business Machines Corporation Method, system, and storage medium for dynamically reordering resource participation in two-phase commit to heuristically optimize for last-agent optimization
US7386642B2 (en) 2005-01-28 2008-06-10 Sony Computer Entertainment Inc. IO direct memory access system and method
US7680972B2 (en) * 2005-02-04 2010-03-16 Sony Computer Entertainment Inc. Micro interrupt handler
JP2006216042A (ja) * 2005-02-04 2006-08-17 Sony Computer Entertainment Inc 割り込み処理のためのシステムおよび方法
WO2007071889A1 (en) * 2005-12-22 2007-06-28 Arm Limited Arbitration method reordering transactions to ensure quality of service specified by each transaction
US7908255B2 (en) * 2007-04-11 2011-03-15 Microsoft Corporation Transactional memory using buffered writes and enforced serialization order
US7861024B2 (en) * 2008-09-30 2010-12-28 Intel Corporation Providing a set aside mechanism for posted interrupt transactions
US20110119469A1 (en) * 2009-11-13 2011-05-19 International Business Machines Corporation Balancing workload in a multiprocessor system responsive to programmable adjustments in a syncronization instruction
US11030102B2 (en) * 2018-09-07 2021-06-08 Apple Inc. Reducing memory cache control command hops on a fabric

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485455A (en) 1994-01-28 1996-01-16 Cabletron Systems, Inc. Network having secure fast packet switching and guaranteed quality of service
US5664223A (en) 1994-04-05 1997-09-02 International Business Machines Corporation System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
US5805924A (en) 1994-11-08 1998-09-08 Stoevhase; Bent Method and apparatus for configuring fabrics within a fibre channel system
US5694556A (en) 1995-06-07 1997-12-02 International Business Machines Corporation Data processing system including buffering mechanism for inbound and outbound reads and posted writes
US5610745A (en) 1995-10-26 1997-03-11 Hewlett-Packard Co. Method and apparatus for tracking buffer availability
US6108741A (en) * 1996-06-05 2000-08-22 Maclaren; John M. Ordering transactions
US5887138A (en) 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US5905876A (en) * 1996-12-16 1999-05-18 Intel Corporation Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
US6138192A (en) * 1996-12-31 2000-10-24 Compaq Computer Corporation Delivering a request to write or read data before delivering an earlier write request

Also Published As

Publication number Publication date
SG87866A1 (en) 2002-04-16
US6347349B1 (en) 2002-02-12
CN1135479C (zh) 2004-01-21
TW460787B (en) 2001-10-21
CN1259702A (zh) 2000-07-12
MY124338A (en) 2006-06-30

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20071209