HK1002241A1 - Cache memory control system - Google Patents

Cache memory control system

Info

Publication number
HK1002241A1
HK1002241A1 HK98101188A HK98101188A HK1002241A1 HK 1002241 A1 HK1002241 A1 HK 1002241A1 HK 98101188 A HK98101188 A HK 98101188A HK 98101188 A HK98101188 A HK 98101188A HK 1002241 A1 HK1002241 A1 HK 1002241A1
Authority
HK
Hong Kong
Prior art keywords
control system
cache memory
memory control
cache
memory
Prior art date
Application number
HK98101188A
Other languages
English (en)
Inventor
Toshikatsu Mori
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62033495A external-priority patent/JPS63201852A/ja
Priority claimed from JP62060207A external-priority patent/JPS63226751A/ja
Application filed by Nec Corp filed Critical Nec Corp
Publication of HK1002241A1 publication Critical patent/HK1002241A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
HK98101188A 1987-02-18 1998-02-16 Cache memory control system HK1002241A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62033495A JPS63201852A (ja) 1987-02-18 1987-02-18 キヤツシユメモリのアクセス制御方式
JP62060207A JPS63226751A (ja) 1987-03-17 1987-03-17 キヤツシユメモリのバスエラ−制御方式

Publications (1)

Publication Number Publication Date
HK1002241A1 true HK1002241A1 (en) 1998-08-07

Family

ID=26372199

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98101188A HK1002241A1 (en) 1987-02-18 1998-02-16 Cache memory control system

Country Status (6)

Country Link
EP (2) EP0279421B1 (fr)
AU (2) AU602952B2 (fr)
CA (1) CA1299767C (fr)
DE (1) DE3855893T2 (fr)
HK (1) HK1002241A1 (fr)
SG (1) SG45227A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3812858A1 (de) * 1988-04-18 1989-10-26 Siemens Ag Verfahren zur kennzeichnung ungueltiger eintraege in einem speicher, insbesondere in einem cache-speicher, und anordnung zur durchfuehrung des verfahrens
EP0382396A3 (fr) * 1989-02-08 1991-11-27 Hitachi, Ltd. Tampon de mémoire de programme pour processeur
US5257359A (en) * 1989-02-08 1993-10-26 Hitachi Microsystems, Inc. Instruction cache buffer with program-flow control
US5197144A (en) * 1990-02-26 1993-03-23 Motorola, Inc. Data processor for reloading deferred pushes in a copy-back data cache
US5659712A (en) * 1995-05-26 1997-08-19 National Semiconductor Corporation Pipelined microprocessor that prevents the cache from being read when the contents of the cache are invalid
GB2390700B (en) 2002-04-15 2006-03-15 Alphamosaic Ltd Narrow/wide cache

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1123964A (fr) * 1978-10-26 1982-05-18 Anthony J. Capozzi Hierarchie integree de stockage a niveaux multiples pour systeme de traitement de donnees
JPS5577070A (en) * 1978-12-01 1980-06-10 Toshiba Corp Cash memory control system
US4459666A (en) * 1979-09-24 1984-07-10 Control Data Corporation Plural microcode control memory
GB2127189B (en) * 1982-09-18 1986-11-05 Int Computers Ltd Automatic invalidation of validity tags in data store
DE3751642T2 (de) * 1986-10-17 1996-09-05 Amdahl Corp Verwaltung von getrennten Befehls- und Operanden-Cachespeichern
AU604101B2 (en) * 1987-04-13 1990-12-06 Computervision Corporation High availability cache organization

Also Published As

Publication number Publication date
CA1299767C (fr) 1992-04-28
EP0655689A2 (fr) 1995-05-31
AU5860890A (en) 1990-10-11
EP0655689A3 (fr) 1995-10-11
DE3855893D1 (de) 1997-06-05
EP0279421A3 (fr) 1990-10-17
AU1179188A (en) 1988-08-25
AU617948B2 (en) 1991-12-05
EP0279421A2 (fr) 1988-08-24
SG45227A1 (en) 1998-01-16
AU602952B2 (en) 1990-11-01
EP0279421B1 (fr) 1997-05-02
DE3855893T2 (de) 1997-08-14

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Legal Events

Date Code Title Description
PF Patent in force
PE Patent expired

Effective date: 20080216