GB947723A - Storage devices - Google Patents

Abstract

947,723. Pulse storage circuits. STANDARD TELEPHONES & CABLES Ltd. Jan. 13, 1961 [Jan. 19, 1960], No. 1557/61. Heading H3B. To overcome the effects of contact bounce which spoils the waveform of metering pulses to be registered in a first matrix M1, the elements of which are read out cyclically and each of which has an input from the metering relay of a telephone subscriber, a bit read out of an element in the first matrix M1 is transferred to a main store H and is also registered in the corresponding element of a second matrix M2 which duplicates all the elements of M1, the presence of an output from this element in matrix M2 in the next interrogation cycle inhibiting the transfer of any output from the corresponding element in matrix M1 to the main store H. The matrices M1, M2 are ferrite core arrays which are read out and reset in synchronism by the same source A. If the metering pulses are mutilated by contact bounce as shown by waveform a of Fig. 3, and are interrogated by the narrow pulses shown by waveform b of Fig. 3, then it is possible when an interrogation coincides with a mutilation of a metering pulse that a core will have been switched sufficiently to provide an output to interrogation and will be switched again by the remainder of the metering pulse so as to give a second and spurious output at the next interrogation. It is arranged, however, that the first output from a core in matrix M1, over an amplifier and sneak suppressor L1, is transferred to the main store H and also sets the core corresponding to itself in the matrix M2. At the next interrogation of these particular cores the output from matrix M2 over amplifier and sneak suppressor L2 inhibits a gate V to prevent transfer of a spurious output from matrix M1 and in the event of such a spurious output prevents its re-registration in matrix M2. The inhibition circuitry is simplified if the first output from a core in matrix M1 is not only written in the corresponding core in matrix M2 but is also re-written in the matrix M1 so that the next interrogation will always produce signals in opposition from M1 and M2. The outputs of the matrices M1 and M2 are staticized by bi-stable circuits F1, F2, so that they may control the subsequent writing functions.