GB8510147D0 - Computer systems - Google Patents

Computer systems

Info

Publication number
GB8510147D0
GB8510147D0 GB858510147A GB8510147A GB8510147D0 GB 8510147 D0 GB8510147 D0 GB 8510147D0 GB 858510147 A GB858510147 A GB 858510147A GB 8510147 A GB8510147 A GB 8510147A GB 8510147 D0 GB8510147 D0 GB 8510147D0
Authority
GB
United Kingdom
Prior art keywords
computer systems
systems
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB858510147A
Other versions
GB2173929A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ITT Industries Ltd
Original Assignee
ITT Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ITT Industries Ltd filed Critical ITT Industries Ltd
Priority to GB08510147A priority Critical patent/GB2173929A/en
Publication of GB8510147D0 publication Critical patent/GB8510147D0/en
Publication of GB2173929A publication Critical patent/GB2173929A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
GB08510147A 1985-04-20 1985-04-20 Computer systems Withdrawn GB2173929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08510147A GB2173929A (en) 1985-04-20 1985-04-20 Computer systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08510147A GB2173929A (en) 1985-04-20 1985-04-20 Computer systems

Publications (2)

Publication Number Publication Date
GB8510147D0 true GB8510147D0 (en) 1985-05-30
GB2173929A GB2173929A (en) 1986-10-22

Family

ID=10577965

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08510147A Withdrawn GB2173929A (en) 1985-04-20 1985-04-20 Computer systems

Country Status (1)

Country Link
GB (1) GB2173929A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2225882A (en) * 1988-12-06 1990-06-13 Flare Technology Limited Computer bus structure for multiple processors
US5060139A (en) * 1989-04-07 1991-10-22 Tektronix, Inc. Futurebus interrupt subsystem apparatus
US9519603B2 (en) 2013-09-09 2016-12-13 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9996488B2 (en) 2013-09-09 2018-06-12 Qualcomm Incorporated I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
US9690725B2 (en) 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
EP3055929A1 (en) 2013-10-09 2016-08-17 Qualcomm Incorporated ERROR DETECTION CAPABILITY OVER CCIe PROTOCOL
US9684624B2 (en) 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800287A (en) * 1972-06-27 1974-03-26 Honeywell Inf Systems Data processing system having automatic interrupt identification technique
US3836889A (en) * 1973-03-23 1974-09-17 Digital Equipment Corp Priority interruption circuits for digital computer systems
US3815105A (en) * 1973-09-26 1974-06-04 Corning Glass Works Priority interrupt system
IT1145730B (en) * 1981-11-13 1986-11-05 Olivetti & Co Spa DATA PROCESSING SYSTEM WITH PROGRAM INTERRUPTION CONTROL DEVICE
DE3233542A1 (en) * 1982-09-10 1984-03-15 Philips Kommunikations Industrie AG, 8500 Nürnberg METHOD AND CIRCUIT FOR DELIVERING INTERRUPT REQUEST SIGNALS

Also Published As

Publication number Publication date
GB2173929A (en) 1986-10-22

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)