809,507. Digital electric calculating-apparatus; electric digital-data-storage apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. Sept. 16, 1955 [Sept. 16, 1954], No. 26629/55. Class 106 (1). In an electric digital programme-sequencecontrolled computer comprising a low-speed access main store in which the storage locations are distributed in groups of n units, and a highspeed access instruction store with p locations (p being equal to n or a submultiple of n), means are provided for ensuring that whenever predetermined parts of the addresses of two consecutive instructions differ, either during the normal programme sequence or owing to a sequence interruption, a group of p instructions is transferred from the main store to the highspeed store. As described, the main store of the computer comprises a magnetic drum MM, Fig. 3, having 64 tracks each storing 128 words in minor cycles Cm, Fig. 1, each comprising 23 binary digit pulse periods d1-d23 of duration #. An instruction word comprises portions R, T, L and F for special indications, time address, spatial (track) address and function, the d23 position comprising a gap G. The time address represents the position of a word along a track and corresponds to time address signals CT, denoting consecutively addresses (0) to (127), recorded on a further track of the drum. The pulse periods are defined by pulses TR and major cycles or revolutions of the drum by a pulse CM recorded on other tracks. The pulses TR are passed to a distributer D1 which supplies on 23 separate outputs the respective digit pulses including the d23 minor cycle pulses TL. The sequence of computer operations is controlled by a switch CO comprising a delay line loop in which an instruction address is circulated ; the loop includes an adder whereby " 1 " may be added to the address when a pulse is supplied to input 5. The T and L address portions are supplied to outputs 15 and 18 respectively, and the old and new addresses are supplied via lines 13 and 14 respectively to a comparison device including an anti-coincidence circuit which routes a pulse at 31 to output 38 or 37 according to whether the L address portions differ or not. These outputs respectively control the transfer of a batch of instructions from the drum to high-speed store 43, and the read out of a single instruction from store 43 to instruction store MO. The output at 38 sets bi-stable trigger device 62, e.g. an Eccles-Jordan circuit, which, when reset by the next pulse CM via small delay 67, supplies a setting pulse through condenser 65 to bi-stable device 64 which then opens gates 47 and 52. The complete contents of the track selected by circuit 40 under control of the L-address from 18 are then transferred to routing arrangement 44, controlled by signals CT, which distributes the 128 words to separate storage locations, e.g. delay line loops, in store 43. After a major cycle, a further pulse CM resets 64 which sends a setting pulse via small delay 39 to bi-stable device 57 which opens gate 49 to allow a single instruction word, selected by routing arrangement 45 under control of the T-address from 15, to pass to MO and to be decoded in DO. Where the instruction involves an interruption of the control sequence, the new instruction address is supplied to input 7 of switch CO. At the end of a minor cycle, pulse TL resets 57 which sends a setting pulse to bi-stable device 59 whose output 60 controls the carrying out of the instruction; this pulse, after delay in 61, also provides the " 1 "-representing input at 5 to CO. An end-of-instruction pulse from circuit 32 resets 59 and, via gate 70, provides the comparison input at 31. As the pulse will now pass to 37, device 57 is again set, and the above sequence of reading out instructions from 43 is repeated until all the instructions have been used when the control address in CO will indicate a new track (by a carry into the d10 position, Fig. 1) and output 38 will be effective to transfer a further batch of instructions to store 43. Operations are started by switch 71 which sets device 62 to effect a first batch transfer, and sets device 69 to open gate 70, and are stopped by switch 72 which resets 69. In a modification (Fig. 4, not shown), the high-speed store receives the contents of only one half of a track of the drum, the gates 47 and 52 being opened for one half of a major cycle.