784,155. Electric digital-data-storage apparatus; digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 24, 1954 [Dec. 31, 1953], No. 37384/54. Class 106 (1). An input data transfer device for a machine adapted to process data read from a magnetic record medium, the medium carrying groups of electric-pulse-producing bits recorded on separate tracks and read on to separate pulse entry lines, comprises a first and second register for each entry line, a circuit normally interconnectnecting each pair of registers whereby a pulse on the corresponding entry line will be entered in both, means for generating a timing pulse effective to disable the interconnecting circuit and to reset the first register whereby the pulses are entered in the first registers only, and means for discharging pulses in parallel from the second registers into a storage register. This enables a group of bits to be entered in the first registers at the same time as a previously read group is being discharged from the second registers. General. The input-output device described is for transferring data between magnetic tape and an electrostatic memory (see Fig. 1) of an electronic digital computer (not described in detail) via an MQ (multiplier-quotient) register comprising a ring of 36 stages S (for sign) and 1-35, Fig. 3, around which data can be shifted. A " memory bus " 62, Fig. 1, allows a 36-bit binary word to be entered in parallel from a " memory register " into the MQ register, and allows the output of the latter to be connected to the electrostatic memory, through selectively operated switches. An I/O (input-output) bus 64 connects the MQ register with one of four tape units, e.g. as described in Specification 733,807, [Group XXXV]. A word is recorded on the tape in groups of 6 bits on 6 separate tracks, Fig. 2, check bits R in a 7th track being such as to make the total numbers of " 1 "s recorded across the tape add. A word in the MQ register is shifted left for recording on a tape, the bits being taken 6 at a time from stages 30-35 and combined with a check bit as indicated in Fig. 3. When reading from a tape, the data bits are entered in groups into stages 9-5 and shifted left or right according to whether the tape is being fed forward or backward, the check bit being entered into a separate checking circuit. The input/output device comprises electronic circuits consisting mainly of standard units (circuit diagrams given) including double triode trigger circuits and AND and OR diode circuits. MQ register. Each of the 36 stages comprises a storage loop including a 1 Ás. delay unit as described in Specification 719,418, [Group XL (c)], and AND switching circuits whereby a data pulse may be continuously recirculated, or may be shifted to the next adjacent stage to the left or right, as described in Specification 721,180. The storage loop for any of stages 2-5, Fig. 12, for example, comprises an OR circuit, cathode follower CF and delay unit D connected via line 370 and AND circuit 360 rendered operative by a " Hold MQ " potential on line 72. For shifting left or right, AND circuit 750B or 850 is operative in place of 360 and passes the next higher or next lower bit into the delay unit. Data is entered from the I/O bus via AND circuit 736B. Tape units. Associated with each tape are 7 read-write heads comprising coils 75, Fig. 20, one for each track, and an erase coil. Bits are recorded by producing a change of flux for a " 1 " and no change for "0", successive " 1 "s being written by feeding current alternately through one half or the other of a coil 75. In reading, a " 1 " may produce a pulse of either polarity in the coil, such pulses being passed through a shaping and amplifying circuit Figs. 23 and 24, not shown) which produces a standard " 1 "representing pulse on a line 492, Fig. 33. MQ register to tape. The writing of a word stored in the MQ register on to a tape is controlled by a counter (not shown) comprising bistable trigger circuits stepped on by timing pulses. The word is first shifted 6 digits to the left by applying a 6 Ás. pulse to line 66, Fig. 12, thus shifting the group of digits in stages 9-5 into stages 30-35 (by way of the " ring shift " path, Fig. 3). The digits, as they are shifted through stage 5, are applied to a " tape redundancy counter " comprising a bi-stable trigger circuit (Fig. 29, not shown) which is switched from one condition to the other by every 2 " received whereby its final condition determines whether a " 1 " should be written in the check bit position. The outputs of this trigger and of stages 30-35 are applied through cathode followers CF to AND circuits 340, 412 ... 422, Fig. 18, which are rendered operative simultaneously by a " write tape group " pulse to cause a group of bits to be written across the tape by selective energization of coils 75, Fig. 20, under control of bi-stable trigger circuits (Fig. 19, not shown). The process of 6-digit shifts and group recording is repeated until the whole word has been written when a " tape group counter " (Fig. 31, not shown) emits a " tape word complete " signal which conditions the tape write control circuits to enable another word to be written from the memory register, Fig. 1, into the MQ register, or otherwise to disconnect the tape unit. Tape to MQ register. The tape-reading circuits are especially designed to deal with "skew ", i.e. the feeding of the tape at an angle relative to the read-write heads due to tolerances in the tape-feeding mechanism; this results in a delay (" skew period ") between the reading of the first and the last of a transverse group of 7 bits. The problems of skew are discussed in detail in the Specification. Fig. 38 illustrates the minimum permissible distance between bits on a given track of a tape; since the relationship of heads and bits may be reversed during reading and writing, at least two " skew periods " will be required (the " skew delay " of Fig. 39) plus a "gate length to allow time for the bits to enter the MQ register. When reading a group of 7 bits, the signal on each line 492 is applied through the circuits shown in Fig. 33 to a first bi-stable trigger 496 (register 1, Fig. 39). At the same time, all such signals are applied in parallel to control-read circuits (Figs. 32 and 17, not shown), including a timing counter; the first " 1 " pulse initiates a skew delay signal, Fig. 39, during which the whole of the group of bits must be read. As soon as a shift tape registers line 788, Fig. 33, goes positive (indicating that the required period for entering a prior group, if any, into the MQ register has ended (see Fig. 39, especially groups B and C), an AND circuit 498 is rendered operative so that the setting of 496 is applied to a second trigger 502 (register 2, Fig. 39). At the end of the skew delay the potential on line 788 falls, thus isolating 502 from 496, and the latter is reset and can now accept new information from the tape. During the following " line charge period, Fig. 39, the outputs from triggers 502 " charge up " the I/O lines of the MQ register, after which (" access to MQ " period, Fig. 39) the data bits are entered into register stages 9-5, Fig. 1. When the tape is being read forward, the bits are shifted 6 stages left, as in the writing operation, and during the passage through stage 9, control the " tape redundancy counter " whose initial setting is determined by the check bit. If the final count of " 1 "s is even, an error is indicated, e.g. by a neon lamp. During a backward read operation, when the bits are shifted right, stage 5 controls the redundancy counter. After the " access to MQ " period, the line 788 goes positive, and resets each trigger 502, Fig. 33, through an inverter Is. The next group of bits can then be accepted from 496, the process being repeated until a whole word has been entered into the MQ register when a " tape word complete signal will be obtained as in the writing operation. During backward read, a final 6-digit left shift (without check) is necessary to position the word correctly. Specification 784,330 also is referred to.