GB764522A - Improvements in or relating to electronic computers - Google Patents

Abstract

764,522. Digital electric calculating apparatus. COMPAGNIE DES MACHINES BULL. July 2, 1953 [July 2, 1952; July 2, 1952; Oct. 23, 1952], No. 18334/53. Class 106 (1). An electronic, cyclically operating computer comprises a plurality of number stores each having entry control means and being capable of receiving series of pulses representing codeddecimal digits, one store (MO) including an algebraic adder unit, connections permitting the transfer of numbers from the store MO to the other stores, or vice versa, an order transmitter (TO) defining the type of operation to be effected and an order transmitter (AD) defining the address of the number store used during an operation; the computer is characterized in that it comprises two further order transmitters adapted to define respectively (i) the numeral of the beginning order (OD) and (ii) the numeral of the end order (OF), these numerals indicating the limits of a partial zone of a number store, and a circuit arrangement called a " filtering comparator " cooperating with the last-mentioned order transmitters and exercising further control over entry to the number stores, whereby, when a determined number store has been selected for an entry under the joint control of order transmitters TO and AD, the entry control means of this store is energized so that only the partial zone defined by the numerals OD and OF is taken into consideration. Figs. 17a and 17b show the general arrangement of the computer with circulating serial memories S1 ... S4 and a similar memory MO provided with an addersubtractor. All the storage devices are of the closed-loop circuit type, consisting of one or more electromagnetic delay elements and pulse reshapers or pulse regenerators of the type described in Specifications 711,240 and 764,521, [both in Group XL (c)]. CC and CG are comparing devices of a " sequence unit " which controls the operations of a number of pulse generators Gz, Gp, Gl, G1, G2 and G3, described as " phase selectors." The comparing devices are similar to that described in Specification 730,297. There is an auxiliary memory MD and a counter-discounter CD. AC represents the accumulator of a tabulating machine with which the computer is associated. The apparatus is generally similar to that described in Specification 764,523, which is referred to. The following description is therefore confined to the characteristic features mentioned above. Order transmitters OD, OF. These store numbers representing the time positions of the lowest and highest digits, respectively, of a number allocation in a storage memory defined by order transmitter AD. Each of the numbers is stored in serial form in a single loop 75, Fig. 5, having a capacity of four binary digits. A line selection pyramid 78 connects the appropriate plug socket 77 to input circuits of the storage loop and, under control of four gates 81 to 84, four binary elements of the number are passed into the storage loop, from which they control the aligning process described below. Operation " OB." This programme operation serves to illustrate the use of order transmitters OD, OF. It consists in transferring an amount from the arithmetic storage memory MO to a storage Sn defined by the order transmitter AD. It should be noted that more than one amount can be stored in a memory loop, these storage loops having a capacity, in the embodiment described, of twelve decimal digits. There are three stages in the operation. During the first, referred to as the " framing stage," the amount circulating in MO is brought to a position relative to the store Sn to which it is to be transferred, equivalent to the position in that store defined by the numbers in OD, OF. The relative location of the amount in MO is represented by a number lodged in an auxiliary store MD, and this number is transferred to the counter-discounter CD for reduction by one unit during the same period that a change in the length of MO accomplishes a shift of the amount stored therein by one unit. This procedure is repeated as many times as necessary. The comparator CC determines when the numbers in OD and MD are equal and initiates the second stage during which the digits between those positions in the selected storage Sn defined by the numbers stored in OD and OF, are erased. A device described as a " filtering comparator " FC is employed at this stage. It comprises a counter similar to CD, but counting decimal periods only, and a comparator proper which compares the number stored in OD with the number in the counter. This starts from zero in a time cycle common with that of the storage memories S1 ... Sn. A train of erasing or " filtering " pulses is emitted when equality is detected and continues until a similar comparison with the number in OF terminates the erasing process. The third stage of transfer of the contents of MO into the selected store Sn, by gating the series train of binary-coded decimal pulses from the one storage loop to the other, takes place when the train of " filtering " pulses mentioned above terminates. Coding of zeros. During the second, or erasing, stage of an operation, OB, any zeros situated to the right of the highest significant decimal digit of the amount concerned are detected and arrangements made to represent each of these by binary pulses " 2 " and " 8 " when the transfer stage occurs so as to distinguish these zeros from those to the left of the highest significant digit. The printing apparatus includes means for detecting the coded zeros for printing. Other programme operations including addition and subtraction are described and the following Specifications also are referred to: 740,756 and 742,869.