GB740404A - Electrical multiplication circuit - Google Patents

Abstract

740,404. Pulse circuits. STANDARD TELEPHONES & CABLES, Ltd. June 19, 1953 [June 26, 1952], No. 17035/53. Class 40 (6). [Also in Group XIX] A calculating circuit (see Groups XIX) employs, between stages of a binary counter, discriminating or gating networks each such that a single pulse at a or c produces an output pulse at b while coincident pulses cause an output at d and not b. In Fig. 12, a negative pulse at a or c will cut off one side of a double triode V2, thus increasing the current through the other side and lowering its anode potential so that a negative pulse is passed to b through rectifier r4 ot r5 and capacitor C. However, coincident pulses at a and c will cut off both sides of the triode, thus lowering the potential at the commoned cathodes which are connected to d. The alternative embodiment shown in Fig. 13 responds to positive pulses and comprises " or " and " and " gates comprising rectifiers r9, r10 and r6, r7 respectively. The coincidence output pulse at d is also passed to the grid of a triode V3 which then becomes conductive and prevents b going positive. In a simplified arrangement (Fig. 14, not shown) for the case where a pulse is always present at c when a pulse appears at a, the rectifier gates are omitted.