GB674952A - Improvements in and relating to calculating apparatus - Google Patents

Improvements in and relating to calculating apparatus

Info

Publication number
GB674952A
GB674952A GB805449A GB805449A GB674952A GB 674952 A GB674952 A GB 674952A GB 805449 A GB805449 A GB 805449A GB 805449 A GB805449 A GB 805449A GB 674952 A GB674952 A GB 674952A
Authority
GB
United Kingdom
Prior art keywords
line
pulse
trigger
over
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB805449A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WILLIAM WOODS HILL
British Tabulating Machine Co Ltd
Original Assignee
WILLIAM WOODS HILL
British Tabulating Machine Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to NL666611639A priority Critical patent/NL152498B/en
Priority to NL80783D priority patent/NL80783C/xx
Application filed by WILLIAM WOODS HILL, British Tabulating Machine Co Ltd filed Critical WILLIAM WOODS HILL
Priority to GB805449A priority patent/GB674952A/en
Priority to US147441A priority patent/US2745599A/en
Priority to FR1032554D priority patent/FR1032554A/en
Priority to US202917A priority patent/US2690507A/en
Priority to US202916A priority patent/US2623115A/en
Publication of GB674952A publication Critical patent/GB674952A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491Computations with decimal numbers radix 12 or 20.
    • G06F7/498Computations with decimal numbers radix 12 or 20. using counter-type accumulators
    • G06F7/4983Multiplying; Dividing
    • G06F7/4986Multiplying; Dividing by successive multiplication or division by 2

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
  • Electrotherapy Devices (AREA)
  • Particle Accelerators (AREA)

Abstract

674,952. Digital electric calculating-apparatus. BRITISH TABULATING MACHINE CO., Ltd., HILL, W. WOODS-, and DAVIS, D. T. March 7, 1950 [March 24, 1949], No. 8054/49. Class 106 (i). In an electronic multiplier comprising a pulse generator 31, Fig. 1, a pulse emitter 30, a multiplier register 41, multiplicand register 42, and product counter 43, each register has one or more trigger stages in each denomination, the multiplier and multiplicand are repeatedly halved and doubled, respectively, under control of the emitter by applying pulses to all the trigger stages, and the multiplicand value is transmitted to the counter 43 whenever the multiplier value is odd, as determined by odd/ even detector F2, Q. General operation. The apparatus shown is for multiplying a monetary by a decimal amount. The emitter comprises 19 units which are operated successively under control of the generator 31 and half-cycle control unit 100 to supply control pulses to lines 34b during one " half-cycle," for odd/even detection and trans. mission of the multiplicand, and lines 34 during the next, to effect one halving and doubling operation. Once the emitter sequence is started by depressing key 90 of start control unit 39, it continues for a fixed number of cycles determined by counter 40. The denominations of the registers 41, 42 and counter 43 (except that for 10 shillings) each comprise a binary counter consisting of four trigger stages representing values 1, 2, 4 and 8, respectively. Pulse generator. A square waveform from the anode of triode 107 of a multivibrator MV, Fig. 3, is applied to the grids of triodes 112, 113 of a shaping trigger circuit 97. The successive triggering causes positive anode pulses to be applied alternately to the grids of valves 98, 99 so that negative pulses are produced alternately on lines 32, 33, Fig. 1, for controlling emitter units 30. Also, positive anode pulses are sent over line 86 to the unit 39. Start control unit. The pulses on line 86 are applied to the control grids of pentodes T1, T2, Fig. 4, and, in the position shown, key 90 connects the suppressor grid of T1 to earth line 1, while the suppressor grid of T2 is connected to negative supply line 15. Thus negative pulses are produced at the anode of T1 and switch over trigger circuit U, V so that valve V conducts. When the key is depressed, anode pulses from T2 switch back the trigger and a negative anode pulse from valve U over line 92 switches over trigger X, Y, thus raising the suppressor grid potential of a valve Z and sending a negative pulse over line 87 to the first emitter unit 30 (1). Emitter; cycle control. The pulse over line 87 switches over a trigger pair of valves 105, 132, Fig. 2, which is switched back by a pulse over line 32. The consequent negative pulse on line 131 switches over the trigger pair of unit 30(2), Fig. 1, which is switched back by a pulse over line 33 and so on to unit 30(19) which tends a positive pulse over line 38 to the control grid of valve Z, Fig. 4, and the resultant negasive anode pulse is sent over line 89 to reoperate unit 30(1), Fig. 2. Unit 30(19) also sends a negative pulse to unit 100, Fig. 1, thus switching over a pair of trigger valves (not shown), each connected to a cathode follower from which lines 36, 37 extend to the suppressor grids of emitter gate valves such as 134, 133, Fig. 2. During each half-cycle one of the lines is at high potential so that when, e.g., unit 30(1) is operated, the positive pulse from the anode of valve 105 to the control grids of valves 133, 134 produces a negative control pulse on the corresponding line 34 or 34b. The sequence continues until the binary counter 40, Fig. 1, comprising four series-connected trigger circuits, has received 16 pulses over line 117 from unit 30(19), when a negative pulse will be sent over line 88 to switch back trigger X, Y, Fig. 4, so that valve Z will no longer pass anode current when a pulse is received over line 38. Eight full cycles will then have been completed. Auxiliary control units. Various units 46, 54 and 58, Fig. 1, are provided which receive and reverse the polarity of the emitter outputs on lines 34, 34b. In each unit 54, line 34 is connected to the grid of a normally conducting valve H, Fig. 5, whose anode is connected to a cathode-follower J, so that a negative pulse on line 34 will produce a positive pulse on line 17 (or 18, Fig. 1). Unit 58 is similar, valve H being replaced by a pentode whose control and suppressor grids are each connected to some of the lines 34. Units 46 comprise normally conducting grid-controlled amplifying valves which produce positive pulses on lines such as 50, connected to their anodes, when emitter pulses are received. Two units 55 are also provided which are similar to the half-cycle control unit 100 except that only one of the trigger valves is connected to a cathode follower and output line (23 or 84). The line 23 is switched to high potential by the pulse on the associated line 34b and is switched back by the pulse on line 34 of emitter unit 30(10). Registering and halving the multiplier. Each of the two denominations of the multiplier register 41, Figs. 1 and 7, comprises four trigger stages A, B connected through double triodes E2, E4, E8 so as to form a four-denomination binary counter. The multiplier digit, e.g. 9, is entered by applying a negative voltage to one or more selected lines 19 (1 and 8), e.g. by means of key or relay contacts, thus lowering grid potentials of the corresponding valves A (which are normally conducting) and switching over the triggers (1 and 8). The grids of the lower triodes of the pairs E2, E4, E8 are connected to a point 61 which is normally at a higher potential than point 60 connected to the upper triodes since valve A of a trigger circuit N is normally conducting. Halving is effected by negative pulses over lines 12 from emitter units 30(2) to (5). Thus if " 9 " has been entered, the pulse on line 12(8) will switch back trigger stage 8 and a positive pulse will be sent from the anode of valve B to the grid of lower triode E8 which will then conduct, the resultant decrease in anode voltage switching over trigger stage 4. The pulse on line 12(1) will switch back stage 1 and, if there is a lower denomination, a negative pulse will be sent from the anode of valve A over line 72 to switch over a carry trigger circuit P, thus raising the control grid potential of a valve F1. Subsequently, a pulse over line 66 from emitter unit 30(9) will switch over trigger N so that the upper triodes E2, E4, E8 are operable. Five positive pulses from units 30(13) to (17) are sent over line 24 to the suppressor grid of carry valve F1 which will then conduct and supply five negative anode pulses over line 152 to trigger stage 1 of the next lower denomination, these pulses switching over the higher stages through connections such as that from the anode of stage 1 valve B to the grid of the upper triode E2, whose anode is connected to stage 2. Trigger P is returned to normal by a pulse over line 20 from unit 30(18) and trigger N by a pulse from unit 30(1) over line 65. Odd/even detector. The anode of valve A of stage 1 of the multiplier units denomination, Fig. 7, is connected to the control grid of pentode F2 whose potential will thus be high if valve A is not conducting (indicating an odd multiplier) so that the pentode will conduct when a positive pulse from unit 30(1) over line 77 is applied to its suppressor grid, and will apply a pulse to trigger circuit Q to render valve B conductive and raise the potential of line 47. Registering and doubling the multiplicand. Fig. 8 shows one denomination of the multiplicand register 42 comprising four cascadeconnected trigger stages A, B, stage 1 being connected to stage 2 through an isolating double triode D and line 7. The multiplicand digit is entered on lines 11 connected to the normallyconducting valves A. Doubling is effected by the emitter pulses over lines 12, the switching to normal of stage 8 sending a positive pulse over line 6 to the control grid of pentode G1 which then conducts, since line 23 is at high potential, and switches over carry trigger circuit C. If the denomination is decimal, since the registered value after doubling may be greater than ten, an additional six is added by three positive pulses over line 17 from units 30(6) to (8) to the right-hand triode D. If, after this, no carry is registered, valve B of trigger C will be cut off and the control grid of pentode G2 will be at high potential, so that five positive pulses from units 30(13) to (17) over line 24 will produce negative anode pulses which are sent over line 7 to stage 2 to add a correcting value of ten. Line 23 is then at low potential so that trigger C is isolated. Trigger C, if actuated, is switched back by the emitter pulse over line 20 and then produces a carry pulse over line 21 which is sent to stage 1 of the next denomination (line 21a, Fig. 8). For the duodecimal pence denomination, four and twelve are added, instead of six and ten, by an emitter pulse over line 34a, Fig. 1, to stage 4, and three pulses over line 18 to pentode G2 (which is connected to stage 4 instead of 2) respectively. The 10 shillings denomination comprises a single registering trigger stage and carry trigger. If a trigger stage is switched over (valve B conducting) a corresponding line 48 is at high potential. Product counter; transmitting the product components from the multiplicand register. The counter 43, shown diagrammatically in Fig. 11, comprises registering triggering stages 1, 2, 4, 8 and carry circuits C connected as in the multiplicand register 42, Figs. 1 and 8, pentodes G3, G4 and isolating triodes R, S replacing pentodes G2, Gland double triodes D respectively. The multiplicand values are entered over lines 51 connected between stages 1 and the anodes of gate valves 44, Fig. 1, which conduct when positive pulses are recei
GB805449A 1949-03-24 1949-03-24 Improvements in and relating to calculating apparatus Expired GB674952A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
NL666611639A NL152498B (en) 1949-03-24 CHAIN STOPPER.
NL80783D NL80783C (en) 1949-03-24
GB805449A GB674952A (en) 1949-03-24 1949-03-24 Improvements in and relating to calculating apparatus
US147441A US2745599A (en) 1949-03-24 1950-03-03 Electronic multiplier
FR1032554D FR1032554A (en) 1949-03-24 1950-03-22 Electronic device to multiply
US202917A US2690507A (en) 1949-03-24 1950-12-27 Electronic multiplier
US202916A US2623115A (en) 1949-03-24 1950-12-27 Electronic multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB805449A GB674952A (en) 1949-03-24 1949-03-24 Improvements in and relating to calculating apparatus

Publications (1)

Publication Number Publication Date
GB674952A true GB674952A (en) 1952-07-02

Family

ID=9844904

Family Applications (1)

Application Number Title Priority Date Filing Date
GB805449A Expired GB674952A (en) 1949-03-24 1949-03-24 Improvements in and relating to calculating apparatus

Country Status (1)

Country Link
GB (1) GB674952A (en)

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