GB2598119A

GB2598119A - Impedance to voltage converter circuit and system for non-ideal operational amplifiers

Info

Publication number: GB2598119A
Application number: GB2012904.5A
Authority: GB
Inventors: Gomez Saiz Alberto; Rovere Giovanni; Awqati Faisal
Original assignee: Crypto Quantique Ltd
Current assignee: Crypto Quantique Ltd
Priority date: 2020-08-18
Filing date: 2020-08-18
Publication date: 2022-02-23
Also published as: WO2022038348A1; GB202012904D0

Abstract

An impedance to voltage converter circuit 300, operable in an offset storage mode and a conversion mode, comprises a first operational amplifier (op-amp) 310 having first and second inputs and a first output. A capacitor 306 is connected between the first input and a first terminal 316. A second terminal 326, configured to be held at a reference voltage V2, is connected to the second input. A first feedback loop is connectable between the output and a junction 328 between the capacitor and first input, and a second feedback loop, including an impedance 312, is connectable between the output and a junction 356 between the first terminal and the capacitor. In the offset storage mode, a junction 340 between the first terminal and capacitor is configured to be held at a first voltage V1, and the first feedback loop is connected to store the voltage offset of the op-amp in the capacitor. In the conversion mode, where current INP to be converted is received at the first terminal, the second feedback loop is connected such that the voltage between the first terminal and capacitor is the negative offset voltage to compensate the voltage offset of the op-amp. Further arrangements include a differential impedance to voltage converter (Fig.3B), and systems including the converter and a controller (Fig.10). The circuit may be used to compensate for non-ideal op-amp characteristics.

Description

Impedance to voltage converter circuit and system for non-ideal operational amplifiers

TECHNICAL FIELD

[0001] The present invention relates generally to impedance to voltage conversion. 5 BACKGROUND [0002] An operational amplifier arranged in a circuit as a transimpedance amplifier facilitates the measurement of the impedance of an input. Figure 1A illustrates a known transimpedance amplifier 100 having a single input Vp, which is connected to the inverting input of the operational amplifier, and a single output VouT. The non-inverting input of the operational amplifier is connected to a reference voltage, such as ground. There is a feedback loop from the output of the operational amplifier to the non-inverting input which has a resistance Rf 106. The operational amplifier 110 is an ideal operational amplifier which therefore has infinite open loop gain, infinite input impedance such that no current flows into either input terminal, zero output impedance, infinite bandwidth and zero input offset voltage. Due to the infinite input impedance, the current I, all flows through resistor R1 and so the voltage V"t = I,. Thus, the output of the transimpedance amplifier 110 can be used to calculate the input current 1 and consequently the impedance of the input. However, it does not produce an output based on the difference between the impedance of two inputs, as the transimpedance amplifier only receives one input. [0003] An operational amplifier can be arranged in a circuit as a differential amplifier which receives two inputs. Figure 1B illustrates a typical differential transimpedance amplifier circuit 150. This circuit amplifies the difference between two input voltages. The operational amplifier 160 is an ideal operational amplifier, as explained above in relation to Figure 1A. The first input to the circuit has current imp and voltage Vmp 152 and is connected to the non-inverting input of the operational amplifier 160. The second input to the circuit has current limy and voltage VffiN 154 and is connected to the inverting input of the operational amplifier 160. The first and second outputs of the operational amplifier 160 have voltages VouTp 162 and VouTN 164 respectively. The first and second outputs of the operational amplifier 160 are fed back to the inverting input via resistors R1 156 and R2 158 respectively. The following equation applies to the differential transimpedance amplifier circuit 150 when R = R1=R2.

Vou p = liupR and Vow N = R VOUTP VOUTN = (11NP FINN)R [0004] The above equation illustrates the purpose of the differential transimpedance amplifier circuit 150 of Figure 1B, which is to amplify, using R, the difference between the input currents to produce a differential output voltage. However, as shown in the above equation, the differential output voltage depends on the input differential current but not on the input differential voltage. Hence, it is not suitable to measure the input differential impedance, as this requires the output to be based on the input differential voltage. This is because the differential impedance of the input Z,",,. is based on the input differential voltage, as shown in the following equation.

VINP -VANN

Imp -'INN [0005] It is an object of embodiments of the invention to at least mitigate one or more of the problems of the prior art.

SUM MARY

[0006] Given a device under test (DUT), one may seek to measure the impedance of the DUT. To do this, it is required to convert the impedance of the DUT into a voltage suitable for further processing or digitalization. One could use a transimpedance amplifier as described above in relation to Figure 1A with being the output current from the DUT and Vp being the known voltage applied across the DUT to generate the output current. If the operational amplifier was ideal, as described above, the output current of the DUT would then allow the DUT impedance to be calculated using the voltage output by the operational amplifier, the known applied voltage and known equations such as ohm's law. However, as actual operational amplifiers are non-ideal operational amplifiers, the operational amplifier has its own input offset voltage which may be unknown. The voltage applied across the DUT is therefore not the known voltage but is dependent on and changed by the input offset voltage, causing a voltage biasing error in the input of the circuit of Figure 1A. This causes an error in the current that is output from the DUT and input into the circuit of Figure 1A because it is no longer uniquely proportional to the DUT impedance and the known voltage Vp but also depends on the input offset voltage. This causes errors in the output voltage of the operational amplifier and consequent calculation of the impedance of the DUT because the applied voltage needed is unknown.

[0007] A known approach is to use a complex calibration procedure on the transimpedance amplifier of Figure 1A to calculate the input offset voltage of the operational amplifier, which can then be compensated for either by adjusting the known voltage or using it to calculate impedance based on the biased output. Such a procedure may affect measurement results and requires additional circuitry or memory resources.

[0008] To overcome this problem, the inventors have invented circuitry that includes a capacitor before the inverting input of an operational amplifier to provide offset cancellation for the biasing voltage by storing the input offset voltage of the amplifier so that the voltage across the DUT is not affected by the input offset voltage but is instead uniquely proportional to the ZIND11, = DUT impedance and the known voltage. Thus, the operational amplifier can be preceded by a capacitor to provide input offset storage which enables control of the voltage bias of the DUT. A further explanation of how the capacitor provides input offset storage is provided below in relation to Figures 3A, 3B, 4A and 4B. The capacitor therefore reduces or, in some circumstances, removes the effect of the input offset voltage of the operational amplifiers on the output of the circuit, consequently removing the error caused by such an effect. This means that when a known voltage is applied across the DUT, the current output by the DUT is uniquely proportional to the DUT impedance and the known voltage and so the correct and precise DUT impedance can be calculated by converting the current output by the OUT into a voltage. Thus, the output of the operational amplifier accurately provides an amplification of the current output from the DUT and consequently accurately provides the DUT impedance. Thus, the circuit therefore provides accurate impedance to voltage conversion, and in some examples amplification, without requiring additional circuitry, memory or complex calibration procedures. [0009] Moreover, the circuit enables the conversion of an impedance to a large voltage which can be accurately processed and digitalized in integrated circuits. In particular, the inclusion of the capacitor, which may be referred to as input offset storage, provides more precise and accurate outputs so that the impedance of each OUT can be precisely and accurately measured.

[0010] According to an aspect of the invention, there is provided an impedance to voltage converter circuit operable in an offset storage mode and an impedance to voltage conversion mode, the circuit comprising a first operational amplifier comprising a first input, a second input and a first output, a second terminal electrically connected to the second input, the second terminal configured to be held at a reference voltage and a first capacitor between a first terminal and the first input. The circuit further comprises a first feedback loop connectable between the first output and a first junction between the first capacitor and the first input and a second feedback loop connectable between the first output and a second junction between the first capacitor and the first terminal, the second feedback loop comprising a first impedance. In the offset storage mode, a third junction between the first capacitor and the first terminal is configured to be held at a first voltage, and the first feedback loop is connected such that the voltage offset of the first operational amplifier is stored across the first capacitor. In the impedance to voltage conversion mode, the first terminal is configured to receive a first input current to be converted, and the second feedback loop is connected such that the voltage between the first capacitor and the first terminal is the negative voltage offset which compensates the voltage offset of the first operational amplifier.

[0011] Throughout the application, impedance to voltage conversion mode may be referred to as conversion mode and offset storage mode may be referred to as storage mode.

[0012] The circuit may further comprise a first device under test (DUT) electrically connected to the first terminal in impedance to voltage conversion mode, wherein the first voltage may be applied across the first DUT such that the first input current from the first DUT is received at the first terminal.

[0013] The first voltage may be selected based on the desired bias of the first DUT.

[0014] In the offset storage mode, the second feedback loop may be disconnected and, in the impedance to voltage conversion mode, the first feedback loop may be disconnected.

[0015] The first input may be an inverting input and the second input may be a non-inverting input.

[0016] The first input current may be a nanoampere scale current.

[0017] Given two devices under test (DUTs), one may seek to measure the difference in impedance of each DUT. To do this, it is required to convert the difference in impedance of each DUT into a voltage suitable for further processing or digitalization. In order to convert the difference in impedance between two inputs into a voltage, one naive approach would be to apply a first voltage across both DUTs and duplicate the transimpedance amplifier of Figure 1A so that a first current generated by the first OUT can be input into the inverting input of one of the operational amplifiers and a second input current generated by the second OUT can be input into the inverting input of another operational amplifier. The reference voltage (shown as ground in figure 1A) connected to the non-inverting input of the operational amplifier 110 of Figure 1A can be connected to the non-inverting input of both operational amplifiers to ensure the DUT impedances at the inverting inputs are subjected to the same voltage of the non-inverting input. This configuration will be referred to as the dual transimpedance amplifier configuration. The outputs of the operational amplifiers would then theoretically provide a conversion into voltage, and possible amplification, of the difference in current between the first and second currents and consequently provide the difference in impedance.

[0018] However, as actual operational amplifiers are non-ideal operational amplifiers, each has its own input offset voltage. The first voltage is applied across each DUT but depends on, and is changed by, the input offset voltage. Therefore, the voltage applied across each OUT will differ and consequently the input current generated from each DUT, is no longer uniquely proportional to the DUT impedance but also to the input offset voltage. Therefore, the output voltage of each operational amplifier, which is based on the input current, is not uniquely proportional to the DUT impedance and the first voltage and therefore the differential output voltage cannot be used to measure the difference in impedance of each DUT. Moreover, as different voltages are applied across each DUT, the DUTs do not have the same operating conditions and therefore their outputs are incomparable. Consequently, the difference in impedance of each OUT cannot be calculated correctly when using the dual transimpedance amplifier configuration.

[0019] To overcome this problem, the inventors have invented circuitry that includes a capacitor before the inverting input of an operational amplifier that provides offset cancellation for the first voltage of the DUT by storing the amplifier input offset voltage. This enables control of the applied voltage of each DUT. Thus, both operational amplifiers can be preceded by capacitors to provide input offset storage. A further explanation of how these capacitors provide input offset storage is provided below in relation to Figures 3A, 3B, 4A and 4B. The capacitors therefore reduce or, in some circumstances, remove the effect of the input offset voltages of the operational amplifiers on the output of the circuit, consequently removing the error caused by such an effect. Thus, the outputs of the operational amplifiers accurately provide an amplification of the difference in current between the first and second currents and consequently accurately provide the difference in impedance.

[0020] The circuits described herein therefore enable accurate control of an applied voltage, which enables the measurement of differential impedances. Moreover, the circuits enable the conversion of small differential impedances to large voltages which can be accurately processed and digitalized in integrated circuits. In particular, the inclusion of the first and second capacitors, which may be referred to as input offset storage, provides more precise and accurate outputs which are based on the difference between the input currents such that the difference in impedance of each DUT can be precisely and accurately measured.

[0021] According to another aspect of the invention, there is provided a differential impedance to voltage converter circuit operable in an offset storage mode and an impedance to voltage conversion mode, the circuit comprising any impedance to voltage converter circuit described above, a second operational amplifier comprising a third input, a fourth input and a second output, wherein the second terminal is electrically connected to the third input and a second capacitor between a third terminal and the fourth input. The circuit further comprises a third feedback loop connectable between the second output and a fourth junction between the second capacitor and the fourth input and a fourth feedback loop connectable between the second output and a fifth junction between the second capacitor and the third terminal, the fourth feedback loop comprising a second impedance. In the offset storage mode, a sixth junction between the second capacitor and the third terminal is configured to be held at a first voltage and the third feedback loop is connected such that the voltage offset of the second operational amplifier is stored across the second capacitor. In the impedance to voltage conversion mode, the third terminal is configured to receive a second input current to be converted, and the fourth feedback loop is connected such that the voltage between the second capacitor and the third terminal is the negative voltage offset which compensates the voltage offset of the second operational amplifier.

[0022] The circuit may further comprise a second DUT electrically connected to the third terminal in impedance to voltage conversion mode, wherein the first voltage may be applied across the second DUT such that the second input current from the first DUT is received at the third terminal.

[0023] The first voltage may be selected based on the desired bias of the first and second DUTs.

[0024] In the offset storage mode, the fourth feedback loop may be disconnected and, in the impedance to voltage conversion mode, the third feedback loop may be disconnected. [0025] The first impedance and/or second impedance may comprise a resistance. The first impedance and/or second impedance may comprise a capacitance.

[0026] The offset storage mode may occur before the impedance to voltage conversion mode.

The offset storage mode may occur directly before the impedance to voltage conversion mode such that the voltage across the capacitor in the impedance to voltage conversion mode may be the voltage offset of the operational amplifier, which may be set during offset storage mode. The offset storage mode may be directly followed by a transition mode which may be directly followed by the impedance to voltage conversion mode. The transition mode may be between the offset storage mode and impedance to voltage conversion mode where only some of the closed switches have been opened and/or only some of the open switches have been closed after the offset storage mode.

[0027] The first input and the fourth input may be inverting inputs and the second input and third input may be non-inverting inputs.

[0028] The fourth input may be an inverting input and the third input may be a non-inverting input.

[0029] The second input current may be a nanoampere scale current.

[0030] The difference in current between the first input current and second input current may be a sub-picoamp current.

[0031] The voltage offset of the first operational amplifier may be different to the voltage offset of the second operational amplifier.

[0032] The size of the voltage offset of each operational amplifier may be dependent on the manufacturing process. The input offset voltage may be between 1 and 10mV.

[0033] The first and/or second DUT may be an electronic component. The first and/or second DUT may have a quantum tunneling barrier. The first and/or second DUT may be a transistor or a capacitor. The first and/or second DUT may be a metal oxide semiconductor field effect transistor (MOSFET). Each input terminals of the circuit may be connected to a gate terminal of a MOSFET.

[0034] In impedance to voltage conversion mode, the first output may be held at a first output voltage and the second output may be held at a second output voltage and the difference between the first output voltage and the second output voltage may be dependent on the difference between the first input current and the second input current.

[0035] The first voltage may be substantially the same as the reference voltage.

[0036] The first voltage and/or reference voltage may be predetermined voltages. In an example, the first voltage may be approximately 1.2 Volts. In an example, the reference voltage may be approximately 1 Volt.

[0037] The first impedance may comprise a third capacitor and the second impedance may comprise a fourth capacitor, and the first voltage may be different to the initial output voltage, which is determined by the reference voltage.

[0038] In the impedance to voltage conversion mode, the circuit may be configured to comprise a first connection from the second output to a seventh junction between the first terminal and the first input, the first connection comprising a third impedance, and a second connection from the first output to an eighth junction between the third terminal and the fourth input, the second connection comprising a fourth impedance.

[0039] As explained further below, these connections enable the circuit to output voltages which amplify the differential impedance provided by the inputs. However, if the input offset voltages of the operational amplifiers are large, the connections will also amplify the error due to the offset voltages. By combining the capacitors for storing the input offset voltage and the connections for amplifying the differential impedance, the circuit is able to amplify the exact difference between the inputs without amplifying an error. Thus, this circuit provides an accurate output voltage which amplifies the differential impedance such that it can easily be processed to obtain an accurate measurement of the differential impedance of the DUTs.

[0040] The increase in the differential impedance to voltage gain is provided by increasing the differential mode of the input currents and decreasing the common mode of the input currents. When receiving input currents where the difference in magnitude between the currents is smaller than the magnitude of the input currents, the outputs of the operational amplifiers would not be large enough to effectively provide the difference between the input currents. This is because the outputs of the dual transimpedance amplifier would be a function of the difference in current between the inputs (i.e. the differential mode) and the amount of current that is the same in both inputs (i.e. the common mode) and both the differential mode and the common mode are subject to the same amplification. Thus, for input currents with only a small difference in magnitude between them, the common mode of the input currents would be substantially larger than the differential mode and consequently the amplifier outputs would saturate.

[0041] Increasing the differential impedance to voltage gain and decreasing the common mode of the input currents is advantageous over normal configurations where gain of the common mode is equal to gain of the differential mode because it enables the conversion of the difference between the input impedances into larger voltages so that they can be accurately processed and digitalized in integrated circuits. Thus, even small differences between two input currents can be measured. This makes it easier to measure small differences in impedance. In fact, the circuit of the present invention can be used to measure differential impedances generating sub-picoamp differential currents in integrated circuits. The circuit of the present invention therefore overcomes a problem of setting a near-zero differential voltage in the DUT. [0042] The inclusion of the two connections, also referred to as bootstrapping, increases the achievable differential impedance to voltage gain beyond that achievable by the typical architectures and components. Additionally, for the same differential impedance to voltage gain achieved by typical architectures and components, the bootstrapping technique results in a lower added noise.

[0043] According to another aspect of the invention, a system is provided for converting impedance to voltage. The system comprises any impedance to voltage converter circuit described above. The system further comprises a controller configured to operate the circuit in the offset storage mode and the impedance to voltage conversion mode.

[0044] According to another aspect of the invention, a system is provided for converting differential impedance to voltage. The system comprises any differential impedance to voltage converter circuit described above. The system further comprises a controller configured to operate the circuit in the offset storage mode and the impedance to voltage conversion mode. [0045] The system may further comprise a filter to filter the first and second outputs. The filter may reduce the noise of the signals output from the circuit.

[0046] The system may further comprise a switch capacitor integrator to reduce the noise of the first and second outputs.

[0047] Many modifications and other embodiments of the inventions set out herein will come to mind to a person skilled in the art to which these inventions pertain in light of the teachings presented herein. Therefore, it will be understood that the disclosure herein is not to be limited to the specific embodiments disclosed herein. Moreover, although the description provided herein provides example embodiments in the context of certain combinations of elements, steps and/or functions may be provided by alternative embodiments without departing from the scope of the invention.

BRIEF INTRODUCTION OF THE DRAWINGS

[0048] Illustrative embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1A illustrates a known transimpedance amplifier circuit; Figure 1B illustrates a known differential transimpedance amplifier circuit; Figures 2A and 2B illustrate example circuits of devices under test; Figure 3A shows an impedance to voltage converter circuit having input offset storage; Figure 3B shows a differential impedance to voltage converter circuit having input offset storage; Figure 4A shows the differential impedance to voltage converter circuit of Figure 3B in storage mode; Figure 4B shows the differential impedance to voltage converter circuit of Figure 38 in conversion mode; Figure 5 shows an integration configuration of the differential impedance to voltage converter circuit of Figure 3B; Figure 6 shows a differential impedance to voltage converter circuit having input offset storage and bootstrapping; Figures 7A and 7B show the differential mode of the differential impedance to voltage converter circuit of Figure 6; Figures 8A and 8B show the common mode of the differential impedance to voltage converter circuit of Figure 6; Figure 9 shows a timing diagram of the switches of the differential impedance to voltage converter circuit of Figure 6; Figure 10 shows a system for converting differential impedance to voltage; Figure 11 shows an array comprising a plurality of cells, each cell comprising devices under test.

[0049] Throughout the description and the drawings, like reference numerals refer to like parts.

DETAILED DESCRIPTION

[0050] Examples provide systems and circuits suitable for converting impedance to a voltage suitable for further processing or digitization.

[0051] One may seek to compare the output current of two devices under test (DUTs). For example, one may seek to compare the impedance of two DUTs by applying a voltage across each DUT and using the output current to calculate the differential impedance of the DUTs.

Figure 2A illustrates a first device under test (DUTp) 302 and a second device under test (DUTN) 304 according to an example. The first and/or second DUT may be any device, for example, an electronic component. The first and/or second DUT may be a device with a quantum tunnelling barrier, such as a capacitor or transistor. The current output of DUT p 302 is 'my 202 and the current output of DUTN 304 is /INN 204. As it is desirable to compare the currents /iNp 202 and IINN 204, DUTN 304 and DUT p 302 share a common ground 206. However, they could also share other potentials.

[0052] Figure 2B illustrates an example of DUTN and DUT. Figure 2B shows a cell 250 according to an example, in which both DUTN 304 and DUTp 302 are transistors 354 and 352 respectively of the cell 250. The gate terminal 180 of each of the transistors 352, 354 is to be connected to the differential impedance to voltage converter circuit. Source and drain terminals 182, 184 of the transistors 352, 354 are held at the same potential. The gate terminal of each transistor 352, 354 is separated from the source and drain terminals 182, 184 by an oxide layer having a small thickness such that the oxide layer acts as a quantum tunnelling barrier.

[0053] In use, a potential difference exists between the gate terminal 180 of the transistors 352, 354 and the source terminal 182 (and drain terminal 184) of the transistors 352, 354. The potential difference across the insulating layer of each of the transistors enables quantum tunnelling through the quantum tunnelling barrier. Due to inherent differences in the transistors introduced during manufacture, the first quantum tunnelling barrier uniquely characterises the first transistor 352 and the second quantum tunnelling barrier uniquely characterises the second transistor 354. The potential difference may be below a threshold voltage for which current would classically be able to pass through either the first quantum tunnelling barrier or the second quantum tunnelling barrier. Therefore, whilst quantum tunnelling current may flow through the quantum tunnelling barriers of the first and second transistor 352, 354, classical current may not flow.

[0054] Due to the inherent differences between the oxide layers of the first transistor 352 and the second transistor 354, when the same potential difference is applied across the barriers of both transistors, a first quantum tunnelling current imp through the first transistor 352 and at terminal 316 is inherently different to a second quantum tunnelling current 'INN through the second transistor 354 and at terminal 318. The quantum tunnelling current flowing through each of the quantum tunnelling barriers is a unique identifier of each transistor 352, 354 (and therefore can be used to uniquely identify a device comprising the transistors). Tunnelling currents imp and /INN measured from terminals 316 and 318 respectively are therefore characteristic of the transistors 352 and 354 and so are characteristic of the particular cell 250. [0055] The difference between these tunnelling currents is very small. VVhen connected, the differential impedance to voltage converter circuit receives 'I NPand 'INN and amplifies the difference whilst converting them into voltage Vomm and VOUTP * The output voltages VOUTN and VOUTP are formed of a common mode component and a differential component. It is the differential component of the output voltages that can then be used to measure the quantum tunnelling current of each transistor 352, 354. Thus, the differential impedance to voltage converter circuit enables effective measurement of the quantum tunnelling current through the oxide layer of the transistors 352, 354 to establish the characteristic of the cell 250 and consequently the unique identity of the device containing the two transistors 352, 354.

[0056] Figure 3A shows an impedance to voltage converter circuit 300 according to an example. The circuit 300 comprises a first operational amplifier 310 with an inverting input, a non-inverting input and an output. The first operational amplifier 310 may have non-ideal characteristics. The first amplifier 310 is a voltage amplifier and has a large input impedance and low output impedance.

[0057] The output of the first operational amplifier 310 is connected to an output terminal 312 which has a voltage VouTp. The non-inverting input of the first operational amplifier 310 is connected to a terminal 326 which is held at a reference voltage Vy.

[0058] The circuit has a first terminal 316 configured to receive current //No 202 from DUTp 302. In some examples, circuit 300 includes DUTp 302 and the input to the circuit is the applied biasing voltage V1 across DUT p 302 which generates current 11Np 202. In other examples, circuit may not include DUTp 302, for example, DUTp 302 may be detachable. The terminal 316 is connected to the inverting input of the first operational amplifier 310 via a capacitor C1306. The capacitor C1 306 provides input offset storage for the first operational amplifier 310. The concept of input offset storage is described below.

[0059] The circuit 300 comprises a junction 340 between the input terminal 316 and the capacitor Cj. 306 which is connected to a terminal 324 having a voltage V1. The circuit 300 comprises a switch 51 402 between the junction 340 and the terminal 316. In some examples, the circuit 300 may comprise a switch So 366 between the input terminal 316 and the junction 340. The voltage applied across DUT p 302, when switches So 366 and S1 402 are closed, is V1 because DUTp 302 is connected between terminal 324, which is held at V1, and ground 206. Thus, the voltage V1 is selected depending on the desired bias of the DUT 302. The voltage V1 may therefore be referred to as the DUT bias voltage. The voltage Vy at terminal 326 may be the same, or substantially the same, as the voltage V1. In other examples, the voltage V, may be different to the voltage V1.

[0060] The circuit 300 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 328 between the capacitor C, 306 and the inverting input of the first operational amplifier 310, the feedback loop comprising a switch S2 406. The circuit 300 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 356 between the input terminal 316 and the capacitor Cj. 306. This feedback loop has impedance z1 312 and a switch 53 408. The impedance 4 is used to generate the current to voltage gain of the circuit in conversion mode.

[0061] Regarding the operation of circuit 300, voltage V1 324 is applied across DUTp which generates input current Up. The input current imp to the operational amplifier 310 is generated by DUTp based on the impedance of the DUT. The output voltage input current VOL/fl) is based on the input current input current Imp and consequently based on the impedance of the DUT. Thus, the circuit 300 enables accurate conversion, and in some examples amplification, from OUT impedance to voltage.

[0062] As mentioned previously, ideal operational amplifiers are known to have infinite open loop gain, infinite input impedance such that no current flows into either input terminal, zero output impedance, infinite bandwidth and zero input offset voltage. However operational amplifiers 310 is not ideal. One of the non-ideal characteristics of operational amplifiers is input offset voltage which is combined with voltage V, 324 to provide a voltage across DUTI, 302. The voltage applied across the DUT is therefore not the known voltage but is dependent on and changed by the input offset voltage, causing a voltage biasing error. This causes an error in the current that is output from the DUT because it is no longer uniquely proportional to the DUT impedances and voltage V, but also depends on the input offset voltage. This causes errors in the output voltage of the operational amplifier and consequent calculation of the impedance of the DUT because the applied voltage needed is unknown. As explained below, the capacitor C, 306 stores the input offset voltage to prevent such errors occurring.

[0063] In an example, the impedance to voltage converter circuit is first configured to operate in storage mode and is subsequently configured to operate in conversion mode. The circuit may be operated in a transition mode between storage mode and conversion mode.

[0064] The circuit 300 is operable in a storage mode and a conversion mode. When switches S, and S, are closed and switches So and 53 are open, the circuit 300 is operating in storage mode. When switches Sj. and S2 are open and switches So and 53 are closed, the circuit 300 is operating in conversion mode.

[0065] In some examples, DUTp 302 is only connected as illustrated in Figure 3A when the circuit 300 is operating in impedance to voltage conversion mode. In other examples, DUT p 302 is connected in all modes and circuit 300 further comprises switch so 366 which is open in storage mode and transition mode and is closed in impedance to voltage conversion mode. This switch may be used to control the provision of the input current imp 202 that has been provided by DUT,, 302 so that it is only provided in impedance to voltage conversion mode i.e. when it needs to be measured.

[0066] In the storage mode, there is a junction 340 between the input terminal 316 and the capacitor C, 306 which is connected to terminal 324 which is held at voltage V,. There is also a feedback loop between the output of the first operational amplifier 310 and a junction 328 between the capacitor C, 306 and the inverting input of the first operational amplifier 310 which permits current to flow between the output and the capacitor 306. This feedback loop enables the input offset voltage of the operational amplifier to be stored across the capacitor C, 306. In the storage mode, the input offset voltage of the first operational amplifier 310, VoFFsET,43, will be stored across the capacitor C, 306. This is because Vc, = V_ -V, = V2 -V OFFSETA1-V1= -VOFFSETA1 when V2 't.'" V1. The same equations apply to the upper half of circuit 350 of Figure 3B and corresponding equations apply to the lower half of circuit 350 of Figure 3B for operational amplifier 320 and capacitor C2. In storage mode, the feedback loop between the output of the first operational amplifier 310 and a junction 356 between the input terminal 316 and the capacitor C, 306 which has an impedance Z, 352 is disconnected and consequently does not allow current flow.

[0067] There may be a first transition mode between the storage mode and conversion mode.

As the switches are opened and closed when transitioning from storage mode to conversion mode, switch S, may be opened before switches So and 53 have closed. The circuit 300 is operating in the first transition mode when the switch S, is closed and switches So, S2 and 53 are open. In this mode, the charge of the capacitor C, 306 remains constant because there is no path to ground from V_ for C, to discharge. The circuit may operate in a second transition mode between the storage mode and conversion mode, after the first transition mode. In the second transition mode, the switch 53 is closed and switches So, S, and S, are open. In this mode, the charge of the capacitor C, 306 remains constant because there is no path to ground from V_ for C, to discharge. In this mode, V+ = V INP + V C1= VINP ± (V2 -VOFFSETA1-Vd. Also, = V2 -VOFFSET and, because there is no current flowing into 4, Vmp = VOUTP* Using the above equations, the known operational amplifier equation of VouTp = A(V+ -V_) can be rewritten as VINP = A((VINP ± (V2 -VOFFSETA1-V1)) -(V2 -VOFFSET)) = A(VINP V1).

[0068] Therefore V, = Vti1p(1 L) and, as A, » 1,V1 Vmp. As Vim, is the bias voltage for DUTp,V1 determines the voltage applied to DUTp. The same equations apply to the upper half of circuit 350 of Figure 3B and corresponding equations apply to the lower half of circuit 350 of Figure 3B for operational amplifier 320 and capacitor C2.

[0069] In the conversion mode, there is a feedback loop between the output of the first operational amplifier 310 and a junction 356 between the input terminal 316 and the capacitor C, 306. This feedback loop has an impedance Z, 352. In conversion mode, the feedback loop between the output of the first operational amplifier 310 and a junction 328 between the capacitor C, 306 and the inverting input of the first operational amplifier 310 is disconnected and consequently does not allow current flow. In conversion mode, the first terminal 316 receives current imp 202 from DUTp 302 this current is converted such that the voltage VouTp at the output terminal 312 is based on the input current /iNp. In the conversion mode, the voltage at terminal 316 is the negative of the offset voltage of the first operational amplifier 310, -VOFFSETA1, because the capacitor C, 306 is inverted and, due to previously being configured in the storage mode, the capacitor is storing the offset voltage VoifFsETAl. This voltage -VOFFSETA1 compensates the offset of the first operational amplifier 310 VOFFSETAl* The output voltage in this mode VouTp = V INP * -INP-Z 1= V, + /mpZ, because V, Vmp. The same equations apply to the upper half of circuit 350 of Figure 33 and corresponding equations apply to the lower half of circuit 350 of Figure 3B for operational amplifier 320 and capacitor Cy. [0070] Figure 33 shows a differential impedance to voltage converter circuit 350 according to an example. The circuit 350 comprises a first operational amplifier 310 and a second operational amplifier 320, each with an inverting input, a non-inverting input and an output. The first and second operational amplifiers 310 and 320 may have non-ideal characteristics. The first and second operational amplifiers 310 and 320 are voltage amplifiers and have a large input impedance and low output impedance.

[0071] The output of the first operational amplifier 310 is connected to an output terminal 312 which has a voltage VouTp. The output of the second operational amplifier 320 is connected to an output terminal 314 which has a voltage VouTN. The non-inverting input of both first and second operational amplifiers 310, 320 is connected to a terminal 326 which is held at a reference voltage Vy, which may be the same as V,.

[0072] The circuit has two terminals 316, 318 to receive input current, the first terminal 316 configured to receive current iffip 202 from DUTp 302 and the second terminal 318 configured to receive current /INN 204 from DUTN 304. In some examples, circuit 350 includes DUTp 302 and DUTN 304 and the input to the circuit is the applied biasing voltage V, across DUTp 302 and DUTN 304 which generate current //Np 202 and /INN 204 respectively. In other examples, the circuit 350 may not include the DUTs, for example, the DUTs may be detachable from the circuit. The terminal 316 is connected to the inverting input of the first operational amplifier 310 via a capacitor C1306. The terminal 318 is connected to the inverting input of the second operational amplifier 320 via a capacitor Cy 308. The capacitor C, 306 provides input offset storage for the first operational amplifier 310 and the capacitor Cy 308 provides input offset storage for the second operational amplifier 320. Thus, the circuit 350 has input offset storage for both operational amplifiers. The concept of input offset storage is described below in relation to the storage and conversion modes of Figures 4A and 4B respectively.

[0073] The circuit 350 comprises a junction 340 between the input terminal 316 and the capacitor C, 306 which is connected to a terminal 324 having a voltage V,. The circuit 350 comprises a switch S1 402 between the junction 340 and the terminal 316. In some examples, the circuit 350 may comprise a switch Sc, 366 between the input terminal 316 and the junction 340. The voltage across DUTp 302, when switches so 366 and S1402 are closed, is V, because DUTp 302 is connected between terminal 324, which is held at V1, and ground 206. The circuit 350 also comprises a junction 342 between the input terminal 318 and the capacitor Cy 308 which is also connected to terminal 324. The circuit 350 comprises a switch S6 404 between the junction 342 and the terminal 318. In some examples, the circuit 350 may comprise a switch.55 368 between the input terminal 318 and the junction 342. The voltage across DUTA, 304, when switches Ss 368 and S6 404 are closed, is V, because DUTA, 304 is connected between terminal 324, which is held at V1, and ground 206. Thus, the voltage V, is selected depending on the desired bias of the DUTs 302, 304. The voltage V, may therefore be referred to as the DUT bias voltage. The voltage V2 at terminal 326 may be the same, or substantially the same, as the voltage V,.

[0074] The circuit 350 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 328 between the capacitor C, 306 and the inverting input of the first operational amplifier 310, the feedback loop comprising a switch 52 406. The circuit 350 also comprises a feedback loop between the output of the second operational amplifier 320 and a junction 330 between the capacitor C2 308 and the inverting input of the second operational amplifier 320, the feedback loop comprising a switch 57 412.

[0075] The circuit 350 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 356 between the input terminal 316 and the capacitor C, 306. This feedback loop has impedance Z, 312 and a switch 53 408. There is also a feedback loop between the output of the second operational amplifier 320 and a junction 358 between the input terminal 318 and the capacitor C2 308. This feedback loop has impedance Z2 354 and a switch S8 414. The impedances Z, and Z2 are used to generate the current to voltage gain of the circuit in conversion mode.

[0076] As mentioned previously, ideal operational amplifiers are known to have infinite open loop gain, infinite input impedance such that no current flows into either input terminal, zero output impedance, infinite bandwidth and zero input offset voltage. However operational amplifiers 310, 320 are not ideal. One of the non-ideal characteristics of operational amplifiers is input offset voltage, which differs for each operational amplifier. Therefore, the first and second operational amplifiers 310 and 320 will have a different input offset voltage. Whilst there may be other non-ideal characteristics of the operational amplifiers 310, 320, these extend beyond the scope of the present application. The difference in input offset voltage will cause the voltage output to be incorrect, and thus not based on the difference between the input currents. This circuit implementation uses a mechanism for offset cancellation to achieve a small error in resistance to voltage conversion compared to typical architectures.

[0077] In detail, the operational amplifiers 310,320 have a large gain, with operational amplifier 310 having a gain of Al and operational amplifier 320 having a gain of A2. The gains Al and A2 may be the same. The gains Al and A2 may be above 60dBV. The operational amplifiers 310, 320 also have a large input impedance and low output impedance. The operational amplifier 310 may be the same as operational amplifier 320 except for characteristics caused by manufacturing defects.

[0078] In an example, the differential impedance to voltage converter circuit is first configured to operate in storage mode and is subsequently configured to operate in conversion mode. The circuit may be operated in a transition mode between storage mode and conversion mode. [0079] The circuit 350 is operable in a storage mode and a conversion mode. When switches S,, S6, S2 and 57 are closed and switches So, 55, .53 and 53 are open, the circuit 350 is operating in storage mode and the connections are as shown in the circuit 400 of Figure 4A. When switches Si, 56, 52 and 57 are open and switches 50, 55, 53 and.55 are closed, the circuit 350 is operating in conversion mode and the connections are as shown in the circuit 450 of Figure 4B. [0080] In some examples, DUTp 302 and DUTN 304 are only connected as illustrated in Figures 3B, 4A and 4B when the circuit 350 is operating in impedance to voltage conversion mode. In other examples, DUTp 302 and DUTN 304 are connected in all modes and circuit 350 further comprises switch Su 366 and switch 55 368, which are open in offset storage mode and transition mode and are closed in impedance to voltage conversion mode. These switches may be used to control the provision of the input currents low 202 and IINN 204 that have been provided by DUTp 302 and DUTN 304 respectively so that these currents are only provided in impedance to voltage conversion mode i.e. when they needs to be measured and not in storage mode. [0081] Figure 4A shows the effective circuit 400 of the circuit of Figure 3B when configured to operate in storage mode and Figure 4B shows the effective circuit 450 of the circuit of Figure 3B when configured to operate in conversion mode according to an example.

[0082] In the storage mode, as illustrated in Figure 4A, there is a junction 340 between the input terminal 316 and the capacitor C1 306 which is connected to terminal 324 which is held at voltage 171. There is also a feedback loop between the output of the first operational amplifier 310 and a junction 328 between the capacitor C1 306 and the inverting input of the first operational amplifier 310 which permits current to flow between the output and the capacitor 306. This feedback loop enables the input offset voltage of the operational amplifier to be stored across the capacitor C1 306. In the storage mode, the input offset voltage of the first operational amplifier 310, VOFFSETA1, will be stored across the capacitor C1 306. The dashed lines indicate that in storage mode the DUTs may not be electrically connected to the circuit 400, either by being detachable or due to switches S© 366 and 55 368 being open.

[0083] In the storage mode, there is also a junction 342 between the input terminal 318 and the capacitor 308 which is connected to terminal 324 which is held at voltage V1. There is also a feedback loop between the output of the second operational amplifier 320 and a junction 330 between the capacitor C2 308 and the inverting input of the second operational amplifier 320 which permits current to flow between the output and the capacitor C2 308. This feedback loop enables the voltage offset of the operational amplifier to be stored across the capacitor C2 308.

In the storage mode, the input offset voltage of second operational amplifier 320, Voyysky,12, will be stored across the capacitor C2 308.

[0084] There may be a first transition mode between the storage mode and conversion mode. As the switches are opened and closed when transitioning from storage mode to conversion mode, switches S2 and 57 may be opened before switches So, 55, S, and S, have closed. The circuit 350 is operating in first transition mode when the switches S, and S6 are closed and switches So, 55, S2, 57, 53 and S, are open. In this mode, the charge of the capacitors Ci 306 and C2 308 remains constant. There may also be a second transition mode between the storage mode and conversion mode, after the first transition mode. In the second transition mode, the switches 53 and S, are closed and switches S0; Si0, S, and Ss are open.

[0085] In the conversion mode, as illustrated in Figure 4B, there is a feedback loop between the output of the first operational amplifier 310 and a junction 356 between the input terminal 316 and the capacitor C, 306. This feedback loop has an impedance Zi 352. There is also a feedback loop between the output of the second operational amplifier 320 and a junction 358 between the input terminal 318 and the capacitor C2 308. This feedback loop has an impedance Z2 354. The feedback loops of Figure 4A are no longer connected due to switches 52 and 57 being open and the voltage Vi is not provided to the circuit due to switches Si and S6 being open. In conversion mode, the DUTs may be electrically connected to the circuit 450, either by being attached or due to switches S0 366 and 55 368 being closed. In conversion mode, the first terminal 316 receives current imp 202 from DUTp 302 and the second terminal 318 receives current //,"N 204 from DUTN 304 and these currents are converted such that the voltages V0.,.1.1, and VouT Ai at the output terminals 312 and 314 respectively are based on the input currents and /INN respectively. In the conversion mode, the voltage at terminal 316 is the negative of the offset voltage of the first operational amplifier 310, -VaFFSETAll because the capacitor Ci 306 is inverted and, due to previously being configured in the storage mode, the capacitor is storing the offset voltage VOFFSETA1 * This voltage -VOFFSETA1 compensates the offset of the first operational amplifier 310 V06,5,"". Moreover, the voltage at terminal 318 is the negative of the offset voltage of the second operational amplifier 320, -Vo",5g7,2, because the capacitor C2 308 is inverted and, due to previously being configured in the storage mode, the capacitor is storing the offset voltage VOFFSET A2. This voltage -VorrscrA2 compensates the offset of the second operational amplifier 320 VOFFSETA2.

[0086] Figure 5 shows a differential impedance to voltage converter circuit 500. The differential impedance to voltage converter circuit 500 is an integrating configuration of the differential impedance to voltage converter circuit 350 of Figure 3B and is the same as the circuit 350 except the impedance Zi 352 comprises a capacitor C3 512 and the impedance Z2 354 comprises a capacitor C4 514. In the integration configuration illustrated in circuit 500 of Figure 5, there is no DC path between the inverting input and output of the first operational amplifier 310 or between the inverting input and output of the second operational amplifier 320. Therefore, the DUT bias voltage V, can be different to the amplifier initial output voltage determined by Vy. Therefore, in the circuit 500 of Figure 5, the reference voltage Vy may be different to the DUT bias voltage V, due to the use of the integration configuration. By adjusting the reference voltage V, such that it is not equal to voltage 171, the dynamic range of the integration can be increased. V, and V, are limited by the voltage rating of the circuit components and the input voltage range of the operational amplifiers. Having voltage V, different to voltage Vy enables each voltage to be individually controlled without being dependent on the other. For example, it is an aim to control V, to be the optimal biasing value for the DUT. It is also an aim to control V2 to be the optimal operation input voltage of the operational amplifiers and to control 172 in order to control the desired output level of the operational amplifiers, which is based on V,. This is because the outputs of the operational amplifiers are based on the voltage V2, the current from the DUTs and the impedance of the feedback loops. For example, for the circuit 300 of Figure 3A, VouTp= V2+ Iny-pZi.

[0087] Figure 6 shows a differential impedance to voltage converter circuit 1100 according to an example. The circuit 1100 may be a differential impedance to voltage converter circuit having both input offset storage and bootstrapping.

[0088] The differential impedance to voltage converter circuit 1100 comprises a first operational amplifier 310 and a second operational amplifier 320, each with an inverting input, a non-inverting input and an output. The first and second operational amplifiers 310 and 320 may be first and second operational amplifiers 310, 320 of Figures 3 and/or 5. The output of the first operational amplifier 310 is connected to an output terminal 312 which has a voltage VouTp. The output of the second operational amplifier 320 is connected to an output terminal 314 which has a voltage V"TN. The non-inverting input of both first and second operational amplifiers 310, 320 is connected to a terminal 326 which is held at a reference voltage V2.

[0089] The circuit 1100 has two terminals 316, 318 to receive input current, the first terminal 316 configured to receive current 202 from DUT p 302 and the second terminal 318 configured to receive current 'INN 204 from DUTN 304. The terminal 316 is connected to the inverting input of the first operational amplifier 310 via a capacitor C, 306. The terminal 318 is connected to the inverting input of the second operational amplifier 320 via a capacitor C2 308. As explained in relation to Figures 4A and 4B, these capacitors provide the circuit 1100 with input offset storage for both operational amplifiers. The circuit 1100 may include the DUTs. In some examples, the circuit 1100 may not include the DUTs, for example, these may be detachable from the circuit.

[0090] The circuit 1100 comprises a junction 340 between the input terminal 316 and the capacitor C, 306 which is connected to a terminal 324 having a voltage V1, which is selected as described in relation to Figures 3A and 3B. The circuit 1100 comprises a switch S, 402 between the junction 340 and the terminal 316. In some examples, the circuit 1100 may comprise a switch So 366 between the input terminal 316 and the junction 340. The circuit 1100 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 328 between the capacitor C, 306 and the inverting input of the first operational amplifier 310, the feedback loop comprising a switch S2 406.

[0091] The circuit 1100 also comprises a junction 342 between the input terminal 318 and the capacitor C2 308 which is also connected to terminal 324 having voltage V1. The circuit 1100 comprises a switch 56404 between the junction 342 and the terminal 318. In some examples, the circuit 1100 may comprise a switch 55 368 between the input terminal 318 and the junction 342. The circuit 1100 also comprises a feedback loop between the output of the second operational amplifier 320 and a junction 330 between the capacitor C2 308 and the inverting input of the second operational amplifier 320, the feedback loop comprising a switch S7 412.

[0092] The circuit 1100 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 356 between the input terminal 316 and the capacitor 306. This feedback loop has impedance Z1 312 and a switch 53 408. There is also a feedback loop between the output of the second operational amplifier 320 and a junction 358 between the input terminal 318 and the capacitor 308. This feedback loop has impedance Z2 314 and a switch 5'8 414.

[0093] The circuit 1100 also comprises a connection from the output of the second operational amplifier 320 to a junction 628 between the terminal 316 and the inverting input of the first operational amplifier 310, the connection having impedance Z3 606 and a switch 54 1108. The circuit 1100 of Figure 6 also comprises a connection from the output of the first operational amplifier 310 to a junction 632 between the terminal 318 and the inverting input of the second operational amplifier 320, the connection having impedance Z4 608 and a switch 53 1114. These connections, a form of bootstrapping, increase the differential mode and reduce the common mode of the outputs Vamp and VouTN, as explained in relation to 7A, 7B, 8A and 8B below. In particular, the connections, having impedance Z3 and Z4, further increase the differential current to voltage gain.

[0094] The skilled person would appreciate that the junctions mentioned throughout the specification have been shown as separate junctions but that other configurations may be used. For example, in the circuit 1100 of Figure 6, the junction 628 and the junction 356 may meet at a single junction, and similarly the junction 632 and fourth junction 358 may meet at a single junction. For example, the feedback loop and connection that form the junction 628 and junction 356 may be electrically connected and form their own junction before meeting at a single junction at the inverting input to the operational amplifier 310. Similarly, the feedback loop and connection that form the junction 632 and junction 358 may be electrically connected and form their own junction before meeting at a single junction at the inverting input to the operational amplifier 320.

[0095] The circuit 1100 has the following conditions Z1 Z2 Z3 --z1 Z4 Z3 > Z1 rt A2 A1 >> 1 [0096] The output of the circuit consists of a common mode and a differential mode. The common mode is representative of the amount of current common to both inputs, i.e. the minimum of Imp and 'INN. The differential mode is representative of the difference in current between the two inputs. To explain the analysis of the circuit 1100 of Figure 6, the Figures 7A and 73 show only the extracted differential mode circuits of the circuit 1100, and Figures 8A and 88 show only the extracted common mode circuits of the circuit 1100. The extracted differential mode circuits in Figures 7A and 7B and the extracted common mode circuits of Figures 8A and 8B are simplified versions of the circuit 1100 of Figure 6 and are simply used for explaining the function of the connections, i.e. the bootstrapping, of the circuit 1100 of Figure 6. For example, these figures do not illustrate the capacitors C1 306 and Cy 308 and do not illustrate the first voltage 171 324 or the connections thereto. The circuits 750 and 850 of Figures 73 and 83 are equivalent circuits of the circuits 700 and 800 of Figures 7A and 8A respectively.

[0097] Figure 7A shows the extracted differential mode circuit 700 of circuit 1100 of Figure 6.

The differential mode of the current 'INN is i'lly/2 and the differential mode of the current imp is -imE/2, which is negative because the current in the circuit 1100 of Figure 6 is going in the opposite direction to the current of Figure 7A. The difference between these currents is therefore IDIF * The circuit 700 of Figure 7A can be simplified to the circuit 750 of Figure 7B by symmetry such that the circuit 750 of Figure 7B is equivalent to the circuit 700 of Figure 7A. The difference between VOUTP and VOUTN is VOUTDIF. The triangle 716 multiplies the input with a gain of -1 and outputs the result to Z3. This triangle 716 represents the connections between the output of each operational amplifier to the inverting input of the other operational amplifier. As mentioned above, Z, = Zy and Z3 = Z4 so the impedances can be simplified to just Z, and Z3, as illustrated in Figure 7B.

[0098] The following equations apply to the differential mode equivalent circuit 750 of Figure 78.

VOUTDIF = VINDIF VINDM = VOUTDIF VOLUME -ViNDIF = -VOW DI& Zy -1* VOUTDIF VINDIF Ai lz,VOUTDIF Z3 Z3 [0099] The amplifier gain is much larger than 1 so-0 so /z VOUTDIF and I -VOUTDIF 1 zi z, [00100] Applying Kirchhoffs law: -IDIF = IZ, it -1) = VOUTDIF ± -Z1 Z3 VOUTD1

GMDIFF

[00101] As mentioned above, Z3 > Z1 so the differential gain (GMD/FF) is larger due to the connection between the different operational amplifiers of impedance Z3. Thus, circuit 1100 of Figure 6 provides an increased differential impedance to voltage gain (GMEnFF) with respect to typical implementations.

[00102] Figure 8A shows the extracted common mode circuit 800 of circuit 1100 of Figure 6. The common mode current of the current /rivp and the current /INN is /",, 812. The circuit 800 of Figure 8A can be simplified to the circuit 850 of Figure 83 by symmetry such that the circuit 850 of Figure 8B is equivalent to the circuit 800 of Figure 8A. The common mode voltage of VouTp and VouTu is VouTum. As mentioned above, Zi = Zy and Z3 = Z4 so the impedances can be simplified to just Zi and Z3, as illustrated in Figure 83.

[00103] The following equations apply to the common mode equivalent circuit 850 of Figure 83.

VOUTCM = AlVCM

VCM - VOUTCM

VOUTCM VCM

VOU I CM Zy

-

VOUTCM -VCM 1 -Al Iz,VOUTCM, Z3 Z,3 = [00104] The amplifier gain is much larger than 1 so L,-=,/ 0 so Izi = VoLITCM and /z, = Z, VouTCM Z, [00105] Applying Kirchhoffs law: TCM = 1z, + 1 1" -1cm = Vourcm Z3 G Mem VOUTCM Zi* Z3 kZ 3 Zi (CM [00106] As mentioned above, Z3 > Z1 so the common mode gain (GMcm) is smaller due to the connection between the different operational amplifiers of impedance Z3. Thus, circuit 1100 of Figure 6 provides a decreased common mode impedance to voltage gain (GMcm) with respect to typical implementations.

[00107] Thus, the connections between operational amplifiers are a form of bootstrapping that allows both increased differential impedance to voltage gain and decreased common mode impedance to voltage gain with respect to typical implementations. The circuit 1100 is operable in a storage mode and a conversion mode. When switches Si, S6, 52 and 57 are closed and switches So, 55, 53, 54, 58 and 59 are open, the circuit 1100 is operating in storage mode and the connections are as shown in the circuit 400 of Figure 4A. When switches 51, S6, 52 and 57 are open and switches So, Ss, 53, 54, 58 and 59 are closed, the circuit 1100 is operating in conversion mode as shown in the circuit 450 of Figure 4B but with the addition of the connections for bootstrapping as shown in Figures 7A and 8A.

[00108] The outputs Vamp and VouTN of the circuit 1100 may be input into a filter 1102 and/or an integrator 1104. However, in some examples the circuit 1100 may not include a filter 1102 and/or an integrator 1104. These are described below in relation to Figure 10.

[00109] Figure 9 shows an example timing diagram 1150 of the switches of the circuit 1100 of Figure 6. Each signal line represents a switch being open or closed over time and may represent a control line to control the switch. For each switch, a high signal line represents the switch being closed and a low signal line represents the switch being open. At t1 1152, switches S1, S6, S2 and 57 are closed, represented by their signal lines being high, and switches So, 55, £3, 54, .58 and 5, are open, represented by their signal lines being low, and so the circuit 1100 is operating in storage mode. At t4 1158, switches Si, 56, 52 and 57 are open and switches So, Ss, S3, 54,S8 and 59 are closed, and so the circuit 1100 is operating in conversion mode. Due to the delay in transitioning between storage mode and conversion mode, at t2 1154, which is between t1 1152 and t4 1158, all switches except 54 and 56 may be open. Moreover, at t3 1156, which is between t1 1152 and t4 1158, all switches except 53, 5,3, 54 and 59 may be open. An example time for t1 1152 is lps. An example time for t2 1154 and t3 1156 either combined or separately is 0.1 ps. An example time for t4 1158 is 1ms. In an example, Z, 312 and/or Z2 314 may be a 400fF capacitor.

[00110] Figure 10 shows a system 1000 according to an example. The system 1000 comprises a differential impedance to voltage converter circuit 1004 and a controller 1002. The differential impedance to voltage converter circuit 1004 may be any of the circuits mentioned above. For example, differential impedance to voltage converter circuit 1004 may be impedance to voltage converter circuit 300 of Figure 3A, differential impedance to voltage converter circuit 500 of Figures, differential impedance to voltage converter circuit 1100 of Figure 6 or differential impedance to voltage converter circuit 350 of Figure 3B. The controller 1002 is configured to control the switches of the circuit 1004. For example, where circuit 1004 is differential impedance to voltage converter circuit 350 of Figure 3B or differential impedance to voltage converter circuit 500 of Figure 5 or differential impedance to voltage converter circuit 1100 of Figure 6, controller may control whether the switches So to 59 are open or closed, depending on the mode the circuit is operating in. The controller may also be configured to determine the value of and/or provide voltages V, and V, to terminals 324 and 326 respectively when the controller is controlling circuit 300 of Figure 3A, circuit 350 of Figure 3B, circuit 500 of Figure 5 or circuit 1100 of Figure 6.

[00111] The system 1000 may further comprise a filter 1102 and an integrator 1104. For example, the filter 1102 may filter the outputs VouTp and VouTN of the differential impedance to voltage converter circuit 1004 to remove high frequency components. The filter 1102 may provide enhanced noise reduction capabilities. The integrator 1104 may be a switch capacitor integrator to reduce the noise of the outputs VouTp and VouTN. The integrator 1104 may reduce the noise at the outputs and reduce measurement errors due to impedance mismatch effects.

[00112] Figure 11 shows an example of a use of the differential impedance to voltage converter circuit of Figures 3, 5 or 6. Figure 11 shows an example of a block diagram of an array 1200 for use in identifying a device. As can be seen in Figure 11, the array / arrangement 1200 comprises a plurality of cells 1206. Each cell 1206 may be cell 250 of Figure 2B. Each cell of the plurality of cells can be individually addressed using row decoder 1202 and column decoder 1204. The array 1200 may comprise any number of cells 1206. A cell may be considered as a unit of the array 1200 that can be selectively probed.

[00113] In the example shown in Figure 11, each cell 1206 comprises a single elementary circuit having a quantum tunnelling barrier, although the skilled person would appreciate that a cell may comprise, for example, an entire row or column of the array, or some other addressable unit of the array. Particular cell 1206' comprises a first electronic component in the form of a first transistor 352, and a second electronic component in the form of a second transistor 354, which may be equated to the transistors 352 and 354 of Figure 2B. Thus, the first transistor may be DUTp 302 input into any of the circuits of Figures 3, 5 and 6 and the second transistor may be DUTN 304 input into any of the circuits of Figures 3, 5 and 6.

[00114] The gate terminal 180 of transistor 352 is labelled as "L" in Figure 11 and the gate terminal 180 of transistor 354 is labelled as "R" in Figure 11. The cell 1206' may be selected using the row decoder 1202 and column decoder 1204 to apply a voltage to terminal "V in order to apply a potential difference across the quantum tunnelling barriers of the first and second transistors 352, 354. The voltage applied across the quantum tunnelling barrier may be reference voltage V1, as discussed above in relation to Figures 3A and 3B.

[00115] A method for determining an identifier value of a device and the required processing circuitry to operate the above array is described further in United Kingdom patent application no. 1905446.9, entitled "Device Identification With Quantum Tunnelling Currents" and filed on 17 April 2019, which is incorporated by reference herein in its entirety for all purposes.

[00116] A quantum tunnelling current from a cell 1206 of an array 1200 is usually very small (on the scale of nano-amperes or smaller). Each cell 1206 may comprise further electronic circuitry to be able to handle such small currents, for example a switching circuit in order to be able to effectively turn the cell "off". Such circuitry has been described in United Kingdom patent application no. 1807214.0, entitled "Near-zero leakage switching circuit" and filed on 2 May 2018, which is incorporated by reference herein in its entirety for all purposes.

[00117] Variations of the described embodiments are envisaged, for example, the features of all of the disclosed embodiments may be combined in any way and/or combination, unless such features are incompatible.

[00118] A quantum tunnelling barrier as described herein may be of any suitable thickness such that quantum tunnelling through the barrier can occur. For example, the quantum tunnelling barrier may be less than 5nm, or less than 4nm, or less than 3nm, or less than 2nm or less than mm. The quantum tunnelling barrier may be formed of any suitable insulating material such as a dielectric oxide. Although silicon has been mentioned throughout this specification other materials may be used, such as III-V materials. In order to form the quantum tunnelling barriers, dielectrics with any suitable k-value may be used.

[00119] Throughout the specification, transistor devices have been described. The skilled person will appreciate that the transistor devices may be p-or/and n-doped transistor devices and that the dopant density of the devices can also be varied.

[00120] A circuit or system described above may be implemented on a chip, a computer, a tablet, a mobile phone or any other such device.

[00121] It will be appreciated that embodiments of the present invention can be realised in the form of hardware, software or a combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape. It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs that, when executed, implement embodiments of the present invention. Accordingly, embodiments provide a program comprising code for implementing a system or method as claimed in any preceding claim and a machine-readable storage storing such a program. Still further, embodiments of the present invention may be conveyed electronically via any medium such as a communication signal carried over a wired or wireless connection and embodiments suitably encompass the same.

[00122] All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

[00123] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[00124] The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The claims should not be construed to cover merely the foregoing embodiments, but also any embodiments which fall within the scope of the claims.

Claims

CLAIMS1 An impedance to voltage converter circuit operable in an offset storage mode and an impedance to voltage conversion mode, the circuit comprising: a first operational amplifier comprising a first input, a second input and a first output; a second terminal electrically connected to the second input, the second terminal configured to be held at a reference voltage; a first capacitor between a first terminal and the first input; a first feedback loop connectable between the first output and a first junction between the first capacitor and the first input; and a second feedback loop connectable between the first output and a second junction between the first capacitor and the first terminal, the second feedback loop comprising a first impedance; wherein, in the offset storage mode: a third junction between the first capacitor and the first terminal is configured to be held at a first voltage; and the first feedback loop is connected such that the voltage offset of the first operational amplifier is stored across the first capacitor; and wherein, in the impedance to voltage conversion mode: the first terminal is configured to receive a first input current to be converted; the second feedback loop is connected such that the voltage between the first capacitor and the first terminal is the negative voltage offset which compensates the voltage offset of the first operational amplifier.
2 An impedance to voltage converter circuit as claimed in claim 1, the circuit further comprising a first device under test (OUT) electrically connected to the first terminal in the impedance to voltage conversion mode, wherein the first voltage is applied across the first OUT such that the first input current from the first OUT is received at the first terminal.
3. An impedance to voltage converter circuit as claimed in claim 2, wherein the first voltage is selected based on the desired bias of the first OUT.
4 An impedance to voltage converter circuit as claimed in any preceding claim, wherein, in the offset storage mode, the second feedback loop is disconnected and, in the impedance to voltage conversion mode, the first feedback loop is disconnected.
5. An impedance to voltage converter circuit as claimed in any preceding claim, wherein the first input is an inverting input and the second input is a non-inverting input.
6. An impedance to voltage converter circuit as claimed in any preceding claim, wherein the first input current is a nanoampere scale current.
7 A differential impedance to voltage converter circuit operable in an offset storage mode and an impedance to voltage conversion mode, the circuit comprising: the impedance to voltage converter circuit as claimed in any preceding claim; a second operational amplifier comprising a third input, a fourth input and a second output, wherein the second terminal is electrically connected to the third input; a second capacitor between a third terminal and the fourth input; a third feedback loop connectable between the second output and a fourth junction between the second capacitor and the fourth input; a fourth feedback loop connectable between the second output and a fifth junction between the second capacitor and the third terminal, the fourth feedback loop comprising a second impedance, wherein, in the offset storage mode: a sixth junction between the second capacitor and the third terminal is configured to be held at a first voltage; and the third feedback loop is connected such that the voltage offset of the second operational amplifier is stored across the second capacitor; and wherein, in the impedance to voltage conversion mode: the third terminal is configured to receive a second input current to be converted; the fourth feedback loop is connected such that the voltage between the second capacitor and the third terminal is the negative voltage offset which compensates the voltage offset of the second operational amplifier.
8 A differential impedance to voltage converter circuit as claimed in claim 7, the circuit further comprising a second DUT electrically connected to the third terminal in the impedance to voltage conversion mode, wherein the first voltage is applied across the second DUT such that the second input current from the first DUT is received at the third terminal.
9. A differential impedance to voltage converter circuit as claimed in claim 8, wherein the first voltage is selected based on the desired bias of the first and second DUTs.
10. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 9, wherein, in the offset storage mode, the fourth feedback loop is disconnected and, in the impedance to voltage conversion mode, the third feedback loop is disconnected.
11. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 10, wherein the fourth input is an inverting input and the third input is a non-inverting input.
12. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 11, wherein the second input current is a nanoampere scale current.
13. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 12, wherein the difference in current between the first input current and second input current is a sub-picoamp current.
14. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 13, wherein the voltage offset of the first operational amplifier is different to the voltage offset of the second operational amplifier.
15. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 14, wherein, in impedance to voltage conversion mode, the first output is at a first output voltage and the second output is at a second output voltage and the difference between the first output voltage and the second output voltage is dependant on the difference between the first input current and the second input current.
16. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 15, wherein the first voltage is substantially the same as the reference voltage.
17. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 16, wherein the first impedance comprises a third capacitor and the second impedance comprises a fourth capacitor, and wherein the first voltage is different to the initial output voltage, which is determined by the reference voltage.
18. A differential impedance to voltage converter circuit as claimed in any of claims 7 to 17, wherein, in the impedance to voltage conversion mode, the circuit is configured to comprise: a first connection from the second output to a seventh junction between the first terminal and the first input, the first connection comprising a third impedance, a second connection from the first output to an eighth junction between the third terminal and the fourth input, the second connection comprising a fourth impedance.
19. A system for converting impedance to voltage, comprising: a impedance to voltage converter circuit as claimed in any of claims 1 to 7; and a controller configured to operate the circuit in the offset storage mode and the current to voltage conversion mode.
20. A system for converting differential impedance to voltage, comprising: a differential impedance to voltage converter circuit as claimed in any of claims 7 to 18; and a controller configured to operate the circuit in the offset storage mode and the current to voltage conversion mode.
21. The system as claimed in claim 19 or claim 20, the system further comprising a filter to filter the first and second outputs.
22 The system as claimed in any of claims 19 to 21, the system further comprising a switch capacitor integrator to reduce the noise of the first and second outputs.