GB2587032B - Method for designing accelerator hardware - Google Patents
Method for designing accelerator hardware Download PDFInfo
- Publication number
- GB2587032B GB2587032B GB1913353.7A GB201913353A GB2587032B GB 2587032 B GB2587032 B GB 2587032B GB 201913353 A GB201913353 A GB 201913353A GB 2587032 B GB2587032 B GB 2587032B
- Authority
- GB
- United Kingdom
- Prior art keywords
- designing
- accelerator hardware
- accelerator
- hardware
- designing accelerator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/045—Combinations of networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
- G06N3/086—Learning methods using evolutionary algorithms, e.g. genetic algorithms or genetic programming
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Computer Hardware Design (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Artificial Intelligence (AREA)
- Data Mining & Analysis (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Computational Linguistics (AREA)
- Geometry (AREA)
- Neurology (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Medical Informatics (AREA)
- Bioinformatics & Cheminformatics (AREA)
- Bioinformatics & Computational Biology (AREA)
- Evolutionary Biology (AREA)
- Physiology (AREA)
- Complex Calculations (AREA)
- Image Analysis (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1913353.7A GB2587032B (en) | 2019-09-16 | 2019-09-16 | Method for designing accelerator hardware |
KR1020200034093A KR20210032266A (en) | 2019-09-16 | 2020-03-19 | Electronic device and Method for controlling the electronic device thereof |
CN202080052984.1A CN114144794A (en) | 2019-09-16 | 2020-08-13 | Electronic device and method for controlling electronic device |
EP20865553.0A EP3966747A4 (en) | 2019-09-16 | 2020-08-13 | Electronic device and method for controlling the electronic device thereof |
PCT/KR2020/010741 WO2021054614A1 (en) | 2019-09-16 | 2020-08-13 | Electronic device and method for controlling the electronic device thereof |
US17/015,724 US20210081763A1 (en) | 2019-09-16 | 2020-09-09 | Electronic device and method for controlling the electronic device thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1913353.7A GB2587032B (en) | 2019-09-16 | 2019-09-16 | Method for designing accelerator hardware |
Publications (3)
Publication Number | Publication Date |
---|---|
GB201913353D0 GB201913353D0 (en) | 2019-10-30 |
GB2587032A GB2587032A (en) | 2021-03-17 |
GB2587032B true GB2587032B (en) | 2022-03-16 |
Family
ID=68315417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1913353.7A Active GB2587032B (en) | 2019-09-16 | 2019-09-16 | Method for designing accelerator hardware |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR20210032266A (en) |
GB (1) | GB2587032B (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111325327B (en) * | 2020-03-06 | 2022-03-08 | 四川九洲电器集团有限责任公司 | Universal convolution neural network operation architecture based on embedded platform and use method |
CN111652365B (en) * | 2020-04-30 | 2022-05-17 | 哈尔滨工业大学 | Hardware architecture for accelerating Deep Q-Network algorithm and design space exploration method thereof |
CN112613598B (en) * | 2020-12-10 | 2023-04-07 | 上海交通大学 | FPGA simulation-based resistive neural network accelerator evaluation method |
CN112507197B (en) * | 2020-12-18 | 2024-01-19 | 北京百度网讯科技有限公司 | Model searching method, device, electronic equipment, storage medium and program product |
CN113065639B (en) * | 2021-03-08 | 2023-06-13 | 深圳云天励飞技术股份有限公司 | Operator fusion method, system, equipment and storage medium |
CN113033784A (en) * | 2021-04-18 | 2021-06-25 | 沈阳雅译网络技术有限公司 | Method for searching neural network structure for CPU and GPU equipment |
CN113592062A (en) * | 2021-06-30 | 2021-11-02 | 深圳元戎启行科技有限公司 | Neural network configuration method and device, computer equipment and storage medium |
CN113592088B (en) * | 2021-07-30 | 2024-05-28 | 中科亿海微电子科技(苏州)有限公司 | Parallelism determination method and system based on fine-granularity convolution computing structure |
CN113780542B (en) * | 2021-09-08 | 2023-09-12 | 北京航空航天大学杭州创新研究院 | Method for constructing multi-target network structure facing FPGA |
CN115099393B (en) * | 2022-08-22 | 2023-04-07 | 荣耀终端有限公司 | Neural network structure searching method and related device |
KR102531646B1 (en) * | 2022-11-14 | 2023-05-12 | 주식회사 마키나락스 | Method for controlling air conditioning device based on delayed reward |
-
2019
- 2019-09-16 GB GB1913353.7A patent/GB2587032B/en active Active
-
2020
- 2020-03-19 KR KR1020200034093A patent/KR20210032266A/en active Search and Examination
Non-Patent Citations (1)
Title |
---|
Zhang et al.; "When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design", published during 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 15-17 July 2019 * |
Also Published As
Publication number | Publication date |
---|---|
GB2587032A (en) | 2021-03-17 |
KR20210032266A (en) | 2021-03-24 |
GB201913353D0 (en) | 2019-10-30 |
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