GB2579757A - Handling effective address synonyms in a load-store unit that operates without address translation - Google Patents

Handling effective address synonyms in a load-store unit that operates without address translation Download PDF

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Publication number
GB2579757A
GB2579757A GB2006344.2A GB202006344A GB2579757A GB 2579757 A GB2579757 A GB 2579757A GB 202006344 A GB202006344 A GB 202006344A GB 2579757 A GB2579757 A GB 2579757A
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Prior art keywords
effective address
instruction
entry
address
ert
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GB2579757B (en
GB202006344D0 (en
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Sinharoy Balaram
Lloyd Bryan
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International Business Machines Corp
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International Business Machines Corp
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Priority claimed from US15/726,627 external-priority patent/US11175924B2/en
Priority claimed from US15/726,596 external-priority patent/US10606591B2/en
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Publication of GB202006344D0 publication Critical patent/GB202006344D0/en
Publication of GB2579757A publication Critical patent/GB2579757A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of- order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

Claims (20)

1. A processing unit for executing one or more instructions, the processing unit comprising: a load-store unit (LSU) for transferring data between memory and registers, the LSU configured to execute a plurality of instructions in an out-of-order (OoO) window, the execution comprising: in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address; and in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry; and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.
2. The processing unit of claim 1, wherein, in response to the second effective address also corresponding to said first real address: comparing a first page size associated with the first instruction with a second page size associated with the second instruction; and wherein the SDT entry that maps the second effective address to the ERT is created in response to the first page size being greater than the second page size.
3. The processing unit of claim 2, wherein, in response to the first page size being smaller than the second page size: modifying the ERT entry by replacing the mapping between the first effective address and the first real address with a mapping between the second effective address and the first real address.
4. The processing unit of claim 3, wherein, further in response to the first page size being smaller than the second page size: creating the SDT entry that maps the first effective address to the ERT entry.
5. The processing unit of claim 1 , wherein the SDT entry comprises a thread identifier of a thread on which the first instruction is launched, the effective address of the first instruction, a page size of the first instruction, a relaunch effective address of the first instruction, and an ERT entry identifier of the corresponding ERT entry.
6. The processing unit of claim 1 , wherein the first instruction is one from a group of instructions consisting of a load instruction and a store instruction.
7. The processing unit of claim 1 , wherein a counter is maintained to indicate number of instructions launched with the first effective address, and in response to the counter crossing a predetermined threshold, invalidating the ERT entry corresponding to the first effective address.
8. A computer-implemented method for executing one or more out-of-order instructions by a processing unit, the method comprising: issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window, the issuing comprising: in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address; and in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) in an SDT, wherein the SDT entry maps the second effective address to the ERT entry; and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.
9. The computer-implemented method of claim 8, wherein, in response to the second effective address also corresponding to said first real address: comparing a first page size associated with the first instruction with a second page size associated with the second instruction; and wherein, the SDT entry that maps the second effective address to the ERT entry is created in response to the first page size being greater than the second page size.
10. The computer-implemented method of claim 9, wherein, in response to the first page size being smaller than the second page size: modifying the ERT entry by replacing the mapping between the first effective address and the first real address with a mapping between the second effective address and the first real address.
11. The computer-implemented method of claim 10, wherein, in response to the first page size being smaller than the second page size: creating the SDT entry that maps the first effective address to the ERT entry.
12. The computer-implemented method of claim 8, wherein the SDT entry comprises a thread identifier of a thread on which the first instruction is launched, the effective address of the first instruction, a page size of the first instruction, a relaunch effective address of the first instruction, and an ERT entry identifier of the corresponding ERT entry.
13. The computer-implemented method of claim 8, wherein the first instruction is one from a group of instructions consisting of a load instruction and a store instruction.
14. The computer-implemented method of claim 8, wherein a counter is maintained to indicate number of instructions launched with the first effective address, and in response to the counter crossing a predetermined threshold, invalidating the ERT entry corresponding to the first effective address.
15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising: issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window by: in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address; and in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) in an SDT, wherein the SDT entry maps the second effective address to the ERT entry; and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.
16. The computer program product of claim 15, wherein, in response to the second effective address also corresponding to said first real address: comparing a first page size associated with the first instruction with a second page size associated with the second instruction; and wherein, the SDT entry that maps the second effective address to the ERT entry is created in response to the first page size being greater than the second page size.
17. The computer program product of claim 16, wherein, in response to the first page size being smaller than the second page size: modifying the ERT entry by replacing the mapping between the first effective address and the first real address with a mapping between the second effective address and the first real address.
18. The computer program product of claim 17, wherein, in response to the first page size being smaller than the second page size: creating the SDT entry that maps the first effective address to the ERT entry.
19. The computer program product of claim 15, wherein the SDT entry comprises a thread identifier of a thread on which the first instruction is launched, the effective address of the first instruction, a page size of the first instruction, a relaunch effective address of the first instruction, and an ERT entry identifier of the corresponding ERT entry.
20. The computer program product of claim 15, wherein the first instruction is one from a group of instructions consisting of a load instruction and a store instruction.
GB2006344.2A 2017-10-06 2018-10-03 Handling effective address synonyms in a load-store unit that operates without address translation Active GB2579757B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US15/726,627 US11175924B2 (en) 2017-10-06 2017-10-06 Load-store unit with partitioned reorder queues with single cam port
US15/726,596 US10606591B2 (en) 2017-10-06 2017-10-06 Handling effective address synonyms in a load-store unit that operates without address translation
US15/825,453 US11175925B2 (en) 2017-10-06 2017-11-29 Load-store unit with partitioned reorder queues with single cam port
US15/825,494 US10606592B2 (en) 2017-10-06 2017-11-29 Handling effective address synonyms in a load-store unit that operates without address translation
PCT/IB2018/057694 WO2019069255A1 (en) 2017-10-06 2018-10-03 Handling effective address synonyms in a load-store unit that operates without address translation

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GB2579757A true GB2579757A (en) 2020-07-01
GB2579757B GB2579757B (en) 2020-11-18

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GB2006338.4A Active GB2579534B (en) 2017-10-06 2018-10-03 Load-store unit with partitioned reorder queues with single CAM port

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CN (2) CN111133413B (en)
DE (2) DE112018004006B4 (en)
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WO (2) WO2019069255A1 (en)

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JP2023056289A (en) 2021-10-07 2023-04-19 富士通株式会社 Arithmetic processing unit, and arithmetic processing method
CN114780146B (en) * 2022-06-17 2022-08-26 深流微智能科技(深圳)有限公司 Resource address query method, device and system

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Publication number Publication date
GB2579534B (en) 2020-12-16
CN111133413A (en) 2020-05-08
JP7025100B2 (en) 2022-02-24
DE112018004006B4 (en) 2021-03-25
GB2579757B (en) 2020-11-18
CN111133421B (en) 2023-09-29
WO2019069256A1 (en) 2019-04-11
JP2020536308A (en) 2020-12-10
GB202006338D0 (en) 2020-06-17
CN111133421A (en) 2020-05-08
DE112018004006T5 (en) 2020-04-16
WO2019069255A1 (en) 2019-04-11
JP7064273B2 (en) 2022-05-10
JP2020536310A (en) 2020-12-10
DE112018004004T5 (en) 2020-04-16
GB2579534A (en) 2020-06-24
CN111133413B (en) 2023-09-29
GB202006344D0 (en) 2020-06-17

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