GB2573308A

GB2573308A - Near-zero leakage switching circuit

Info

Publication number: GB2573308A
Application number: GB1807214.0A
Authority: GB
Inventors: Awqati Faisal; Camilleri Patrick
Original assignee: Crypto Quantique Ltd
Current assignee: Crypto Quantique Ltd
Priority date: 2018-05-02
Filing date: 2018-05-02
Publication date: 2019-11-06
Anticipated expiration: 2038-05-02
Also published as: GB201807214D0; WO2019211614A1; GB2573308B

Abstract

An electronic switching circuit 100’, e.g. a differential switch, suitable for controlling the flow of a very small current, such as leakage or tunnelling current, comprises first 110’, second 120’ and third 130’ terminals with the second and third terminals at substantially the same potential. A first switching element 140’, connected between the first and second terminals, enables current flow in a first mode and impedes current flow in a second mode. A second switching element 150’, connected between the first and third terminals, impedes current flow in a first mode and enables current flow in a second mode. The first and second modes are controlled by application of a control potential to the first and second switching elements, which may be CMOS transistors, or NMOS or PMOS transistor pairs. A third switching element 175 may be connected between the first terminal and the first and second switching devices to enable current flow between the first and second terminals in the first mode, and impede current flow in the second mode. A device comprising the switching circuit includes an electronic component (Fig.1B, 180), e.g. a capacitor or transistor, connected to the first terminal where, in use, a tunnelling current flows through a quantum tunnelling barrier of the electronic component. A method of operating the device and measuring the current flow is also provided.

Description

[0001] The present disclosure relates to electronic switching circuits for controlling the flow of a current between two terminals. In particular, the present disclosure concerns switching means having near-zero leakage, particularly for use with controlling a flow of small currents. Devices, methods and computer-readable media are also described, which utilise said switching circuits.

Background [0002] To achieve higher integration density and performance, integrated circuits (ICs) and the electronic components (including complementary metal-oxide-semiconductor - “CMOS” components) on which they rely have been scaled downwards in size in recent years, to the extent that quantum mechanical effects are becoming more important to the operation of such devices. For example, due to this scaling down, current may flow through one or more components of a device even when the device is considered to be in an “OFF” state in which current should not classically be able to flow via physical phenomena such as quantum tunnelling. Often, such quantum mechanical effects, including leakage currents / sub-threshold currents, are considered to be losses in such systems and are thought to have a detrimental effect on performance.

[0003] In circumstances for which sensitive measurements of very small currents, such as picoampere scale currents or sub-picoampere scale currents, are required, these quantum effects can cause significant problems with measurements. For example, one may choose to selectively measure one such small current flow from a plurality of such current flows, and so would like to be able to turn off the current flow from the other current flows of the plurality of current flows. However, sub-threshold leakage currents through classically operated switches, such as a single CMOS transistor connected between a current source and the measurement device, would ensure that the measurement device would still measure a current even when the switch is considered to be “OFF”, and such leakage currents are likely to be not much smaller than the current being turned “OFF”.

[0004] It is an object of embodiments of the invention to at least mitigate one or more of the problems of the prior art.

Summary [0005] According to an aspect of the invention, an electronic / electrical switching circuit is provided, the electronic switching circuit for controlling the flow of a current between a first terminal and a second terminal. The switching circuit comprises the first terminal. The switching circuit further comprises the second terminal. The switching circuit further comprises a third terminal at substantially the same potential as the second terminal. The switching circuit further comprises a first switching element connected between the first terminal and the second terminal. The switching circuit further comprises a second switching element connected between the first terminal and the third terminal. The switching circuit further comprises a control terminal electronically coupled to the first switching element and the second switching element, the control terminal for coupling to a control potential to switch the electronic switching circuit between a first mode and a second mode. In the first mode, the first switching element is configured to enable current flow between the first terminal and the second terminal. In the first mode, the second switching element is configured to impede current flow between the first terminal and the third terminal. In the second mode, the first switching element is configured to impede current flow between the first terminal and the second terminal. In the second mode, the second switching element is configured to enable current flow between the first terminal and the third terminal.

[0006] Conventionally, a CMOS transistor may be used on its own as a switch, controlled via a gate potential to turn the flow of current between source and drain “ON” or “OFF”. As a gateto-source voltage is increased past a threshold voltage, a conducting path is formed between the source and drain, turning the CMOS transistor from “OFF” to “ON”. However, conventional CMOS transistor switches may also exhibit the property of subthreshold conduction (also sometimes referred to as sub-threshold leakage or sub-threshold drain current), whereby a small current flows between the source and the drain when the transistor is in sub-threshold region, or weak-inversion region, i.e. for gate-to-source potentials below the threshold voltage. Accordingly, even when such a transistor switch is thought to be “OFF”, a small sub-threshold current often on the picoampere scale still flows through the switch. As transistors have gotten smaller over the years, such leakages have become more relevant. For example, if one is trying to control the flow of a small current (e.g. on the nanoampere or picoampere scale) by turning that current “OFF” then the sub-threshold current may detrimentally lead to erroneous results.

[0007] Advantageously, by providing an electronic switching circuit as described herein, such parasitic leakage currents may be substantially reduced, even to the attoampere scale (that is, on the order of IO'¹⁸ amps) or sub-attoampere scale. A sensitive measuring device connected to (without loss of generality) the first switchable element, indirectly or directly, through the second terminal (respectively the third terminal) of the electronic switching circuit may accordingly, when the switching circuit is configured in the second (or respectively the first) mode, detect a leakage current several orders of magnitude smaller than if a CMOS transistor switch were used. That is, when one believes the current between the first and second terminals to have been turned “OFF” the sub-threshold leakage through the first switchable element is near-zero (and the impedance of the first switching element is very high). In circumstances in which, for example, a controlled current between the first and second terminals is very small, for example on the microampere, nanoampere or picoampere scale, the electronic switching circuits described herein enable enhanced control over the flow of that current.

[0008] In what follows, the phrase “switching circuit” has been used. The skilled person would appreciate that such a term may denote any suitable electronic arrangement that may be used to “make” or “break” an electronic circuit. In particular, the electronic circuits described herein may comprise arrangements of switching elements and connections between terminals that, when incorporated into a larger working electrical circuit, can control the flow of current along conducting paths. A “terminal” as used herein, for example in relation to the “first terminal”, “second terminal”, “third terminal” and “control terminal” is considered to comprise a point at which a conductor from the electronic switching circuit comes to an end and provides a point of connection to external circuits.

[0009] Labels such as “first”, “second”, “third” and “control” have been used to distinguish between different features (e.g. terminals) and are to aid in explanation of the illustrative embodiments described herein. The skilled person would appreciate that the labels themselves are not intended to be limiting. The label “switching” is considered to be synonymous with “switchable”.

[0010] Furthermore, various operations will be described herein as multiple discrete operations, in turn, in a manner that is helpful to understanding the illustrative embodiments. However, the order of the description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of operation. Descriptions of entities and/or modules as separate modules should likewise not be construed as requiring that the modules be separate and/or perform separate operations. In various embodiments, illustrated and/or described operations, entities, data, and/or modules may be merged, broken into further sub-parts, and/or omitted.

[0011] The electronic switching circuits described herein are suitable for controlling the flow of picoampere scale, or sub-picoampere scale currents between a first terminal and a second terminal. “Picoampere scale currents” are considered to be currents of a few picoamperes, or tens of picoamperes, or hundreds of picoamperes. A “sub-picoampere scale current” is considered to be a current that is smaller than a picoampere, for example, on the order of a few femtoamperes, tens of femtoamperes, or hundreds of femtoamperes. The electronic switching circuits describd herein may be used for controlling the flow of nanoampere scale currents or even milliampere scale currents between the first terminal and the second terminal.

[0012] The electronic switching circuits described herein are operable to be switched between a first mode and a second mode. The skilled person would appreciate that “between” may mean that the switching circuit is switched from the first mode to the second mode, or may mean that the switching circuit is switched from the second mode to the first mode. The switching circuit may be operable to switch back and forth between the first mode and the second mode as desired.

[0013] The first switching element may comprise a CMOS switchable element. The second switchable element may comprise a CMOS switching element.

[0014] The first switching element may comprise a first transistor. The control potential may influence a gate potential of the first transistor. The second switching element may comprise a second transistor. The control potential may influence a gate potential of the second transistor. Both of the first transistor and the second transistor may be PMOS transistors. Both of the first transistor and the second transistor may be NMOS transistors. The control terminal may be connected to the first transistor and/or the second transistor via a NOT gate, or inverter.

[0015] The first transistor and/or the second transistor may comprise an oxide layer having a thickness of greater than 3nm. Such a thickness greatly reduces the chance of gate leakage currents through said first transistor and/or second transistor, thereby further reducing noise.

[0016] The electronic switching circuit may further comprise a third switchable element connected between the first terminal and the first switching element and also connected between the first terminal and the second switching element. In the first mode, the third switching element may be configured to enable current flow between the first terminal and the second terminal. In the second mode, the third switching element may be configured to impede current flow between the first terminal and the second terminal. The third switching element may comprise a transistor. Advantageously, by providing a third switching element, when the circuit is operated in the second mode, power leakage is reduced, which may, for example, lead to longer battery life.

[0017] The current may comprise a tunnelling current through a quantum tunnelling barrier of an electronic component. The current may comprise a leakage current through an electronic component.

[0018] According to an aspect of the invention, a device is provided. The device comprises an electronic switching circuit as described herein. The device further comprises an electronic component connected to the first terminal of the electronic switching circuit. The electronic component comprises a first component terminal and a second component terminal, the second component terminal connected to the first terminal of the electronic switching circuit. The electronic component further comprises a quantum tunnelling barrier, the quantum tunnelling barrier located between the first component terminal and the second component terminal. In use, when a potential difference exists between the first component terminal and the second (and third) terminals of the electronic switching circuit, a tunnelling current flows through the quantum tunnelling barrier, the tunnelling current characteristic of the quantum tunnelling barrier.

[0019] In what follows, terms such as “device” and “apparatus” are to be considered as interchangeable and, in some places, have been used interchangeably where the context allows. A device / apparatus may comprise, for example, one or more electronic components, an integrated chip, a computing device, a server, a mobile or portable computer or telephone, and so on. A device / apparatus may comprise a physically unclonable function (PUF).

[0020] A quantum tunnelling barrier as described herein may be of any suitable thickness such that quantum tunnelling through the barrier can occur. For example, the quantum tunnelling barrier may be less than 5nm, or less than 4nm, or less than 3nm, or less than 2nm or less than Inm. The quantum tunnelling barrier may be formed of any suitable insulating material such as a dielectric oxide. Although silicon has been mentioned throughout this specification other materials may be used, such as III-V materials. In order to form the quantum tunnelling barriers, dielectrics with any suitable k-value may be used.

[0021] An electronic / electrical component as described herein may be any suitable electronic component, for example a metal oxide semi-conductor component, or a metal-insulator semiconductor component.

[0022] The electronic component may comprise a capacitor. The electronic component may comprise a transistor, wherein the second component terminal comprises a gate terminal of the transistor, and wherein the first component terminal comprises a source terminal or a drain terminal of the transistor. Throughout the specification, transistor devices have been described. The skilled person will appreciate that the transistor devices may be p- or/and n- doped transistor devices and that the dopant density of the devices can also be varied.

[0023] The electronic switching circuit and the electronic component may be provided together on a microchip. The device itself may comprise a microchip.

[0024] The device may further comprise a controller to apply a control potential to the control terminal of the electronic switching circuit to control the first switching element and the second switching element of the electronic switching circuit.

[0025] The device may further comprise a measurement device configured to measure a current from the second terminal of the electronic switching circuit. The measurement device may be further configured to measure a current from the third terminal of the electronic switching circuit.

[0026] The electronic switching circuit may be a first electronic switching circuit. The electronic device may further comprise a second electronic switching circuit as described herein. The electronic device may further comprise a respective second electronic component connected to the first terminal of the second electronic switching circuit. The second terminal of the first electronic switching circuit and the second terminal of the second electronic switching circuit may be connected. For example, the device may comprise an array of electronic switching circuits as described herein, and may comprise an array of corresponding electronic components each having a quantum tunnelling barrier.

[0027] The electronic device may comprise a measurement device for measuring a current through the second terminal of the first electronic switching circuit, and for measuring a current through the second terminal of the second electronic switching circuit. The measurement device may be suitable for measuring the current through the terminals of any number of switching circuits of the device.

[0028] The electronic device may comprise a controller configured to selectively apply a first control potential to the control terminal of the first electronic switching circuit, and configured to selectively apply a second control potential to the control terminal of the second electronic switching circuit, to thereby select whether the measurement device will measure a tunnelling current from one or both of the first electronic component and the second electronic component. Advantageously, by selectively measuring a tunnelling current from a selected component or combination of components, the device may be interrogated such that, for example, the selected components (and control potentials applied to the corresponding switching circuits) act as a challenge and the measured tunnelling current(s) act as a response uniquely characteristic of the affected electronic components.

[0029] According to an aspect of the invention, a method is provided for operating a device as described herein, particularly when a potential difference exists between the second and third terminals of the electronic switching circuit and the first component terminal, the third terminal being at substantially the same potential as the second terminal. The method comprises applying a control potential to the control terminal of the electronic switching circuit to thereby switch the electronic switching circuit between a first mode and a second mode. In the first mode, the first switching element is configured to enable current flow between the first terminal and the second terminal of the electronic switching circuit. In the first mode, the second switching element is configured to impede current flow between the first terminal and the third terminal of the electronic switching circuit. In the second mode, the first switching element is configured to impede current flow between the first terminal and the second terminal of the electronic switching circuit. In the second mode, the second switching element is configured to enable current flow between the first terminal and the third terminal of the electronic switching circuit. The method may further comprise measuring the current through the second terminal of the electronic switching device. The method may further comprise measuring the current flowing through the third terminal of the electronic switching device. The method may comprise applying the potential difference between the second (and third) terminal of the electronic switching circuit and the first component terminal of the electronic component to cause a tunnelling current to flow through the electronic component.

[0030] According to an aspect of the invention, a computer-readable medium or machinereadable medium or computer program product is provided. The computer-readable medium has instructions stored thereon which, when executed by a processor, cause the processor to perform a method as described herein. The computer-readable medium may comprise a nontransitory computer-readable medium.

[0031] The computer program and/or the code for performing such methods as described herein may be provided to an apparatus, such as a computer, on the computer readable medium or computer program product. The computer readable medium could be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium for data transmission, for example for downloading the code over the Internet. Alternatively, the computer readable medium could take the form of a physical computer readable medium such as semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and an optical disk, such as a CD-ROM, CD-R/W or DVD.

[0032] Many modifications and other embodiments of the inventions set out herein will come to mind to a person skilled in the art to which these inventions pertain in light of the teachings presented herein. Therefore, it will be understood that the disclosure herein is not to be limited to the specific embodiments disclosed herein. Moreover, although the description provided herein provides example embodiments in the context of certain combinations of elements, steps and/or functions may be provided by alternative embodiments without departing from the scope of the invention.

Brief Description of the Figures [0033] Embodiments of the invention will now be described by way of example only, with reference to the accompanying figures, in which:

Figure 1A illustrates an electronic switching circuit;

Figure IB illustrates a device comprising an electronic switching circuit and an electronic component having a quantum tunnelling barrier;

Figure 2 is a block diagram of a device;

Figure 3 is a block diagram of a device;

Figure 4 illustrates a flow chart of a method;

Figure 5 shows a computer readable / machine-readable storage medium; and

Figure 6 illustrates an electronic switching circuit.

[0034] Throughout the description and the drawings, like reference numerals refer to like parts.

Detailed Description [0035] The present invention seeks to provide novel / improved switching arrangements for use in controlling the flow of a current, and appropriate apparatuses and devices for utilising said switching arrangements. Whilst various embodiments are described below, the invention is not limited to these embodiments, and variations of these embodiments may well fall within the scope of the invention which is to be limited only by the appended claims.

[0036] In the following discussion, electronic switching circuits, devices, methods and computer-readable media are described in relation to cryptographic applications, and particularly in the context of uniquely identifying a component or device. However, this is for a context in which the embodiments herein may be used only. The skilled person would understand that the electronic switching circuits, devices, methods and computer-readable media described herein are suitable for many other contexts, particularly when one desires to reduce leakages such as sub-threshold leakages in switching devices. The following detailed description is therefore provided for illustrative purposes only and is not intended to limit the scope of the invention, which is to be limited only by the appended claims.

[0037] Networks such as the Internet have changed the way that everyday tasks are carried out, and this has had major implications for information security. Many everyday tasks require digital devices to securely authenticate and be authenticated by another party and/or securely handle private information. In a world in which an identifier is physically available to the authenticator this is a trivial issue - for example a bank teller may be able to authenticate a bank customer in a bank branch by checking the customer’s passport or other identifying documents. However the situation is far more complicated if the customer’s identifying documents are not immediately available, for example when a customer is provided with an online banking service. The bank must ensure that the correct customer is given access to the correct resources and information. But how can the bank secure the communication link to the customer across a network to prevent eavesdropping or tampering with data, and how can the customer be certain that he or she is connected to their banking service and not an impersonator?

[0038] There are many cryptographic applications that may be employed to address such issues, for example digital signatures or other secret cryptographic keys. In order to provide a secure memory or authentication source, one commonplace method is to place a cryptographic key in a non-volatile electrically erasable programmable read-only memory (EEPROM) or battery backed static random access memory (SRAM) and to use cryptographic operations such as digital signatures or encryption. However, such approaches are often time consuming and can be costly in terms of power consumption. In addition, non-volatile memory is often vulnerable to invasive attacks in which the cryptographic key can be taken. If a stolen cryptographic key is used by a third party in, for example, a bank transaction, the bank would have no immediate way of knowing that the key was being fraudulently used by the third party and so may allow such a fraudulent transaction to proceed.

[0039] Accordingly, it is desirable to be able to uniquely identify a device/apparatus associated with a user such that, without the device/apparatus, certain operations or transactions may not proceed. That is, it is desirable to be able to “fingerprint” a device. Such a fingerprint or identifier must be difficult to clone and largely invariant to environmental factors so that whenever the identity of the device is queried a robust and faithful answer is returned.

[0040] Physically unclonable functions (also known as physical unclonable functions or PUFs) are a cryptographic primitive that are used for authentication and secret key storage without the requirement of secure EEPROMs and other expensive hardware. Instead of storing secrets in digital memory, PUFs derive a secret from the unique physical characteristics of a device, usually introduced during manufacture. Known PUFs are provided on the basis of what would commonly be considered to be classical or macroscopic physics, such as the scattering of laser light through a sheet of hardened epoxy in which tiny silica spheres are suspended, or manufacturing variability in gate delay in some circuits. However, as technology progresses there is a need for ever smaller devices, and PUFs based on such designs are difficult to scale down.

[0041] In what follows, the terms physically unclonable function, physical unclonable function, and PUF are used interchangeably. A PUF comprises an object that performs a functional operation, i.e. when queried with a certain input a PUF produces a measurable output. A PUF is not a true function in the mathematical sense, as an input to a PUF may have more than one possible output. Typically, an input to a PUF is referred to as a “challenge” and the resultant output of the PUF is referred to as a “response”. An applied challenge and its measured response is known as a “challenge-response pair” or “CRP”. In a typical application scenario, often referred to as “enrolment”, one or more challenge-response pairs are gathered from a particular PUF and stored in a corresponding database. In another typical application scenario, often referred to as “verification” or “authentication”, a challenge from the database is applied to the PUF and the response produced by the PUF is compared with the corresponding response from the database. A PUF that can only be interrogated by one or a small number of challenges may sometimes be referred to as a “Physically Obfuscated Key” or “POK”.

[0042] A PUF should be largely invariant to environmental conditions such that its response to any given challenge can be predicted by a valid authenticator having knowledge of a corresponding CRP. This idea is largely captured by the concept of an “intra-distance” between two evaluations on one single PUF instantiation, which is the distance between the two responses resulting from applying a particular challenge twice to the same PUF. One instantiation of a PUF should also be clearly differentiable from another. For a particular challenge, the “inter-distance” between two PUF instantiations is the distance between the two responses resulting from applying the challenge once to both PUF instantiations. The distance measure used can vary depending on the nature of the response - for example, when the response is a bit string, the Hamming distance may be used. Desirably, PUFs should have small intra-distances and large inter-distances.

[0043] In relation to integrated circuits (ICs), a PUF is a pseudorandom function that exploits the random disorders in the integrated circuits’ (complementary metal-oxide-semiconductor “CMOS”) fabrication process to generate random and unique identifiers by physically reducing the IC’s microstructure to a fixed-length string.

[0044] To achieve higher integration density and performance, CMOS devices have been scaled downwards in size in recent years, to the extent that quantum mechanical effects are becoming more important to the operation of such devices. Some of these effects may be detrimental - for example sub-threshold leakage currents between source and drain of a CMOS transistor when in an “OFF” state - and are usually seen as losses or noise in such systems.

[0045] The inventors have recognised that, contrary to such quantum mechanical effects being considered as a loss or source of noise, quantum mechanical effects, and in particular quantum tunnelling, in electronic components such as CMOS components may also be utilised as a useful cryptographic primitive. In particular, such quantum mechanical effects are based on the nanoscale or atomic scale properties of the underlying device and the inventors have further recognised that, as such, these quantum mechanical effects may be used to uniquely identify the underlying device. That is, such quantum mechanical signatures may be used to describe a physically unclonable function or physically obfuscated key.

[0046] The inventors have, in particular, recognised that a quantum tunnelling current through a quantum tunnelling barrier uniquely characterises the quantum tunnelling barrier itself and is, unlike devices which utilise quantum confinement, largely invariant to environmental effects and in particular external temperature. Accordingly, the inventors have recognised that by analysing quantum tunnelling currents, one may implement a PUF or POK.

[0047] The use of electronic components having quantum tunnelling barriers to uniquely identify the components and any devices into which those components have been integrated has been described before, in GB patent application number 1717056.4, which is incorporated herein in its entirety by reference.

[0048] As will be discussed further below, one may therefore seek to provide an array of one or more electronic components, each comprising at least a first component terminal, a second component terminal and an insulating/dielectric/oxide layer therebetween to act as a quantum tunnelling barrier. By selectively measuring tunnelling currents of the electronic components, alone or in selective combinations, one can determine challenge and response pairs for the array.

[0049] In order to measure tunnelling currents for one combination of the electronic components, one may seek to minimise noise from other electronic components, that is, to switch “OFF” any tunnelling currents from the other components. However, as has been mentioned above, in conventional CMOS switches, when the switch is considered to be “OFF”, sub-threshold leakage currents (e.g. between the source and drain on the transistor switch), usually on the order of a few picoamps, may still flow. If one desires to measure tunnelling currents from an array of electronic components, such leakages through the switches contribute a significant source of error.

[0050] Figure 1A illustrates an electronic switching circuit 100. The electronic switching circuit 100 is suitable for controlling a flow of a small current between a first terminal 110 and a second terminal 120 of the electronic switching circuit.

[0051] The electronic switching circuit 100 comprises the first terminal 110 and the second terminal 120. The electronic switching circuit further comprises a third terminal 130.

[0052] A first switching element 140 is connected between the first terminal 110 and the second terminal 120 (and is not connected between the first terminal 110 and the third terminal 130). The first switching element 140 in the present example comprises a complementary metal-oxide-semiconductor (CMOS) transistor arranged such that source and drain terminals of the first switching element 140 are connected to the first and second terminals 110, 120 of the electronic switching circuit 100.

[0053] A second switching element 150 is connected between the first terminal 110 and the third terminal 130 (and is not connected between the first terminal 110 and the second terminal 120). The second switching element 150 in the present example comprises a CMOS transistor arranged such that source and drain terminals of the second switching element 150 are connected to the first and third terminals 110, 130 of the electronic switching circuit 100.

[0054] The electronic switching circuit 100 further comprises a control terminal 160. The control terminal 160 is electronically coupled to the first switching element 140 and to the second switching element 150. The control terminal 160 is suitable for coupling to a control potential to switch the electronic switching circuit 100 between a first mode and a second mode. That is, the control terminal 160 is for connection to a further electronic apparatus/device/component (not shown) that is able to control the application of a control voltage/control potential to the first and second switching elements. The control terminal 160 in Figure 1A is shown connected directly to the gate terminal of the first switching element 140, and accordingly, upon application of a first control potential the first switching element 140 may enable a current flow between the first terminal 110 and the second terminal 120. That is, the first switching element 140 is configured to be “ON”. Upon application of a second potential the first switching element 140 may be configured to impede the flow of current between the first terminal 110 and the second terminal 120. That is, the first switching element 140 may be configured to be “OFF”. The skilled person would appreciate that the application of one of the first or the second control voltage may comprise the application of a zero voltage (i.e. may not imply the active application of a potential at all).

[0055] The electronic switching circuit 100 further comprises a NOT gate, or inverter, 170 connected between the control terminal 160 and the second switching element 150. The NOT gate 170 is connected to the gate terminal of the second switching element 150. Accordingly, upon application of a first control potential the second switching element 150 may impede a flow of current between the first terminal 110 and the third terminal 130. That is, upon application of the first control potential, the second switching element may be configured to be “OFF”. Upon application of a second control potential, the second switching element 150 may be configured to enable the flow of current between the first terminal 110 and the third terminal 130. That is, upon application of the second control potential, the second switching element 150 may be configured to be “ON”.

[0056] The inverter 170 may comprise any suitable logical circuit, as would be appreciated by the person skilled in the art. For example, the inverter may comprise a negative metal-oxidesemiconductor (NMOS) inverter, a positive metal-oxide-semiconductor (PMOS) inverter, a static CMOS inverter, anNPN transistor-transistor logic inverter, a depletion-load NMOS logic NAND, a saturated-load NMOS inverter, or an NPN resistor-transistor logic inverter. The inverter is arranged to output a voltage representing the opposite logic level to its input (control) voltage, such that if an applied control potential is high then the potential at the gate of the second switching element 150 is low and vice versa.

[0057] The electronic switching circuit 100 may therefore be operated in a first mode or in a second mode. In the first mode, the first switching element 140 is configured to enable current flow between the first terminal 110 and the second terminal 120, and the second switching element 150 is configured to impede current flow between the first terminal 110 and the third terminal 130. Accordingly, if an electronic component such as a transistor (see Figure IB) is connected to the first terminal, then any tunnelling current would flow between the first terminal 110 and the second terminal 120. Furthermore, with the electronic switching circuit 100 shown in Figure 1 A, sub-threshold leakage currents through the second switching element 150 are greatly reduced (in comparison to conventional CMOS transistor switch) when operated in the first mode. In the second mode, the first switching element 140 is configured to impede current flow between the first terminal 110 and the second terminal 120, while the second switching element 150 is configured to enable current flow between the first terminal 110 and the third terminal 130. Furthermore, with the electronic switching circuit 100 shown in Figure 1 A, sub-threshold leakage currents through the first switching element 140 are greatly reduced (in comparison to conventional CMOS transistor switch) when operated in the second mode. In this way, when it is not desired to have a current flowing between the first and second terminals, the electronic switching circuit 100 may be operated in the second mode such that the current is redirected such that it passes through the third terminal 130, and a sub-threshold current through the first switching element 140 is substantially zero. In this way, any current measured passing through the second terminal 120 would be significantly smaller than if the third terminal 130 and second switching element 150 were not present as the leakages through the first switching element 140 are greatly reduced. Accordingly, if a measuring device were connected to the second terminal 120, and the electronic switching circuit 100 were operated in the second mode, then a small tunnelling current due to an electronic component connected to the first terminal 110 (see Figure IB) would be turned “OFF” more effectively than using a single classical transistor switch alone in series.

[0058] An application of the electronic switching circuit 100 will now be described with reference to Figure IB, which illustrates the electronic switching circuit 100 coupled to an electronic component 180, which in the present example is a metal-oxide-semiconductor field effect transistor (MOSFET). The electronic switching circuit 100 and the electronic component 180 together may be provided as part of a device, such as a chip 190. The electronic component 180 may be manufactured by any suitable process, such as growing a layer of silicon dioxide (S1O2) on top of a silicon substrate and depositing a layer of metal or polycrystalline silicon.

[0059] As has been mentioned above, as components such as electronic component 180 are made smaller, insulating layers are made thinner until at the nanoscale, quantum tunnelling of charge carriers through the insulating layer may occur. In particular, in a MOSFET such as electronic component 180, the tunnelling is through the insulating layer to the gate terminal (or vice versa). The gate leakage current is strongly correlated with the thickness (oxide thickness) of the insulator layer. A large (for example, greater than 3nm) oxide thickness results in very little quantum tunnelling of electrons, hence a low gate leakage current. On the other hand, gate leakage current increases significantly in the case of a thin oxide causing more electrons to tunnel. Gate leakage current increases exponentially with decreasing oxide thickness.

[0060] It is known that the oxide thickness varies on a lateral scale of 1 to 30 nm as well as on lateral scales of hundreds of nanometres. This variation is a random source of fluctuations. The thickness fluctuations are associated with the Si/SiC>2 interface roughness leading to tunnelling current density fluctuations of several orders of magnitude. Therefore, the gate leakage/quantum tunnelling current of the component 180 is unique and is not physically replicable by another component. The unique tunnelling characteristics of the quantum tunnelling barrier of the electronic component 180 arise from deviations from the nominal characteristics of the electronic component 180 that arise during manufacture.

[0061] Process variability is the naturally occurring variation in attributes of semiconductor devices such as transistors when integrated circuits (IC) are fabricated. The amount of process variation is particularly relevant at small scales, where the variation may be a large percentage of the full length or width of the component and as feature sizes approach fundamental dimensions such as the size of atoms and the wavelength of light for patterning lithography masks. Process variability can be environmental, temporal, or spatial. Spatial variations cause performance differences among electronic components, the differences dependent on the distances between the components or the locations of the components on, for example, an IC.

[0062] Typical spatial variations, such as line width or film thickness non-uniformity, universally exist across lots, across wafers (also known as slices or substrates), across chips and dies, and between circuit blocks and devices. That is, during the manufacture of a CMOS component, variations from nominal component characteristics of a component will creep in due to lot-to-lot variations, wafer-to-wafer variations, chip-to-chip variations, and on-chip variations such as within-die variations.

[0063] Spatial variations can be further classified into systematic and random variations. Systematic variations are repeatable deviations from nominal component characteristics that depend on the component’s spatial position due to the nonidealities of the lithographic system, chamber effects, optical proximity effects and strained silicon effects. Random variations on the other hand, are unpredictable features of component and device variability, such as nonuniformities resulting from random fluctuations in the fabrication process, microscopic fluctuations of the number and location of dopant atoms in a semiconductor channel (for example, in the channel between source and drain electrodes of a MOSFET), referred to as random dopant fluctuations (RDF), line-edge-roughness (LER), and atomic-scale oxidethickness variation (OTV) due to interface roughness, for example, Si/SiCE interface roughness.

[0064] Random dopant fluctuations (RDFs) are a large source of random variation in modern CMOS processes and result from variation in the implanted impurity concentration. In particular, random dopant fluctuation refers to the random variations in the number and locations of dopant atoms in a material such as a metal-oxide semiconductor, for example in a channel region in a MOSFET. Random dopant fluctuations locally modulate the electric field and electron density in the material, to which the direct tunnelling current (e.g. gate leakage current) through the material is very sensitive and so leads to a measurable source of variation between components. In a MOSFET, this means that RDFs have a large effect on gate leakage currents which result from quantum tunnelling through gate oxides. RDFs also cause disparities between components of other electrical properties, such as the threshold voltage, short channel effect, and drain-induced barrier lowering (DIBL). With the gate length scaling down to sublOOnm, the total number of dopant atoms under the gate is reduced to thousands or even hundreds, leading to significant variations in the threshold voltage and drive current for the transistor device.

[0065] For very small structures, for example a length of lOOnm or less, not only the discreteness of the dopant charge, but also the atomicity of matter introduces substantial variation in the individual device/component characteristics. For example, in a MOSFET, a gate oxide thickness at 25 nm is equivalent to a few silicon atomic layers with a typical interface roughness of one to two atomic layers. This introduces more than a 50% variation in the oxide thickness for a process with a Inm gate oxide/insulator layer.

[0066] As there is an exponential dependence of the gate leakage current (gate tunnelling current) on the gate oxide thickness, the oxide thickness variation (OTV) in a MOSFET also leads to differences in gate leakage currents between MOSFETs. Gate oxide thickness can vary on a lateral scale of hundreds of nm, as well as on a much smaller lateral scale of 1 to 30 nm. The thickness fluctuations on a smaller lateral scale are associated with Si/SiCL interface roughness, leading to a deviation from the nominal oxide thickness by one Si(001) inter-atomic plane distance. For a 1-E5nm thick S1O2 gate dielectric, such thickness fluctuations lead to local tunnelling current density fluctuations of orders of magnitude, which increases the mean of the total tunnelling current, relative to that of a uniform (manufactured to nominal characteristics) component.

[0067] The combined effects of RDFs and OTV greatly affect the gate leakage current variability. At high gate bias, gate leakage variability is dominated by the effects of oxide thickness variation, and discrete doping atoms have a negligible impact. This can be explained because at high gate bias, the excess electron charge in the substrate screens the bare potential of the ionised impurities, and the RDF induced fluctuations of the tunnelling current density become too localised, compared to the OTV induced fluctuations.

[0068] Line-edge roughness (LER) is another source of intrinsic gate leakage variability. Line edge roughness is caused by the tendencies of lithographic photoresists to aggregate in polymer chains. These aggregates are large enough to locally affect the speed of the resist development process, which translates to a loss of resolution and low fidelity of the line edge. This is of importance for the formation of the gate pattern, and translates to an uncertainty of the gate length along the width of the component. Although the leakage gate current is linearly proportional to the gate dimensions, it must be kept in mind that the distribution of random impurities forming the source and drain extension is correlated to the gate line edge roughness.

[0069] In MOS structures, such as in electronic component 180, one may distinguish three different quantum tunnelling processes such as Fowler-Nordheim tunnelling, direct tunnelling, and trap-assisted tunnelling.

[0070] In direct tunnelling, charge carriers can tunnel directly through the potential barrier that is formed by the conducting band. The significance of direct tunnelling is exponentially dependent on the thickness of the oxide (e.g. insulator layer) and the oxide perpendicular field, but it is only linearly sensitive to the gate width and source/drain extension overlaps. Direct tunnelling may involve electrons tunnelling from the conduction band of the substrate to the conduction band of the gate terminal (or vice versa) which is known as electrons in the conduction band (ECB), or electrons tunnelling from the valence band of the substrate to the conduct band of the metal which is known as valence band tunnelling (EVB).

[0071] The quantum tunnelling current exhibits a weak temperature dependence because the electric field across the oxide does not strongly depend on temperature. Advantageously, this means that an identifier determined from a measured electrical signal representative of the quantum tunnelling current through an insulating layer of a MOSFET is largely insensitive to temperature and thus is more reproducible than an identifier based on a mechanism that is temperature dependent.

[0072] Referring back to Figure IB, the gate terminal of the electronic component 180 is connected to the first terminal 110 of the electronic switching circuit 100. Source and drain terminals 182, 184 of the electronic component 180 are held at the same potential, for example by both being connected to the same silicon substrate of the chip 190. The gate terminal of the electronic component 180 is separated from the source and drain terminals 182, 184 by an oxide layer having a small thickness such that the oxide layer acts as a quantum tunnelling barrier.

[0073] In use, the second and third terminals 120, 130 are held at substantially the same potential. This may be achieved using any suitable method /apparatus, for example the use of a voltage follower circuit or a regulator. However, a potential difference exists between the second terminal 120 (and third terminal 130) of the electronic switching circuit 100 and the source terminal 182 (and drain terminal 184) of the electronic component 180. The potential difference across the insulating layer of the electronic component 180 enables quantum tunnelling through the insulating layer, and this leakage current is a unique identifier of the electronic component 180 (and therefore can be used to uniquely identify the device 190). A first control potential may be applied to the electronic switching circuit 100 in order to configure the first switching element 140 to enable current to flow between the second terminal 120 and the first terminal 110 (and therefore the source terminal 182 and drain terminal 184 of the electronic component 180) and to configure the second switching element 150 to impede current flow between the third terminal and the first terminal. A measuring device (not shown) in connection with the second terminal 120 may therefore measure the leakage current through the oxide layer of the electronic component 180.

[0074] In order to stop measuring the gate leakage current of the electronic component 180 (colloquially, to turn “OFF” the leakage current), a second control potential may be applied to the electronic switching circuit 100 (which may be a zero potential - that is, may comprise turning off a potential) in order to configure the first switching element 140 to impede current flow between the second terminal 120 and the first terminal 110 (and therefore between the second terminal 120 and the source and drain terminals 182, 184 of the electronic component 180) and to configure the second switching element 150 to enable current flow between the first terminal 110 and the third terminal 130. Due at least in part to the balanced potentials of the second and third terminals, the (sub-threshold) leakage current through the channel between the source and drain of the first switching element 140 is negligible (on the order of attoamperes or below) and so, to all intents and purposes, the measuring device experiences the gate leakage current of the electronic component as having been turned off.

[0075] The skilled person would appreciate that the description provided above in relation to Figures 1A and IB is illustrative and that other variations on the architecture described are relevant also.

[0076] For example, the first switching element 140 and the second switching element 150 in the present example may both be positive channel metal-oxide-semiconductor (PMOS) transistors. The first and second switching elements 140, 150 may both comprise negative channel metal-oxide-semiconductor (NMOS) transistors. In some examples, the first switching element may be a PMOS switching element and the second switching element may comprise a NMOS switching element, or vice versa. When the switching elements 140, 150 comprise CMOS transistors, the insulating / oxide layers of those transistors may have a thickness of greater than 3nm, or may have a thickness of greater than 4nm, or may have a thickness of greater than 5nm and so on.

[0077] The quantum tunnelling barrier of the electronic component 180 may have a thickness of less than 5nm, or may have a thickness of less than 4nm, or may have a thickness of less than 3nm or may have a thickness of less than 2nm, or may have a thickness of less than Inm.

[0078] The electronic component 180 may or may not comprise a CMOS transistor. For example, a capacitor may be used instead. There are many capacitor designs but in its simplest form a capacitor comprises two conductive plates separated by a dielectric medium. When the dielectric medium is sufficiently thin (for example an average thickness of less than 3nm), the dielectric does not act as a perfect insulator and so a leakage current, usually on the order of a few nanoamperes, begins to flow. This small DC current flow is based on quantum tunnelling. Leakage current is a result of electrons physically making their way through the dielectric medium and is often seen as an unwanted artefact as, over time, the capacitor will fully discharge if the supply voltage is removed. The inventors have realised that the leakage current of a capacitor can be used to determine a unique identifier of that capacitor, and therefore be used to determine a unique identifier for any device in which that capacitor is installed.

[0079] The inverter 170, may or may not be present. For example, dependent on the types of switching elements 140, 150 used, there may be no need for an inverter 170. Alternatively the inverter / NOT gate 170 may be connected between the control terminal 160 and the first switching element 140 as opposed to between the control terminal 160 and the second terminal 150.

[0080] The chip 190 may be manufactured by any suitable process, and may comprise a second electronic switching circuit and a second respective electronic component. The chip 190 may comprise further electronic switching circuits and corresponding electronic components, such as an array of electronic switching circuits and corresponding components, each electronic component having a quantum tunnelling barrier unique to that component.

[0081] Figure 2 is a block diagram of a device 200. The device 200 comprises an array 220 of electronic components 180, each having at least a first component terminal and a second component terminal, the first component terminal and the second component terminal of each electronic component 180 separated by a respective quantum tunnelling barrier (QTB) unique to the electronic component 180. For example, the array 220 may comprise a plurality of transistors for which the source and drain terminals are held at equipotential, wherein the first component terminal of any given component 180 comprises the source terminal (or drain terminal) of the transistor, and wherein the second component terminal of the given component 180 comprises the gate terminal of the transistor. The unique characteristics of the QTB of each component 180 ensure that any tunnelling current through the QTB will be representative of that particular component. Accordingly, each electronic component 180 of the array 220 will be associated with a respective quantum tunnelling current or gate leakage current profile (the tunnelling current being dependent on the potential difference across the quantum tunnelling barrier).

[0082] Each electronic component 180 of the QTB component array 220 is connected to a corresponding first terminal 110 of a corresponding switching circuit 100 within a switch array 210. For example, each electronic component 180 may be connected to a corresponding switching circuit 100 as shown in Figure IB.

[0083] The device 200 further comprises a measuring device 240 connected, directly or indirectly, to the switch array 210. For example, the measuring device 240 may be connected to the second terminals 120 of each electronic switching circuit 100 of the switch array 210. The measuring device 240 may measure a current directly, or may comprise circuitry for comparing the current to a predetermined threshold value to output a binary output dependent on whether the current is above or below the threshold value.

[0084] The device 200 further comprises a controller 230. The controller 230 is configured to control the application of a control potential to a control terminal 160 of each switching circuit 100 of the switch array 210, thereby determining whether a leakage current from each respective electronic component 180 of the QTB component array 220 flows between the first and second terminals 110, 120 of the corresponding switching circuit 100 to be measured by the measurement device 240.

[0085] The potential difference between the second terminal 120 (and third terminal 130) of any particular switching circuit 100 of the array 210 and the first component terminal of the corresponding electronic component 180 of the component array 220 that causes a tunnelling current to pass through the corresponding quantum tunnelling barrier may be applied by the controller 230, or may be applied by the measuring device 240. The potential difference may also exist due to the materials used without needing to actively be applied.

[0086] The controller 230 may address each switching circuit individually and so may selectively configure one or more of the electronic switching circuits 100 of the switch array 210 to operate in the first mode in which a tunnelling current passing through the second terminal(s) of those switching circuits is measured by the measuring device 240 while selectively configuring the remaining electronic switching circuits 100 of the switch array 210 to operate in the second mode in which a tunnelling current instead passes through the third terminal and is not measured by the measurement device 240. The controller may comprise, for example, a row decoder and a column decoder to select which electronic switching circuits of the switch array 210 are manipulated at any given time.

[0087] The measurement device 240 may be configured to individually measure the current from each switching circuit 100 (and corresponding electronic component 180) operating in the first mode, or may be configured to measure the total leakage current from all switching circuits (and corresponding components 180) operating in the first mode. In some examples, the measurement device 240 or a second measurement device may be connected to the respective third terminal 130 of each electronic switching circuit 100 in order to measure any leakage currents, individually or together, from switching circuits operating in the second mode. As discussed above in relation to Figures 1A and IB, sub-threshold leakages through the first and second switching elements of each switching circuit are negligible, leading to greater accuracy in measurements.

[0088] The skilled person would appreciate that the description of the device of Figure 2 is illustrative only and that variations on the architecture shown in Figure 2 are envisaged. For example, although the switch array 210 and the component array 220 have been shown as separate (connected) arrays, they may be provided as a single combined array. The device 200 may comprise, for example, one or more electronic components, an integrated chip, a computing device, a server, a mobile or portable computer or telephone, and so on.

[0089] Figure 3 is a block diagram of a device 300. For example, device 300 may comprise a computing device, a server, a mobile or portable computer or telephone and so on. Figure 3 shows in particular an electronic device or apparatus 300. Other architectures to that shown in Figure 3 may be used as will be appreciated by the skilled person.

[0090] Referring to the figure, the apparatus 300 includes a number of user interfaces including visualising means such as a visual display 310 and a virtual or dedicated user input device 312. The apparatus 300 includes a processor 314, a memory 316 and a power system 318. The apparatus 300 comprises a communications module 320 for sending and receiving communications between processor 314 and remote systems. For example, communications module 320 may be used to send and receive communications via a network such as the Internet.

[0091] The device 300 comprises a port 322 for receiving, for example, a non-transitory computer readable medium containing instruction to be processed by the processor 314. The processor 314 is configured to receive data, access the memory 316, and to act upon instructions received either from said memory 316, from communications module 320 or from user input device 312.

[0092] The device further comprises a switching array 324, similar to switching array 210 of Figure 2, and a QTB component array 326, similar to QTB component array 210 of Figure 2.

[0093] The processor 314 of Figure 3 may act as both the controller 230 of Figure 2 and the measuring device 240 of Figure 2. That is, the processor may act upon instructions received via communications module 320, port 322, input device 312 or retrieved from memory 316 to control the application of a control potential to selected switching circuits of the switch array 324. The processor may also measure the output from the switch circuits of the switch array 324.

[0094] Device 300 is operable to work in much the same way as the device 200 of Figure 2.

[0095] Figure 4 is a flow diagram of a method for operating a device such as device 190, device 200 or device 300. It is assumed that a potential difference exists, or is made to exist, between the second terminal 120 (and third terminal 130) of at least one electronic switching circuit 100 and the first component terminal of a respective connected electronic component 180 across a quantum tunnelling barrier, such that a tunnelling current passes through the quantum tunnelling barrier.

[0096] At step 410, the method comprises applying a control potential to the electronic switching circuit to configure the first switching element 140 and the second switching element 150 of that switching circuit 100 such that the tunnelling current may flow between the first component terminal of the electronic component 180 and the second terminal 120, while being impeded from flowing between the third terminal 130 and the first component terminal.

[0097] At step 420, the method comprises measuring the tunnelling current, for example with a measuring device 240 or processor 314.

[0098] To stop measuring the tunnelling current, a second control potential may be applied, the second control potential suitable for configuring the first switching element 140 to impede the flow of current between the second terminal 120 and the first component terminal of the connected electronic component 180, and for configuring the second switching element 150 to enable the flow of current between the third terminal and the first component terminal of the connected electronic component 180. Optionally, the measuring device 260, 314 or a second measuring device may be connected to the third terminal to measure current passing through the third terminal. As has been discussed above in relation to Figures 1A and IB, the electronic switching circuits described herein have an effect that sub-threshold leakages (and indeed other leakages) through the first and second switching elements are negligible.

[0099] Figure 5 illustrates a computer readable medium 520 according to some examples. The computer readable medium 520 stores units, with each unit including instructions 530 that, when executed, cause a processor 510 (for example processor 314 of Figure 3) or other processing device to perform particular operations. The computer readable medium 520 includes instructions 530 that, when executed, cause a controller to control the application of a control potential to the control terminal 160 of an electronic switching circuit 100 as described herein to thereby switch the electronic circuit 100 between a first mode and a second mode.

[0100] The machine readable medium 520 may further comprise instructions that, when executed, cause a processor to measure a tunnelling current.

[0101] The units of the computer readable medium 520 may cause a processing device 320 to operate in accordance with any of the examples described herein.

[0102] Figure 6 illustrates a second electronic switching circuit 100’ that may be used in place of electronic switching circuit 100. The electronic switching circuit 100’ comprises a first terminal 110’, a second terminal 120’, a third terminal 130’, a first switching device 140’, a second switching device 150’, a control terminal 160’ and an inverter 170’, each operable in the same way as their counterpart components describes above.

[0103] Electronic switching circuit 100’ further comprises a third switching element 175, which may also be a transistor. The third switching element 175 is connected between the first terminal 110’ and the first switching element 140’. The third switching element 175 is also connected between the first terminal 110’ and the second switching element 150’. The third switching element 175 is also controllable via the control potential.

[0104] A control potential may be applied to the control terminal 160’ to control whether the switching circuit is configured to operate in a first mode or in a second mode. In the first mode, the first switching element 140’ is configured to enable the flow of current (i.e. is “ON”). In the first mode, the second switching element 150’ is configured to impede the flow of current (i.e. is “OFF”). In the first mode, the third switching element 175 is configured to enable current flow between the first terminal 110’ and the first switching element 140’ (i.e. is “ON”). In the second mode, the first switching element is configured to impede the flow of current (i.e. is “OFF”). In the second mode, the second switching element 150’ is configured to enable current flow (i.e. is “ON”). In the second mode, the third switching element 175 is configured to impede current flow between the first switching element 140’ and the first terminal 110’.

[0105] In this way, the third switching element 175 acts to further impede the flow of current between the first terminal 110’ and the second terminal 120’ when one does not want current to flow therebetween.

[0106] Variations of the described embodiments are envisaged, for example, the features of all of the disclosed embodiments may be combined in any way and/or combination, unless such features are incompatible.

[0107] It will be appreciated that embodiments of the present invention can be realised in the form of hardware, software or a combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape. It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs that, when executed, implement embodiments of the present invention. Accordingly, embodiments provide a program comprising code for implementing a system or method as claimed in any preceding claim and a machine-readable storage storing such a program. Still further, embodiments of the present invention may be conveyed electronically via any medium such as a communication signal carried over a wired or wireless connection and embodiments suitably encompass the same.

[0108] Although the discussion above has mentioned the use of electronic switching circuits to measure tunnelling currents for security purposes, for example for implementing a PUF, the skilled person would appreciate that such circuits are suitable for use in any situation in which control over a picoampere scale or sub-picoampere scale current is required.

[0109] All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

[0110] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[0111] The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The claims should 5 not be construed to cover merely the foregoing embodiments, but also any embodiments which fall within the scope of the claims.

Claims

1. An electronic switching circuit for controlling the flow of a current between a first terminal and a second terminal, the switching circuit comprising:

the first terminal;

the second terminal;

a third terminal at substantially the same potential as the second terminal;

a first switching element connected between the first terminal and the second terminal; a second switching element connected between the first terminal and the third terminal; a control terminal electronically coupled to the first switching element and the second switching element, the control terminal for coupling to a control potential to switch the electronic switching circuit between a first mode and a second mode;

wherein, in the first mode, the first switching element is configured to enable current flow between the first terminal and the second terminal, and the second switching element is configured to impede current flow between the first terminal and the third terminal; and wherein, in the second mode, the first switching element is configured to impede current flow between the first terminal and the second terminal, and the second switching element is configured to enable current flow between the first terminal and the third terminal.

2. An electronic switching circuit according to claim 1, wherein the first switching element comprises a complementary metal-oxide-semiconductor, CMOS, switching element, and/or wherein the second switching element comprises a CMOS switching element.

3. An electronic switching circuit according to claim 1 or claim 2, wherein the first switching element comprises a first transistor, and wherein the control potential influences a gate potential of the first transistor.

4. An electronic switching circuit according to claim 1 or claim 2 or claim 3, wherein the second switching element comprises a second transistor, and wherein the control potential influences a gate potential of the second transistor.

5. An electronic switching circuit according to claim 1, wherein the first switching element comprises a first transistor;

wherein the second switching element comprises a second transistor;

wherein the control potential influences the gate potentials of the first transistor and the second transistor;

wherein both of the first transistor and the second transistor are PMOS transistors or both of the first transistor and the second transistor are NMOS transistors; and wherein the control terminal is connected to the first transistor or the second transistor via a NOT gate.

6. An electronic switching circuit according to any of claims 2-5, in which the first transistor and/or the second transistor comprises an oxide layer having a thickness of at least 3nm.

7. An electronic switching circuit according to any preceding claim, wherein the electronic switching circuit further comprises:

a third switching element connected between the first terminal and the first switching element and also connected between the first terminal and the second switching element.

8. An electronic switching circuit according to claim 7, wherein:

in the first mode, the third switching element is configured to enable current flow between the first terminal and the second terminal; and in the second mode, the third switching element is configured to impede current flow between the first terminal and the second terminal.

9. An electronic switching circuit according to claim 7 or claim 8, wherein the third switching element comprises a transistor.

10. An electronic switching circuit according to any preceding claim, wherein the current comprises a tunnelling current through a quantum tunnelling barrier of an electronic component.

11. An electronic switching circuit according to any preceding claim, wherein the current comprises a leakage current through an electronic component.

12. A device comprising:

an electronic switching circuit according to any preceding claim; and an electronic component connected to the first terminal of the electronic switching circuit, the electronic component comprising:

a first component terminal and a second component terminal, the second component terminal connected to the first terminal of the electronic switching circuit; and a quantum tunnelling barrier, the quantum tunnelling barrier located between the first component terminal and the second component terminal; wherein, in use, when a potential difference exists between the first component terminal and the second and third terminals of the electronic switching circuit, a tunnelling current flows through the quantum tunnelling barrier, the tunnelling current characteristic of the quantum tunnelling barrier.

13. A device according to claim 12, wherein the electronic component comprises a capacitor.

14. A device according to claim 13, wherein the electronic component comprises a transistor, wherein the second component terminal comprises a gate terminal of the transistor, and wherein the first component terminal comprises a source terminal or a drain terminal of the transistor.

15. A device according to any of claims 12-14, wherein the electronic switching circuit and the electronic component are provided on a microchip.

16. A device according to any of claims 12 to 15, wherein the device further comprises:

a controller to apply a control potential to the control terminal of the electronic switching circuit to control the first switching element and the second switching element of the electronic switching circuit.

17. A device according to any of claims 12 to 16, wherein the device further comprises:

a measurement device configured to measure a current through the second terminal of the electronic switching circuit.

18. A device according to claim 17, wherein the measurement device is further configured to measure a current through the third terminal of the electronic switching circuit.

19. A device according to any of claims 12 to 18, wherein the electronic switching circuit is a first electronic switching circuit, and wherein the device further comprises:

a second electronic switching circuit according to any of claims 1 to 11; and a respective second electronic component connected to the first terminal of the second electronic switching circuit;

wherein the second terminal of the first electronic switching circuit and the second terminal of the second electronic switching circuit are connected.

20. A device according to any of claims 12 to 15, wherein the electronic device further comprises:

a measurement device for measuring a current through the second terminal of the first electronic switching circuit, and for measuring a current through the second terminal of the second electronic switching circuit; and a controller configured to selectively apply a first control potential to the control terminal of the first electronic switching circuit, and configured to selectively apply a second control potential to the control terminal of the second electronic switching circuit, to thereby select whether the measurement device will measure a current from one or both of the first electronic component and the second electronic component.

21. A method for operating a device according to any of claims 12 to 20, wherein a potential difference exists between the second and third terminals of the electronic switching circuit and the first component terminal, the third terminal being at substantially the same potential as the second terminal, the method comprising:

applying a control potential to the control terminal of the electronic switching circuit to thereby switch the electronic switching circuit between a first mode and a second mode;

wherein, in the first mode, the first switching element of the electronic switching circuit is configured to enable current flow between the first terminal and the second terminal, and the second switching element of the electronic switching circuit is configured to impede current flow between the first terminal and the third terminal; and wherein, in the second mode, the first switching element of the electronic switching circuit is configured to impede current flow between the first terminal and the second terminal, and the second switching element of the electronic switching circuit is configured to enable current flow between the first terminal and the third terminal.

22. A method according to claim 21, further comprising measuring the current through the second terminal of the electronic switching device.

23. A method according to claim 21 or claim 22, further comprising measuring the current flowing through the third terminal of the electronic switching device.

24. An electronic switching circuit to control the flow of a nanoampere or sub-nanoampere scale current between a first terminal and a second terminal, the current comprising a quantum tunnelling current through a quantum tunnelling barrier of an electronic component, the switching circuit comprising:

the first terminal;

the second terminal;

a third terminal at substantially the same potential as the second terminal;

a first switching element connected between the first terminal and the second terminal; a second switching element connected between the first terminal and the third terminal;

a control terminal electronically coupled to the first switching element and the second switching element, the control terminal to couple to a control potential to switch the electronic switching circuit between a first mode and a second mode;

wherein, in the first mode, the first switching element is configured to enable the flow of the quantum tunnelling current between the first terminal and the second terminal, and the second switching element is configured to impede the flow of the quantum tunnelling current between the first terminal and the third terminal; and wherein, in the second mode, the first switching element is configured to impede the flow of the quantum tunnelling current between the first terminal and the second terminal, and the second switching element is configured to enable the flow of the quantum tunnelling current between the first terminal and the third terminal.

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24. A method according to any of claims 21 to 23, wherein the method comprises applying the potential difference between the second and third terminals of the electronic switching circuit and the first component terminal of the electronic component to cause a tunnelling current to flow through the electronic component.

25. A computer readable medium having instructions stored thereon which, when executed by a processor, cause the processor to perform a method according to any of claims 21 to 24.

Amendments to the claims have been filed as follows 34

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Claims

1. A device comprising:

an electronic switching circuit to control a quantum tunnelling current between a first terminal and a second terminal, the switching circuit comprising:

the first terminal;

the second terminal;

a third terminal at substantially the same potential as the second terminal;

a first switching element connected between the first terminal and the second terminal;

a second switching element connected between the first terminal and the third terminal;

wherein, in the first mode, the first switching element is configured to enable the flow of the quantum tunnelling current between the first terminal and the second terminal, and the second switching element is configured to impede the flow of the quantum tunnelling current between the first terminal and the third terminal; and wherein, in the second mode, the first switching element is configured to impede the flow of the quantum tunnelling current between the first terminal and the second terminal, and the second switching element is configured to enable the flow of the quantum tunnelling current between the first terminal and the third terminal; and an electronic component connected to the first terminal of the electronic switching circuit, the electronic component comprising:

a first component terminal and a second component terminal, the second component terminal connected to the first terminal of the electronic switching circuit; and a quantum tunnelling barrier, the quantum tunnelling barrier located between the first component terminal and the second component terminal;

wherein, in use, when a potential difference exists between the first component terminal and the second and third terminals of the electronic switching circuit, a quantum tunnelling current flows through the quantum tunnelling barrier, wherein the quantum tunnelling current is characteristic of the quantum tunnelling barrier.

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2. A device according to claim 1, wherein the first switching element comprises a complementary metal-oxide-semiconductor, CMOS, switching element, and/or wherein the second switching element comprises a CMOS switching element.

3. A device according to claim 1 or claim 2, wherein the first switching element comprises a first transistor, and wherein the control potential influences a gate potential of the first transistor.

4. A device according to claim 1 or claim 2 or claim 3, wherein the second switching element comprises a second transistor, and wherein the control potential influences a gate potential of the second transistor.

5. A device according to claim 1, wherein the first switching element comprises a first transistor;

wherein the second switching element comprises a second transistor;

6. A device according to claim 3 or 5, in which the first transistor comprises an oxide layer having a thickness of at least 3nm.

7. A device according to any of claims 4-5, in which the second transistor comprises an oxide layer having a thickness of at least 3nm.

8. A device according to any preceding claim, wherein the electronic switching circuit further comprises:

7 07 19 a third switching element connected between the first terminal and the first switching element and also connected between the first terminal and the second switching element.

9. A device according to claim 8, wherein:

in the first mode, the third switching element is configured to enable the flow of the quantum tunnelling current between the first terminal and the second terminal; and in the second mode, the third switching element is configured to impede the flow of the quantum tunnelling current between the first terminal and the second terminal.

10. A device according to claim 8 or claim 9, wherein the third switching element comprises a transistor.

11. A device according to any of the preceding claims, wherein the electronic component comprises a capacitor.

12. A device according to any of claims 1 to 10, wherein the electronic component comprises a transistor, wherein the second component terminal comprises a gate terminal of the transistor, and wherein the first component terminal comprises a source terminal or a drain terminal of the transistor.

13. A device according to any of the preceding claims, wherein the electronic switching circuit and the electronic component are provided on a microchip.

14. A device according to any of the preceding claims, wherein the device further comprises:

a controller to apply the control potential to the control terminal of the electronic switching circuit to control the first switching element and the second switching element of the electronic switching circuit.

15. A device according to any of the preceding claims, wherein the device further comprises:

a measurement device configured to measure the current through the second terminal of the electronic switching circuit.

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16. A device according to claim 15, wherein the measurement device is further configured to measure the current through the third terminal of the electronic switching circuit.

17. A device according to any of the preceding claims, wherein the electronic switching circuit is a first electronic switching circuit, and wherein the device further comprises:

a second electronic switching circuit; and a respective second electronic component connected to the first terminal of the second electronic switching circuit;

18. A device according to any of claims 1 to 13, wherein the electronic device further comprises:

19. A method for operating a device according to any of the preceding claims, wherein a potential difference exists between the second and third terminals of the electronic switching circuit and the first component terminal, the third terminal being at substantially the same potential as the second terminal, the method comprising:

wherein, in the first mode, the first switching element of the electronic switching circuit is configured to enable the flow of the quantum tunnelling current between the first terminal

7 07 19 and the second terminal, and the second switching element of the electronic switching circuit is configured to impede the flow of the quantum tunnelling current between the first terminal and the third terminal; and wherein, in the second mode, the first switching element of the electronic switching circuit is configured to impede the flow of the quantum tunnelling current between the first terminal and the second terminal, and the second switching element of the electronic switching circuit is configured to enable the flow of the quantum tunnelling current between the first terminal and the third terminal.

20. A method according to claim 19, further comprising measuring the quantum tunnelling current through the second terminal of the electronic switching device.

21. A method according to claim 19 or claim 20, further comprising measuring the quantum tunnelling current flowing through the third terminal of the electronic switching device.

22. A method according to any of claims 19 to 21, wherein the method comprises applying the potential difference between the second and third terminals of the electronic switching circuit and the first component terminal of the electronic component to cause a quantum tunnelling current to flow through the electronic component.

23. A computer readable medium having instructions stored thereon which, when executed by a processor, cause the processor to perform a method according to any of claims 19 to 22.