GB2566895A - Power device and preparation method therefor - Google Patents

Power device and preparation method therefor Download PDF

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Publication number
GB2566895A
GB2566895A GB1901361.4A GB201901361A GB2566895A GB 2566895 A GB2566895 A GB 2566895A GB 201901361 A GB201901361 A GB 201901361A GB 2566895 A GB2566895 A GB 2566895A
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trench
trenches
source
region
source regions
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GB2566895B (en
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Wang Peilin
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

A power device (200) and a preparation method therefor. The power device (200) comprises a first device (1) and at least one second device (2). The first device (1) is provided with multiple first source regions (12) and multiple first grooves (13). The multiple first grooves (13) electrically isolate the multiple first source regions (12). The at least one second device (2) is provided with multiple second source regions (22) and multiple second grooves (23). The multiple second grooves (23) electrically isolate the multiple second source regions (22). The second device (2) is embedded into the first device (1) and the second grooves (23) of the second device (2) communicate with the corresponding first grooves (13) of the first device (1). The second source regions (22) of the second device (2) and the first source regions (12) of the first device (1) are electrically isolated by means of metal spacing regions (5), and the parts, except the grooves, of body regions of the first device (1) and the second device (2) are active regions. According to the power device (200) and the preparation method therefor, the structure of the first device (1) is not changed when the second device (2) is embedded, so that current and voltage performance of the first device (1) is not affected.

Description

[0001] The present disclosure relates to the field of semiconductor technologies, and more particularly to a power device and a method for manufacturing the power device.
BACKGROUND [0002] In order to monitor operating state of a power device, it is necessary to perform a quantitative measurement of amount of current conducted by the device (usually a scaling factor (generally referred as CSR) is applied to amount of current in the device) at full scale to ensure safety of the device, for example in the field of automotive electronics. Conventionally, a current sensor device, such as a mirrored current device, is coupled at an appropriate position in an entire device (referred to as main device) to provide such measurement. The coupling and isolation of the current sensor device with or from the main device is very important.
SUMMARY [0003] According to an aspect of the present disclosure, a power device is provided. The power device includes: a first device having a plurality of first source regions and a plurality of first trenches, the plurality of first source regions being electrically isolated from each other by the plurality of first trenches; at least one second device having a plurality of second source regions and a plurality of second trenches, the plurality of second source regions being electrically isolated from each other by the plurality of second trenches, wherein the second device is embedded in the first device, each second trench of the second device is in connection with a corresponding first trench of the first device, and the second source regions of the first device are electrically isolated from the first source regions of the first device by a metal spacing region, and wherein all regions except trenches in body parts of the first device and the second device are active regions.
[0004] According to an aspect of the present disclosure, a method for manufacturing a power device is provided. The method includes: providing a substrate; forming a body part of the first device and a body part of at least one second device on the substrate; and forming a plurality of first trenches for the first device in the body part of the first device and forming a plurality of second trenches for the second device in the body part of the second device, wherein each second trench of the second device is in connection with a corresponding first trench of the first device; forming a plurality of first source regions for the first device and a plurality of second source regions for the second device, wherein the plurality of first source regions are electrically isolated from each other by the plurality of first trenches, and the plurality of second source regions are electrically isolated from each other by the plurality of second trenches, and wherein the second source regions of the second device and the first source regions of the first device are electrically isolated by a metal spacing region, wherein all regions except the trenches in the body parts of the first device and the second device are active regions.
[0005] According to the power device and the method for manufacturing the power device, the first device and the second device are coupled and isolated in a unique manner, and since there is no additional high concentration of diffusion region (i.e., source regions are not removed) in an area where the second device is embedded in the first device, embedding of the second device is smooth and does not cause structural changes to the first device, and thus does not adversely affect current-voltage performance of the first device. In addition, since source regions are not removed in the area where the second device is embedded in the first device, this portion can still contribute to current supply, so that there is no waste of any chip area.
BRIEF DESCRIPTION OF THE DRAWINGS [0006] The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings. The drawings are schematic and should not be construed as limiting the disclosure in any way. In the drawings:
[0007] Fig.l is a simplified plan view showing a power device in accordance with an exemplary embodiment of the present disclosure;
[0008] Fig.2 is a plan view showing details of a power device in accordance with an exemplary embodiment of the present disclosure;
[0009] Fig.3 to Fig.5 respectively show cross-sectional views along lines A-A, B-B and C-C in Fig. 2;
[0010] Fig. 6 is a plan view showing details of a power device according to an exemplary embodiment of the present disclosure;
[0011] Fig.7 to Fig.8 respectively show cross-sectional views along lines D-D and E-E in Fig 6;
[0012] Fig. 9 shows cross-sectional views of the parts 601 to 603 in Fig. 6;
[0013] Fig. 10 is a plan view showing details of a power device according to an exemplary embodiment of the present disclosure;
[0014] Fig. 11 to Fig. 13 respectively show cross-sectional views along lines F-F, G-G and H-H in Fig. 10;
[0015] Fig. 14 shows a cross-sectional view of the part 1001 in Fig 10;
[0016] Fig. 15 is a flowchart illustrating a method for manufacturing a power device according to an exemplary embodiment of the present disclosure.
DETAILED DESCRIPTION [0017] The detailed description of embodiments of the present disclosure provide a lot of details in order to provide a complete understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some of these details. The following description of embodiments is merely intended to provide a clearer understanding of the invention. The present invention is in no way limited to any specific configuration as set forth below, but cover modifications, alternations and changes of related elements without departing from the spirit and scope of the invention. [0018] The detailed description below is merely exemplary in nature and is not intended to limit the invention or application and use of the invention. Furthermore, it is not intended to limit the invention to any theory expressed or implied by the foregoing technical field, the background or the detailed description below.
[0019] The abbreviations MOSFET and IGBT as used in the present disclosure refer to metal oxide semiconductor field effect transistors and insulated gate bipolar transistors, respectively. The MOSFET and the IGBT respectively have a conductive gate electrode, however it should be understood that a conductive material is not necessarily a metal material, but may be, for example, a metal alloy, a semimetal, a metal semiconductor alloy or compound, a doped semiconductor, or a combination thereof. In the present disclosure, reference to metal contact and the like should be interpreted broadly to include various conductive materials discussed above and is not intended to be limited solely to a metallized conductors. Non-limiting examples of an insulating material suitable for use in MOSFETs and IGBTs may include oxides, nitrides, oxygen-nitrogen mixtures, organic insulating materials, and other dielectrics.
[0020] The drawings illustrate a general structure and description and details of various well-known features and techniques may be omitted to avoid unnecessarily obscuring the present invention. In addition, elements in the drawings are not necessarily drawn to scale. For example, some of elements or regions in the drawings may be exaggerated with respect to other elements or regions in order to help understanding of embodiments of the present disclosure.
[0021] The ordinal numbers such as first, second, third, fourth, and the like, are used for distinguish between similar elements or steps and is not necessarily used to described a particular sequence. It is to be understood that the terms as used are interchangeable, where appropriate, such that embodiments of the present disclosure described herein, for example, can work or perform sequentially in accordance with those described herein or any other way. In addition, the terms comprising, including, having or the like refers to a non-exclusive inclusion, such that a process, method, product or device comprising a series of elements or steps is not necessarily limited to those elements or steps, but may include other elements or steps that are not explicitly listed or inherently belonging to such process, method, product or devices. The term connection as used herein is defined to mean a connection, either directly or indirectly, in an electrical or non-electrical manner. As used herein, the terms substantially and substantially mean in a practical manner sufficient to accomplish the stated purpose, and those minor defects, if any, are not apparent to the claimed purpose. [0022] The term additional in the description and claims means beyond a normal state. For example, an additional high concentration of diffusion refers to a diffusion outside normal diffusion in an active region and having a higher concentration than bulk concentration.
[0023] As used herein, the term substrate may refer to a semiconductor substrate, regardless of a single crystal, polycrystalline or amorphous semiconductor, and includes Group IV semiconductors, non-Group IV semiconductors, compound semiconductors, and organic and inorganic semiconductors, and may be, for example, a film structure or a laminated structure.
[0024] For convenience and non-limiting purposes of illustration, a silicon semiconductor is used herein to describe the power device and the methods for manufacturing the power device, but those skilled in the art will appreciate that other semiconductor materials can also be used. In addition, various device types and/or doped semiconductor regions may be labeled as N-type or P-type, but this is for convenience of illustration and is not intended to be limiting, and such markings may be replaced with more general descriptions like first conductivity type or second inverse conductivity type , where the first conductivity type may be either N-type or P-type, and the second conductivity type may also be P-type or N-type.
[0025] According to an aspect of the present disclosure, a power device is provided. The power device includes: a first device having a plurality of first source regions and a plurality of first trenches, the plurality of first source regions being electrically isolated from each other by the plurality of first trenches; at least one second device having a plurality of second source regions and a plurality of second trenches, the plurality of second source regions being electrically isolated from each other by the plurality of second trenches, wherein the second device is embedded in the first device, each second trench of the second device is in connection with a corresponding first trench of the first device, and the second source regions of the first device are electrically isolated from the first source regions of the first device by a metal spacing region, and wherein all regions except trenches in body parts of the first device and the second device are active regions.
[00261 In an embodiment, the plurality of second source regions of the second device may be arranged centrally.
[0027] In an embodiment, the first device and the second device may be formed on a P+N substrate, and the power device is an insulated gate bipolar transistor. In an embodiment, the first device and the second device may be formed on an N+N substrate, and the power device is a metal oxide semiconductor field effect transistor.
[0028] In an embodiment, each second source region of the second device corresponds to a corresponding first source region of the first device, and each second trench of the second device is in direct connection with a corresponding first trench of the first device. In a particular implementation, the power device may further include a plurality of third trenches, wherein the third trench is located in the metal spacing region, and each third trench corresponds to a corresponding second source region of the second device and connects two second trenches corresponding to the second source region. The first trench, the second trench, and the third trench may be structurally identical. In another implementation, the first source region of the first device may have a first metal contact region and the second source region of the second device may have a second metal contact region, wherein boundary of each first metal contact region is at a distance from boundary of a corresponding second metal contact region such that current does not flow laterally along a plane any longer.
[0029] In an embodiment, each second source region of the second device corresponds to two first source regions of the first device, and the power device further comprises a plurality of fourth trenches, each of which having a three-terminal shape, corresponding to a corresponding second source region of the second device, and connecting two second trenches corresponding to the second source region with a trench between two first source regions corresponding to the second source region. The first trench, the second trench, and the fourth trench may be structurally identical.
[0030] According to the power device and the method for manufacturing the power device, the first device and the second device are coupled and isolated in a unique manner, and since there is no additional high concentration of diffusion region (i.e., source regions are not removed) in an area where the second device is embedded in the first device, embedding of the second device is smooth and does not cause structural changes to the first device, and thus does not adversely affect current-voltage performance of the first device. In addition, since source regions are not removed in the area where the second device is embedded in the first device, this portion can still contribute to current supply, so that there is no waste of any chip area.
[0031] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings.
[0032] Fig. 1 is a simplified plan view showing a power device 100 in accordance with an exemplary embodiment of the present disclosure. As shown in Fig. 1, the power device 100 includes a first device 1 and a second device 2. In one example, the second device 2 may be a current sensor device, such as a mirrored current device. The second device 2 is formed on a same substrate 3 as the first device 1, that is, the second device 2 and the first device 1 are coupled in a same chip, so that the second device 2 and the first device 1 can be as under the same conditions (such as temperature). The substrate 3 may be a P+N substrate, whereby the power device 100 may be an insulated gate bipolar transistor (IGBT), or the substrate may be an N+N substrate, whereby the power device 100 may be a metal oxide semiconductor field effect transistor (MOSFET).
[0033] The second device 2 is embedded in the first device 1 and the second device 2 is electrically isolated from the first device 1. Actually, the second device 2 has a drain and a gate connected to that of the first device 1, except that their source regions are electrically isolated. The second device 2 and the first device 1 are electrically isolated by a metal spacing region (not shown). That is, the source regions of the second device 2 and the source regions of the first device 1 are electrically isolated by a certain distance between their source metals.
[0034] As shown in Fig. 1, the power device 100 further includes a gate electrode terminal 4, and each gate of the first device 1 and the second device 2 is connected to the gate electrode terminal 4. Specifically, poly silicon in each gate trench of the first device 1 and the second device 2 is connected to the gate electrode terminal 4.
[0035] It should be understood that although the second device 2 is illustrated as being located approximately at the central portion of the first device 1 and only one second device 2 is illustrated, this is merely an example. The second device 2 may be located at any other location in the first device 1 or more than one second device 2 may be included, depending on temperature distribution and specific requirements of the chip.
[0036] The total effective area (i.e., the area of metal source region) of the second device 2 is in a certain proportional (CSR) to the total effective area of the first device 1 (CSR) in order to obtain a current proportional to current of the first device 1. Thus, it is possible to determining amount of current conducted by the first device 1 by way of current collected by the second device 2, thereby enable monitoring of state of the first device 1.
[0037] Fig. 2 is a plan view showing details of a power device 200 in accordance with an embodiment of the present disclosure. As shown in Fig. 2, the power device 200 includes a first device 1 and a second device 2. The second device 2 is embedded in the first device 1 and the second device 2 is electrically isolated from the first device 1 by a metal spacing region 5. As described above, the metal spacing region 5 electrically isolates source regions of the second device 2 from source regions of the first device 1. In Fig. 2, a region out of an outer dashed line indicates metal materials 11 of the first device 1, and a region inside an inner dashed line indicates metal materials 21 of the second device 2. More specifically, the uppermost layer of the chip is a metal layer, the region out of the outer dotted line is filled with metal materials of the first device 1, and the region inside the inner dotted line is filled with metal materials of the second device 2. The region between the two dashed lines is the metal spacing region 5 to separate metal materials of the first device 1 from metal materials of the second device 2, correspondingly separating source regions of the first device 1 from source regions of the second device 2. In the present disclosure, the metal spacing region 5 represents that the metal materials 11 of the first device 1 is located far away from metal materials 21 of the second device 2.
[0038] Referring to Fig. 2, the first device 1 has a plurality of first source regions 12, each of which has its first metal contact 14. The first device 1 collects current through these first source regions 12 during operation. Similarly, the second device 2 has a plurality of second source regions 22, each of which has a second metal contact 24. The second device 2 collects current through these second source regions 22. The current collected by the second device 2 through all of the second source regions 22 should be in a predetermined proportional relationship with the current collected by the first device 1 through all of the first source regions 12. By measuring the current collected by the second device 2, the amount of current conducted by the first device 1 can be determined, in order for monitoring state of the first device 1. It should be understood that these source regions 12 and 22 are actually located below the metal layer, as illustrated below.
[0039] Further, as shown in Fig. 2, the first device 1 further includes a plurality of first trenches 13. In one example, the first trench 13 may be a strip trench. These first trenches 13 electrically isolate the plurality of first source regions 12 of the first device 1 from each other. Similarly, the second device 2 further includes a plurality of second trenches 23. In one example, the second trench 23 may be a strip trench. These second trenches 23 electrically isolate the plurality of second source regions 22 of the second device 2 from each other. As shown in Fig. 2, each second trench 23 of the second device 2 is in connection with a corresponding first trench 13 of the first device 1. Actually, the first trenches 13 and the second trenches 23 are located in body parts of the first device 1 and the second device 2 and correspond to gates of the first device 1 and the second device 2, respectively. That is, the gate of the first device 1 is connected with the gate of the second device 2.
[0040] Furthermore, as shown in Fig. 2, each second source region 22 of the second device 2 corresponds to a corresponding first source region 12 of the first device 1, and each second trench 23 of the second device 2 is in connection with a corresponding first trench 13 of the first device 1. The power device 200 also includes a plurality of third trenches 6. Each third trench 6 corresponds to a corresponding second source region 22 of the second device 2 and connects two second trenches 23 corresponding to the second source region 22. As shown, each third trench 6 also corresponds to a corresponding first source region 12 of the first device 1 and connects two first trenches 13 corresponding to the first source region 12. In one example, the third trench 6 may be located within the metal spacing region 5. The third trench 6 not only acts as a gate but also allows a source region 22 of the second device 2 to be sufficiently isolated from a corresponding source regions 12 of the first device 1. In one example, the third trench 6 may be a strip trench. The third trench 6 may be identical in structure to the first trench 13 and the second trench 23.
[0041] More specifically, the second source region 22-1 of the second device 2 corresponds to the first source regions 12-1 of the first device 1. The second trenches 23-1 and 23-2 of the second device 2 are in connection with the first trenches 13-1 and 13-2 of the first device 1, respectively. The third trench 6 corresponds to the second source region 22-1 of the second device 2, and connects the two second trenches 23-1 and 23-2 corresponding to the second source region 22-1. Further, as shown, the third trench 6 also corresponds to the first source region 12-1 of the first device 1, and connects the two first trenches 13-1 and 13-2 corresponding to the first source region 12-1.
[0042] In addition, as shown in Fig. 2, the plurality of second source regions 22 of the second device 2 are separated by the second trenches 23, but the second source regions are arranged centrally, that is, adjacent two second sources regions 22 are not separated by any other source region. Although six source regions and corresponding metal contacts of the second device 2 are shown in Fig. 2, this is merely a schematic view, and the second device 2 may have more or fewer source regions and corresponding metal contacts, depending on the predetermined ratio CSR of the second device 2 with respect to the first device 1.
[0043] Fig. 3 to Fig.5 respectively show cross-sectional views along lines A-A, B-B and C-C in Fig. 2. Fig. 3 shows a cross-sectional view along line A-A of Fig. 2. Referring back to Fig. 2, the line A-A spans metal region of the first device 1 and metal region of the second device 2, and both ends of the line A-A are located just in a source metal contact 14 of the first device 1 and a source metal contact 24 of the second device 2. As shown in Fig. 3, the first device 1 and the second device 2 are formed on the same substrate 3. In one embodiment, the first device 1 and the second device 2 may be formed on the P+N type substrate or the N+N type substrate.
[0044] Further, as shown in Fig. 3, an active region is formed on the substrate 3. The active region includes an N-type layer and a P-type layer. A trench 6 is formed in the active region. An N+ layer is formed on the P-type layer, and a P+ region is formed in the P-type layer and the N+ layer. An oxide layer 10 is deposited over the trench 6 filled with polysilicon. At two sides of the oxide layer 10, the metal material 11 of the first device 1 and the metal material 21 of the second device 2 are provided and separated by the metal spacing region 5, and thus the source region 12 of the first device 1 and the source region 22 of the second device 2 are electrically isolated. The trench 6 filled with polysilicon not only serve to connect gates of the first device 1 and the second device 2, but also assist to sufficiently isolate the source region 12 of the first device 1 and the source region 22 of the second device 2. The first device 1 and the second device 2 collect respective currents via metal contacts 14 and 24 of respective source regions along arrows II and 12 indicating current flow.
[0045] Fig. 4 shows a cross-sectional view along line B-B of Fig. 2. Referring back to Fig. 2, the line B-B line spans the metal material 11 of the first device 1 and the metal material 21 of the second device 2, and one end of the line B-B is located just above the source metal contact 14 of the first device 1, and the other end does not correspond to the source metal contact 14 of the first device 1. Referring to Fig. 4, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal material 11 of the first device 1 and the metal material 21 of the second device 2 are separated by the metal spacing region 5. Since one end of the line B-B is located just above the source metal contact 14 of the first device 1, the first device 1 can collect current through the first metal contact 14 of the first source region. However, the other end of the line B-B line does not correspond to a source metal contact of the second device 2, so the second device 2 does not collect current here. As shown, currents in the region below the oxide layer 10 and the metal material 21 of the second device 2 are all collected by the first device 1 via the first metal contact 14 of the first source region. [0046] Fig. 5 shows a cross-sectional view along line C-C of Fig. 2. Referring back to Fig. 2, the line C-C line spans the metal material 11 of the first device 1 and the metal material 21 of the second device 2, and the C-C line is perpendicular to and spans 5 trenches. Referring to Fig. 5, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal material 11 of the first device 1 and the metal material 21 of the second device 2 are electrically isolated by the metal spacing region 5. The intermediate trench below the oxide layer 10 (i.e., in the metal spacing region) also contributes to isolation of the metal material 11 of the first device 1 from the metal material 21 of the second device 2. Further, as it is away from the intermediate trench, one end of the line C-C line enters the metal region of the first device 1, and the other end enters the metal region of the second device 2. In the first device 1, there are two further trenches 13 and there is a first metal contact 14 of the first source region between the two trenches. Between the two trenches 13, current is collected through the metal contact 14. On the other hand, in the second device 2, there are also two further trenches 23 and a second metal contact 24 of the second source region between the two trenches 23. Between the two trenches 23, current is collected through the metal contact 24. Thus, the first device 1 and the second device 2 respectively collect their own currents along the arrows II and 12 indicating current flow as shown.
[0047] It should be noted that in the power device according to the embodiment of the present disclosure, all regions except trenches in body parts of the first device and the second device are active regions. That is, in addition to the active regions of the second device 2 and the first device 1 themselves, there is no additional high concentration of diffusion (i.e. source regions are not removed) in a portion where the second device 2 is embedded with the first device 1 (including a part of the metal spacing region separating source regions of the second device 2 and source regions of the first device 1, and a part of source regions of the first device 1 under metal materials of the second device 2 (the metal materials of the second device 2 above this part function as a source lead-out line of the second device 2). As such, embedding of the second device 2 is smooth and does not cause structural changes to the first device 1, and thus does not adversely affect current-voltage performance of the first device 1. In addition, since source regions are not removed in the area where the second device is embedded in the first device, this portion can still contribute to current supply, so that there is no waste of any chip area.
[0048] Fig. 6 is a plan view showing a second power device 300 according to another exemplary embodiment of the present disclosure. As shown in Fig. 6, like the power device 200 shown in Fig. 2, the power device 300 includes a first device 1 and a second device 2. The second device 2 is embedded in the first device 1 and the second device 2 is isolated from the first device 1 by a metal spacing region 5. Furthermore, the first device 1 has a plurality of source regions 12 and a plurality of trenches 13. These first trenches 13 electrically isolate the plurality of source regions 12 of the first device 1 from each other. The second device 2 has a plurality of source regions 22 and a plurality of trenches 23. These second trenches 23 electrically isolate the plurality of source regions 22 of the second device 2 from each other. Further, likewise, the trench 23 of the second device 2 is in connection with the trench 13 of the first device 1, and the source regions 22 of the second device 2 are arranged centrally.
[0049] The power device 300 of Fig. 6 differs from the power device 200 of Fig. 2 in arrangement of source regions and trenches. Therefore, aspects and details consistent with the power device 200 shown in Fig. 2 are not described herein again. The arrangement of source regions and trenches of power device 300 is discussed in detail below.
[0050] As shown in Fig. 6, in the present exemplary embodiment, each second source region 22 of the second device 2 corresponds to two first source regions 12 of the first device 1, and the power device 22 further includes a plurality of fourth trenches 7, each of which has a three-terminal shape, corresponds to a corresponding second source region 22 of the second device 2 and connects two second trenches 23 corresponding to the second source region 22 with a trench 13 between two first source regions 12 corresponding to the second source region 22. More specifically, the source region 22-1 of the second device 2 corresponds the two second trenches 23-1 and 23-2, and corresponds to the two first source regions 12-1 and
12- 2 of the first device 1. The first trench 13-1 is provided between the two first source regions 12-1 and 12-2. The fourth trench 7 has a three-terminal shape, corresponds to the second source region 22-1, and connects the second trenches 23-1 and 23-2 with the first trench 13-1, wherein two terminals among the three terminals are respectively connected to the second trench 23-1 and 23-2, and the remaining terminal is conenctd with the first trench
13- 1. In Fig. 8, specifically, the three-terminal shape may be a shape like the letter T. However, the three-terminal shape may be any other shape, such as may be any shape like the letter Y.
[0051] Fig. 7 to Fig. 8 shows cross-sectional views along lines D-D and E-E, respectively, of Fig. 6. Fig. 7 shows a cross-sectional view along line D-D in Fig 6. Referring back to Fig. 6, the line D-D spans the metal region of the first device 1 and the metal region of the second device 2, and the line D-D line does not span any source metal contact. Referring to Fig. 7, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal materials 11 of the first device 1 and the metal materials 21 of the second device 2 are separated by the metal spacing region 5. A trench 7 is formed in the body part below the oxide layer 10 for connecting the trenches of the first device 1 and the trenches of the second device 2. Since the line D-D does not span any source metal contact, there is no current expression in Fig. 7.
[0052] Fig. 8 is a cross-sectional view along line E-E of Fig 6. Referring back to Fig. 6, the line E-E spans the metal materials 11 of the first device 1 and the metal materials 21 of the second device 2, and the line E-E is perpendicular to and spans three trenches. Referring to Fig. 8, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal materials 11 of the first device 1 and the metal materials 21 of the second device 2 are electrically isolated by the metal spacing region 5. The intermediate trench below the oxide layer 10 (i.e., in the metal spacing region) also contributes to isolation of the metal materials 11 of the first device 1 from the metal materials 21 of the second device 2. Further, as it is away from the intermediate trench, one end of the line E-E enters the metal region of the first device 1, and the other end enters the metal region of the second device 2. In the first device 1, there is another trench 13, and a metal contact 14 of a first source region is provided at the left side of this trench 13 in order for collecting current. On the other hand, in the second device 2, there is also a trench 23, and a metal contact 24 of a second source region is provided at the right side of this trench 23 for collecting current. Thus, the first device 1 and the second device 2 respectively collect their own currents along the arrows II and 12 indicating current flow as shown.
[0053] Fig. 9 illustrate cross-sectional views of different parts 601 and 602 in Fig. 6. Referring back to Fig. 6, the part 601 is located within the first device 1 and spans a trench 13 and two source metal contact 14 at two sides of the trench 13; the part 602 is located within the second device 2 and spans the head part of a T-shaped trench 7, with the remaining terminal is located on a source metal contact of the second device 2. Referring to Fig. 9, cross-sectional views of positions 601 and 602 are shown in Fig. (a) and (b), respectively. For the part 601, the uppermost layer is filled with metal materials 11 of the first device 1. Since the part 601 spans a trench 13, a trench 13 is illustrated in this view. The trench 13 serves to isolate the source regions 12 of the first device 1. Since both ends of the part 601 are located on source metal contacts 14 of the first device 1, two metal contacts 14 are illustrated in Fig. 9(a), and the two metal contacts 14 respectively collects currents along respective arrows I indicating current flow.
[0054] For the part 602, the uppermost layer is filled with metal materials 21 of the first device 2. Since the part 602 spans a trench 7, a trench 7 is illustrated in this view. The trench 7 serves to isolate a source region of the first device 1 from a source region of the second device 2. Since one end of the part 602 is located on a source metal contact 24 of the second device 2, a metal contact 24 is illustrated in Fig. 9(b) and this metal contact 24 collects current along an arrow I indicating current flow.
[0055] It should be noted that another part 603 is also shown in Fig. 6. The structure of the part 603 is the same as the structure of the part 601 except that the uppermost metal materials and involved source regions are metal materials and source region contacts of the second device 2, which are labeled as 21 and 24 in Fig 9(a), and the trentch is correspondingly labeled as 23.
[0056] Also, it should be noted that in the power device according to embodiments of the present disclosure, all regions except trenches in body parts of the first device and the second device are active regions. That is, in addition to the active regions of the second device 2 and the first device 1 themselves, there is no additional high concentration of diffusion (i.e. source regions are not removed) in a portion where the second device 2 is embedded with the first device 1 (including a part of the metal spacing region separating source regions of the second device 2 and source regions of the first device 1, and a part of source regions of the first device 1 under metal materials of the second device 2 (the metal materials of the second device 2 above this part function as a source lead-out line of the second device 2). As such, embedding of the second device 2 is smooth and does not cause structural changes to the first device 1, and thus does not adversely affect current-voltage performance of the first device 1. In addition, since source regions are not removed in the area where the second device is embedded in the first device, this portion can still contribute to current supply, so that there is no waste of any chip area.
[0057] Fig. 10 is a plan view showing a power device 400 in accordance with another exemplary embodiment of the present disclosure. As shown in Fig. 10, like the power device 200 shown in Fig. 2, the power device 400 includes a first device 1 and a second device 2. The second device 2 is embedded in the first device 1 and the second device 2 is isolated from the first device 1 by a metal spacing region 5. Furthermore, the first device 1 has a plurality of source regions 12 and a plurality of trenches 13. These first trenches 13 electrically isolate the plurality of source regions 12 of the first device 1 from each other. The second device 2 has a plurality of second source regions 22 and a plurality of second trenches 23. These second trenches 23 electrically isolate the plurality of source regions 22 of the second device 2 from each other. Furthermore, the second trenches 23 of the second device 2 are in connection with the first trenches 13 of the first device 1, and the source regions 22 of the second device 2 are arranged centrally.
[0058] The power device 400 of Fig. 10 differs from the power device 200 of Fig. 2 is in arrangement of source regions and trenches. Therefore, aspects and details consistent with the power device 200 shown in Fig. 2 are not described herein again. The arrangement of source regions and trenches of power device 400 are discussed in detail below.
[0059] As shown in Fig. 10, in the present exemplary embodiment, each second source region 22 of the second device 2 corresponds to a corresponding first source region 12 of the first device 1, and each trench 23 of the second device 2 is in connection with a corresponding first trench 13 of the first device 1. Unlike the power device 200, the power device 400 does not have the third trenches 6 as shown in Fig. 2. Rather, a metal contact 24 of a second source region 22 of the second device 2 is at a distance F from a metal contact 14 of a corresponding first source region 12 of the first device 1 such that current cannot no longer flow laterally along the plane, thereby sufficient isolation of source regions of the first device 1 and source regions of the second device 2 is achieved. In one example, the distance F may be between 10 pm and 50 pm. It should be understood that the distance is desired to be small as much as possible as long as it enables current no longer move laterally along the plane. [0060] Fig. 11 to Fig. 14 illustrate cross-sectional views along lines F-F, G-G and H-H, respectively, of Fig. 10. Fig. 11 is a cross-sectional view along line F-F of Fig. 10. Referring back to Fig. 10, the line F-F spans the metal region of the first device 1 and the metal region of the second device 2, and both ends of the line F-F are located just in a metal contact of a source region 12 of the first device 1 and a metal contact of a source region 22 of the second device 2. As shown in Fig. 11, the metal materials 11 of the first device 1 and the metal materials 21 of the second device 2 are separated by a metal spacing region 5. An oxide layer 10 is provided below the metal layer. There is no trench between the first source region 12 of the first device 1 and the second source region 22 of the second device 2, but the first source region 12 of the second device 1 is located at a certain distance from the second source region 22 of the second device such that current is no longer laterally flowable. As shown, the first device 1 and the second device 2 collect respective currents along arrows II and 12 indicating current flow through metal contacts 14 and 24 of the source regions 12 and 22, respectively. As such, current collection of the second device 2 does not affect normal operation of the first device 1.
[0061] Fig. 12 is a cross-sectional view along line G-G of Fig. 10. Referring back to Fig. 10, the line G-G line spans the metal region of the second device 2 and its two ends are respectively located on metal contacts 14 of first source regions 12 on both sides of the first device 1. Referring to Fig. 12, the metal materials 11 of the first device 1 and the metal materials 21 of the second device 2 are separated by a metal spacing region 5. An oxide layer 10 is provided below the metal layer. Since a source metal contact 24 of the second device 2 is disposed in the metal region of the second device 2 at a position where the line G-G passes, the second device 2 collects current along an arrow 12 indicating current flow, but the first device 1 collects current through metal contacts 14 of first source regions 12 on either side of the line G-G, as indicated by an arrow II indicating current flow.
[0062] Fig. 13 is a cross-sectional view of the line H-H of Fig. 10. Referring back to Fig. 10, the line H-H is completely within the the first device 1 and spans three trenches 13, and the line H-H spans two source metal contacts 14. Referring to Fig. 13, the uppermost layer is filled with metal materials 11 of the first device 1. An oxide layer 10 is provided below the metal layer. There are three trenches 13 in the body part below the oxide layer 10. There is no source metal contact between the leftmost trench 13 and the intermediate trench 13. Furthermore, since the line H-H spans two source metal contacts 14, two source metal contacts 14 are shown accordingly in this cross-sectional view. Through the two source metal contacts 14, current between the trenches is collected along arrows II indicating current flow, respectively.
[0063] Fig. 14 shows a cross-sectional view of a part 1001 in Fig. 10. Referring back to Fig. 10, the part 1001 is within the second device 2, spans one trench 23, and one end is located on a source metal contact 24. Referring to Fig. 14, the uppermost layer is filled with metal materials 21 of the second device 2. In the middle portion, since the source region 22 of the second device 2 spans one trench 23, one trench 23 is shown here in the cross-sectional view. From the middle to the right, since one end of the part 1001 is located on a source metal contact 24, the metal contact 24 is shown in the cross-section view, and the metal contact 24 collects current along an arrow 12 indicating current flow.
[0064] Also, it should be noted that in the power device according to embodiments of the present disclosure, all regions except trenches in body parts of the first device and the second device are active regions. That is, in addition to the active regions of the second device 2 and the first device 1 themselves, there is no additional high concentration of diffusion (i.e. source regions are not removed) in a portion where the second device 2 is embedded with the first device 1 (including a part of the metal spacing region separating source regions of the second device 2 and source regions of the first device 1, and a part of source regions of the first device 1 under metal materials of the second device 2 (the metal materials of the second device 2 above this part function as a source lead-out line of the second device 2). As such, embedding of the second device 2 is smooth and does not cause structural changes to the first device 1, and thus does not adversely affect current-voltage performance of the first device 1. In addition, since source regions are not removed in the area where the second device is embedded in the first device, this portion can still contribute to current supply, so that there is no waste of any chip area.
[0065] The structure of the power device according to the present disclosure has been described above by way of embodiments. It should be understood that the number of source regions and trenches may be the same or different than the described embodiments. It should also be noted that the structure of the second device and the first device in the left half and the right half of the figure are the same, so the description about the left half also applies to the corresponding structure of the right half, vice versa.
[0066] The present disclosure also provides a method of manufacturing a power device. Fig. 15 illustrates a method 1500 for manufacturing a power device in accordance with an example embodiment of the present disclosure. As shown in Fig. 15, the method 1500 include: S1501, providing a substrate. Next, in step S1502, a body part of the first device and a body part of at least one second device are formed on the substrate. In step S1503, a plurality of first trenches for the first device are formed in the body part of the first device and a plurality of second trenches for the second device are formed in the body part of the second device, wherein each second trench of the second device is in connection with a corresponding first trench of the first device. Finally, in step S1504, a plurality of first source regions for the first device and a plurality of second source regions for the second device are formed, wherein the plurality of first source regions are electrically isolated from each other by the plurality of first trenches, and the plurality of second source regions are electrically isolated from each other by the plurality of second trenches, and wherein the second source regions of the second device and the first source regions of the first device are electrically isolated by a metal spacing region, and wherein all regions except the trenches in the body parts of the first device and the second device are active regions.
[0067] In an example, the plurality of second source regions of the second device may be arranged centrally.
[0068] In an example, the first device and the second device are formed on a P+N substrate, and the power device is an insulated gate bipolar transistor. In an example, the first device and the second device are formed on an N+N substrate, and the power device is a metal oxide semiconductor field effect transistor.
[0069] In an example, each second source region of the second device corresponds to a corresponding first source region of the first device, and each second trench of the second device is in direct connection with a corresponding first trench of the first device. The method 1500 may further include: forming a plurality of third trenches in the metal spacing region, wherein each third trench corresponds to a corresponding second source region of the second device and connects two second trenches corresponding to the second source region. The first trench, the second trench, and the third trench may be structurally identical. Alternatively, the first source region of the first device has a first metal contact region and the second source region of the second device has a second metal contact region, wherein boundary of each first metal contact region is at a distance from boundary of a corresponding second metal contact region such that current does not flow laterally along a plane any longer.
[0070] In an example, each second source region of the second device corresponds to two first source regions of the first device, and the method further comprises forming a plurality of fourth trenches in the metal spacing region, each of which having a three-terminal shape, corresponding to a corresponding second source region of the second device, and connecting two second trenches corresponding to the second source region with a trench between two first source regions corresponding to the second source region. The first trench, the second trench, and the fourth trench may be structurally identical.
[0071] As described above, the power device and method for manufacturing the power device according to the present disclosure have been described by way of specific embodiments. According to techniques of the present disclosure, the first device and the second device are simultaneously fabricated by a same process on a same substrate, wherein the first device and the second device are well electrically isolated. Furthermore, the first device and the second device are coupled and isolated in a unique manner, and since there is no additional high concentration of diffusion region (i.e., source regions are not removed) in an area where the second device is embedded in the first device, embedding of the second device is smooth and does not cause structural changes to the first device, and thus does not adversely affect current-voltage performance of the first device. In addition, since source regions are not removed in the area where the second device is embedded in the first device, this portion can still contribute to current supply, so that there is no waste of any chip area [0072] While at least one exemplary embodiment and manufacture method have been presented in the foregoing detailed description of the invention, it should be appreciated that there are still a large number of alternations. It also should be understood that one or more exemplary embodiments are provided as examples, and are not intended to limit scope, application and structure of the present invention in any way. The forgoing description provide for those skilled in the art a route map for conveniently practicing exemplary embodiments of the present disclosure. It should be understood that various changes of functions and arrangements of elements of the exemplary embodiments can be made without departing the scope of the invention as set forth in the appended claims and their legal equivalents.

Claims (20)

CLAIMS:
1. A power device, comprising:
a first device having a plurality of first source regions and a plurality of first trenches, the plurality of first source regions being electrically isolated from each other by the plurality of first trenches;
at least one second device having a plurality of second source regions and a plurality of second trenches, the plurality of second source regions being electrically isolated from each other by the plurality of second trenches, wherein the second device is embedded in the first device, each second trench of the second device is in connection with a corresponding first trench of the first device, and the second source regions of the first device are electrically isolated from the first source regions of the first device by a metal spacing region, and wherein all regions except trenches in body parts of the first device and the second device are active regions.
2. The power device according to claim 1, wherein the plurality of second source regions of the second device are arranged centrally.
3. The power device according to claim 1, wherein the first device and the second device are formed on a P+N substrate, and the power device is an insulated gate bipolar transistor.
4. The power device according to claim 1, wherein the first device and the second device are formed on an N+N substrate, and the power device is a metal oxide semiconductor field effect transistor.
5. The power device according to claim 2, wherein each second source region of the second device corresponds to a corresponding first source region of the first device, and each second trench of the second device is in direct connection with a corresponding first trench of the first device.
6. The power device according to claim 5, wherein the power device further comprises a plurality of third trenches, wherein the third trench is located in the metal spacing region, and each third trench corresponds to a corresponding second source region of the second device and connects two second trenches corresponding to the second source region.
7. The power device according to claim 6, wherein the first trench, the second trench, and the third trench are structurally identical.
8. The power device according to claim 5, wherein the first source region of the first device has a first metal contact region and the second source region of the second device has a second metal contact region, wherein boundary of each first metal contact region is at a distance from boundary of a corresponding second metal contact region such that current does not flow laterally along a plane any longer.
9. The power device according to claim 2, wherein each second source region of the second device corresponds to two first source regions of the first device, and the power device further comprises a plurality of fourth trenches, each of which having a three-terminal shape, corresponding to a corresponding second source region of the second device, and connecting two second trenches corresponding to the second source region with a trench between two first source regions corresponding to the second source region.
10. The power device of claim 9, wherein the first trench, the second trench, and the fourth trench are structurally identical.
11. A method for manufacturing a power device, comprising: providing a substrate;
forming a body part of the first device and a body part of at least one second device on the substrate;
forming a plurality of first trenches for the first device in the body part of the first device and forming a plurality of second trenches for the second device in the body part of the second device, wherein each second trench of the second device is in connection with a corresponding first trench of the first device; and forming a plurality of first source regions for the first device and a plurality of second source regions for the second device, wherein the plurality of first source regions are electrically isolated from each other by the plurality of first trenches, and the plurality of second source regions are electrically isolated from each other by the plurality of second trenches, and wherein the second source regions of the second device and the first source regions of the first device are electrically isolated by a metal spacing region, wherein all regions except the trenches in the body parts of the first device and the second device are active regions.
12. The method of manufacturing a power device according to claim 11, wherein the plurality of second source regions of the second device are arranged centrally.
13. The method of manufacturing a power device according to claim 11, wherein the first device and the second device are formed on a P+N substrate, and the power device is an insulated gate bipolar transistor.
14. The method of manufacturing a power device according to claim 11, wherein the first device and the second device are formed on an N+N substrate, and the power device is a metal oxide semiconductor field effect transistor.
15. The method of manufacturing a power device according to claim 12, wherein each second source region of the second device corresponds to a corresponding first source region of the first device, and each second trench of the second device is in direct connection with a corresponding first trench of the first device.
16. The method of manufacturing a power device according to claim 15, wherein the method further comprises forming a plurality of third trenches in the metal spacing region, wherein each third trench corresponds to a corresponding second source region of the second device and connects two second trenches corresponding to the second source region.
17. The method of manufacturing a power device according to claim 16, the first trench, the second trench, and the third trench are structurally identical.
18. The method of manufacturing a power device according to claim 15, wherein the first source region of the first device has a first metal contact region and the second source region of the second device has a second metal contact region, wherein boundary of each first metal contact region is at a distance from boundary of a corresponding second metal contact region such that current does not flow laterally along a plane any longer.
19. The method of manufacturing a power device according to claim 12, wherein each second source region of the second device corresponds to two first source regions of the first device, and the method further comprises forming a plurality of fourth trenches in the metal spacing region, each of which having a three-terminal shape, corresponding to a corresponding second source region of the second device, and connecting two second trenches corresponding to the second source region with a trench between two first source regions corresponding to the second source region.
20. The method of manufacturing a power device according to claim 19, wherein the first trench, the second trench, and the fourth trench are structurally identical.
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