GB2554744A - Control panel for a security alarm system - Google Patents
Control panel for a security alarm system Download PDFInfo
- Publication number
- GB2554744A GB2554744A GB1617113.4A GB201617113A GB2554744A GB 2554744 A GB2554744 A GB 2554744A GB 201617113 A GB201617113 A GB 201617113A GB 2554744 A GB2554744 A GB 2554744A
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- Prior art keywords
- control panel
- peripheral devices
- peripheral device
- data rate
- processor
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- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B26/00—Alarm systems in which substations are interrogated in succession by a central station
- G08B26/006—Alarm systems in which substations are interrogated in succession by a central station with substations connected to an individual line, e.g. star configuration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W28/00—Network traffic management; Network resource management
- H04W28/16—Central resource management; Negotiation of resources or communication parameters, e.g. negotiating bandwidth or QoS [Quality of Service]
- H04W28/18—Negotiating wireless communication parameters
- H04W28/22—Negotiating communication rate
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- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B25/00—Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems
- G08B25/14—Central alarm receiver or annunciator arrangements
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- Engineering & Computer Science (AREA)
- Business, Economics & Management (AREA)
- Emergency Management (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Communication Control (AREA)
Abstract
A security alarm system 1 comprises an alarm control panel 2 connected to a network of primary peripheral devices 3 via cables 4. Secondary peripheral devices 5 are connected to the primary peripheral devices 3 via a link 6 which can be a multicore cable or wireless link. The primary peripheral devices 3 can be keypads, expanders or bell boxes. The secondary peripheral devices 5 can be sensors such as motion detectors, shock detectors or contact breakers. (Figure 2 not shown) the control panel 2 contains a processor (10) and network interface (14) where the processor is configured to determine a data rate for transmitting to and receiving from primary peripheral devices 3. The data rate can be determined by measuring a response time of the primary peripheral device 3 via sending a signal from the control panel 2 to the primary peripheral device 3 and receiving a reply. Different data rates can be used for different peripheral devices.
Description
(54) Title of the Invention: Control panel for a security alarm system
Abstract Title: An alarm control panel having a processor to determine data rates for communication between the control panel and peripheral devices (57) A security alarm system 1 comprises an alarm control panel 2 connected to a network of primary peripheral devices 3 via cables 4. Secondary peripheral devices 5 are connected to the primary peripheral devices 3 via a link 6 which can be a multicore cable or wireless link. The primary peripheral devices 3 can be keypads, expanders or bell boxes. The secondary peripheral devices 5 can be sensors such as motion detectors, shock detectors or contact breakers. (Figure 2 not shown) the control panel 2 contains a processor (10) and network interface (14) where the processor is configured to determine a data rate for transmitting to and receiving from primary peripheral devices 3. The data rate can be determined by measuring a response time of the primary peripheral device 3 via sending a signal from the control panel 2 to the primary peripheral device 3 and receiving a reply. Different data rates can be used for different peripheral devices.
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Chose a first, minimum data rate and a second, maximum data rate
For each primary peripheral device, store the highest test data rate value which was successfully received
Fig. 4
Control panel for a security alarm system
The present invention relates to the field of security alarm systems. In particular, the present invention relates to a control panel for connection to a security alarm system, and an associated method.
A typical security alarm system comprises a control panel and a plurality of peripheral devices. The control panel and peripheral devices may be interconnected so as to form a network. Each of the peripheral devices on the network is provided with a unique address so as to enable communication between the control panel and each peripheral device.
It is desirable for the data rate for communications between the control panel and the peripheral devices to be maximised whilst ensuring that the data is not corrupted. This may reduce a response time of the system.
It may be desirable to provide an alternative control panel for a security alarm, and associated method, which at least partially addresses one or more of the problems of the prior art, whether identified herein or elsewhere.
According to a first aspect of the invention there is a provided a control panel for connection to a security alarm system network, the control panel comprising: a processor; and a network interface, the processor being operable to control the network interface so as to generate and transmit data to one or more peripheral devices across a network and to receive data and from the one or more peripheral devices across the network; wherein the processor is operable to determine a data rate for transmission to at least one of the one or more peripheral devices and is further operable to use said data rate when generating and transmitting data to, or receiveing data from, that peripheral device.
The first aspect of the invention allows for a suitable data rate to be determined for exchange of data between the control panel and a peripheral device across a network. It provides a particularly advantageous arrangement since it allows for different data rates to be used for communication with different peripheral devices. Furthermore, it allows the data rate for communication with a given peripheral device to be determined more than once. For example, the data rate may be determined periodically or in response to a request or reported error.
Such a flexible control panel that provides for the determination of the data rate for exchange of data between a control panel and one or more peripheral devices is beneficial as security alarm systems become more advanced and sophisticated there is a need to pass more and more information between devices connected to the control panel via a network.
The first aspect of the invention can be used to optimise the responsiveness of a security alarm system that the control panel forms part of.
The processor may be operable to determine a separate data rate for each of a plurality of peripheral devices connected to the control panel. This allows, for example, lower data rates to be used for peripheral devices that are separated from the control panel by a relatively long distance, so as to ensure that the data exchanged with such devices is not compromised, without slowing down the entire network.
The control panel may further comprise a memory. The processor may be operable to store one or more data rates determined by the processor in the memory.
When the processor is using the network interface to communicate simultaneously with a plurality of different peripheral devices, the processor may be operable to control the network interface so as to communicate with the peripheral devices at the lowest determined data rate for those peripheral devices.
In order to determine a data rate for transmission to a peripheral device the processor may be operable to determine a response time for communication with that peripheral device.
The response time may be determined as the elapsed time between sending a signal from the control panel to the peripheral device and the control panel receiving a reply from the peripheral device.
The determined data rate for communication with a peripheral device may be dependent on an inverse of a previously determined response time for that peripheral device.
The processor may be arranged to determine a data rate for transmission of a data packet to or from at least one of the one or more peripheral devices based on a response time for a previously sent data packet.
The processor may be operable to determine a first, minimum data rate and a second, maximum data rate. It will be appreciated that the first and second data rates may be stored in memory and the processor may be operable to read the first and second data rates from memory.
The first, minimum data rate may be chosen to be a minimum data rate that an operator or designer of the security alarm system is willing to tolerate. The minimum rate may be chosen so as to allow reliable communication between the control panel and a peripheral device over a maximum expected distance of a certain specification of cable. The second, maximum data rate may be chosen to be a desired maximum data rate that an operator or designer of the security alarm system wishes to achieve.
In order to determine a data rate for transmission to a peripheral device the processor may be operable to successively send a plurality of signals to the peripheral device at different data rates and determine whether or not the signals have been successfully received by the peripheral device. The signals may be referred to as “device present” commands. The data rates of the plurality of signals may range from the first data rate to the second data rate.
The processor may be operable to determine the data rate for transmission to the peripheral device as the data rate of the signal with the highest data rate that was successfully received by the peripheral device.
The processor may be arranged to determine a data rate for transmission to at least one of the one or more peripheral devices upon power up. That is, once the control panel is connected to a power supply.
Additionally or alternatively, the processor may be arranged to determine a data rate for transmission to at least one of the one or more peripheral devices in response to a network error. The network errors may include: one or more peripheral devices being unresponsive for a specified time period; or an increase in a packet error rate from one or more peripheral devices.
According to a second aspect of the invention there is provided a security alarm system comprising: the control panel according to the first aspect of the invention; and one or more peripheral devices, wherein the control panel and the or each peripheral devices are connected to so as to form a network.
Various aspects and features of the invention set out above or below may be combined with various other aspects and features of the invention as will be readily apparent to the skilled person.
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:
Figure 1 is a schematic illustration of a security alarm system comprising a device according to an embodiment of the invention;
Figure 2 is a schematic illustration of a control panel that forms part of the security alarm system shown in Figure 1;
Figure 3 is a schematic illustration of a primary peripheral device that forms part of the security alarm system shown in Figure 1; and
Figure 4 is a flow diagram representative of a method implemented by the control panel of Figure 2.
Figure 1 shows, schematically, a security alarm system 1, which comprises a network. The security alarm system 1 comprises a control panel 2, a plurality of primary peripheral devices 3 and a plurality of secondary peripheral devices 5.
Each of the primary peripheral devices 3 is connected, either directly or indirectly, to the control panel 2. In the example shown in Figure 1, this is achieved via cables 4. The cables are arranged so as to form four branches extending away from the control panel 2. Each cable branch extends from the control panel 2 to one or more primary peripheral devices 3 in series. The four cable 4 branches are connected within the control panel 2 and may be considered to form a network bus.
The control panel 2, the cables 4 and the primary peripheral devices 3 may be considered to form a network. The primary peripheral devices 3 may be referred to as networked devices.
Each of the cables 4 comprises a multicore cable. For example, the cables 4 may comprise a four core alarm cable. Two of the cores may be used to transmit power across the network and two of the cores may be used to send signals across the network. The cable 4 branches may therefore be considered to form a four wire network bus.
The two cores used to transmit power across the network may comprise a ground core which is held at ground (i.e. 0 V) and a positive core which is held at a voltage, for example 12 V. In an embodiment, the two cores used for exchange of signals may comprise a clock line and a data line. The clock line may be transmission of a clock signal and the data line may be transmission of a data signal. The clock line and data line may, for example, each be signal lines, which may each be connected to the positive core by a pull up resistor and to the ground core by one or more switches.
It will be appreciated that within the security alarm system 1, the control panel 2 has unidirectional control over the primary peripheral devices 3. That is, communication proceeds on a master/slave basis, with the control panel 2 being the master and the primary peripheral devices 3 being slaves. Therefore, the primary peripheral devices 3 will typically only send data to the control panel 2 in response to a request for said data from the control panel 2. The synchronisation during communication between the control panel 2 and the primary peripheral device 3 is achieved using a clock signal that is generated by the control panel 2 (and transmitted on the clock line).
When the control panel 2 is sending data to a primary peripheral device 3, the control panel 2 may send a clock signal on the clock line and a data signal on the data line. The clock signal and data signal are synchronised. Typically, each bit of data is transmitted for the duration of a clock signal period. Therefore, the frequency of the data signal is typically half that of the clock signal. The primary peripheral device 3 can use the clock signal to interpret the data signal. For example, each time a transition (for example a rising edge) is detected in the clock signal by the primary peripheral device 3, the primary peripheral device 3 may sample the data signal to read the next bit of data.
During transmission of data from a primary peripheral device 3 to the control panel 2 (in response to a request from the control panel 2), the control panel 2 will generate and send the clock signal on the clock line and will read data from the data line. The primary peripheral device 3 will send the data on the data line at half the frequency of, and synchronised with, the clock signal. For example, the primary peripheral device 3 may store the data in a register or buffer and may be operable to transmit a single bit for each cycle of the clock signal that it receives. For example each time the primary peripheral device 3 may be operable to transmit a single bit on the data line every time a transition (for example a rising edge) is detected in the clock signal by the primary peripheral device 3.
Therefore, by controlling the frequency of the clock signal, the control panel 2 can control the data rate of communication being sent to, or received from, a given primary peripheral device 3.
Each of the primary peripheral devices 3 may be connected to one or more of the secondary peripheral devices 5. Each of the secondary peripheral devices 5 is connected to one of the primary peripheral devices 3 via a link 6. The links 6 may be physical, for example comprising a multicore cable, or wireless. On one embodiment, the links 6 comprise six core alarm cable. Two of the cores may be used to transmit power from the primary peripheral device 3 to the secondary peripheral device 5 and the remaining four cores may be used to communicate information from the primary peripheral device 3 to the secondary peripheral device 5. For example, two cores may be user to communicate alarm status information relating to the secondary peripheral device 5 and two of the cores may be used to communicate tamper status information relating to the secondary peripheral device 5.
Since the primary peripheral devices 3 and the control panel 2 are connected so as to form a network, the control panel 2 can communicate directly with the primary peripheral devices 3. In order for the control panel 2 to be able to communicate with each primary peripheral device 3 individually, each of the primary peripheral devices 3 is provided with a unique address.
Information from the secondary peripheral devices 5 is relayed back to the control panel 2 via the primary peripheral devices 3 to which they are connected.
The primary peripheral devices 3 may typically comprise keypads, expanders (also known in the art as zone expanders) and/or bell boxes. The secondary peripheral devices may typically comprise detectors such as, for example, motion detectors, shock detectors and contact breakers. However, it will be appreciated that any component of a security alarm system 1 may be connected to the control panel 2 as a primary peripheral device 3 so as to form part of the network.
Embodiments of the present invention relate to the data rate for exchange of data between the control panel 2 and the primary peripheral devices 3. As security alarm systems become more advanced and sophisticated there is a need to pass more and more information between devices connected to the control panel network, i.e. the primary peripheral devices 3.
Keypads are an example of a type of primary peripheral device 3 which exchanges information with the control panel 2 over the network. Keypads generally provide a user interface for the control panels 2 of security alarm systems and most security alarm systems will comprise at least one keypad. Such keypads typically comprise a user interface that allows a user to input signals and a display screen or the like, both of which are accessible from an exterior of a housing of the keypad. For example, the keypad may comprise a touchscreen which provides both the functionality of a user interface and a display screen. Alternatively, the keypad may comprise an array of buttons (also referred to as the keypad) and a separate display screen.
Keypads may be used by users to monitor and/or alter various settings or parameters of a security alarm system 1. A user of the security alarm system can use the user interface of the keypad to access information, for example by navigating through menus or the like. As a user uses the user interface, for example by pressing buttons on a keypad, information displayed on the display screen will be updated. However, the information being displayed is not typically stored locally within the keypad. Rather, the information is more typically stored in the control panel 2. As a button is pressed by a user, a signal is sent from the keypad to the control panel 2 via the network. Upon receipt of such a signal, the control panel 2 generates a signal which is sent back over the network to the keypad, instructing the keypad how the display screen should be updated. The response time, i.e. the time taken from the button being pressed to the display screen being updated, is dependent on the rate at which the keypad and the control panel 2 can exchange data over the network, as well as the typical volume of traffic over the network. For example, the control panel 2 is typically communicating with each primary peripheral device 3 that is connected to the network and therefore as the number of primary peripheral devices 3 connected to the network increases the, the fraction of time available for communication with any one primary peripheral device 3 may decrease.
It will be appreciated that communication over the network will be achieved by sending and receiving binary signals. Each binary signal may be sent over the network using any suitable line code. That is, the binary signal may be encoded by a device (either the control panel 2 or a primary peripheral device 3) that is transmitting the signal, sent across the network as the line code and then decoded back into binary code by a device that is receiving the signal (either a primary peripheral device 3 or the control panel 2). It will be appreciated by the skilled person that any line code may be used for this purpose as desired or required. Irrespective of the line code used, the signal transmitted across the network (i.e. via cables 4) will in general comprise a plurality of pulses. The data speed may dictate the temporal extent of such pulses. In particular, the data rate or data speed R may be proportional to the inverse of the temporal extent of the pulses.
For embodiments wherein the cables 4 comprise a clock line and a data line, the data speed or data rate may be half the frequency of a clock signal (for example a square wave signal) on the clock line.
To keep the system responsive, there is an increasing demand for network speeds to increase to allow for the increased volume of data between the control panel 2 and the primary peripheral devices 3. However, the maximum rate at which data can be sent over the network before the data becomes corrupted is dependent on the physical characteristics of the cables 4. In particular, it can be dependent on the total capacitance and resistance of the cables, which in turn is dependent on the type of cable and the total length of cable between the control panel 2 and the primary peripheral devices 3. For a given specification of cable and data rate, there is a limit to the total length of cable 4 that can separate the control panel 2 and any primary peripheral devices 3.
In general, the line shape of the pulses contained in the signal may be distorted by the non-zero resistance and capacitance of the cable over which it is sent. For example, a top hat shaped pulse may be distorted such that it becomes generally saw tooth shaped. That is, the sharp vertical edges of the pulses are spread out over non-zero time period. This distortion of the pulses is dependent on the frequency or data rate of the signal. Generally, as the data rate increases the amount of distortion of the signal increases.
If data is sent over the network at a speed above a maximum speed dictated by the properties of the cable, the line shape of the pulses contained in the signal may be distorted to such an extent that control electronics that receive the signal (either in the primary peripheral device 3 or the control panel 2) can no longer interpret the signal. For example, the control electronics may no longer be able to detect the edges of the pulses contained in the signal.
Additionally or alternatively, unless the receiving device (for example the control panel 2 or the primary peripheral device 3) is able to buffer or store data in memory then if data is sent over the network at a speed above a maximum response speed, then the receiving device may not be able to correctly interpret the data. The maximum response speed may be the inverse of a minimum response time for communication between the control panel 2 and a primary peripheral device 3. The minimum response time for communication between the control panel 2 and a primary peripheral device 3 may be the minimum time taken to communicate a single bit of data from the primary peripheral device 3 to the control panel 2. If, for example, the time taken for a bit of data from the primary peripheral device 3 to the control panel 2 was greater than the time period of the clock signal then upon request of a bit of data from the control panel 2 in a given clock signal period, the response would be received in a subsequent clock signal period. If the control panel 2 cannot buffer or store data in memory then the received signal will be out or sync with the requests from the control panel 2. As a result, the control panel 2 would not be able to correctly interpret the data.
Note that the distortion caused by the non-zero capacitance of the cable 4 over which the signals are sent causes the sharp vertical edges of the pulses to be spread out over non-zero time period. Therefore, this distortion of the pulses contributes to the minimum response time between two devices (i.e. the control panel 2 and the primary peripheral devices 3).
Historically, for large installations, the problem of high distortion over large distances of cable may be overcome by using a higher quality cable that has a lower resistance and capacitance, or with the use of additional devices to boost the signals, or more advanced driver circuitry in all network devices. However, all of these options add considerable cost to the system installation.
A control panel 2 according to an embodiment of the invention is operable to determine a data rate for a primary peripheral device 3 to which it is connected, is now described with reference to Figure 2.
Figure 2 is a schematic illustration of the control panel 2. The control panel 2 comprises: a processor 10, memory 12 and a network interface 14.
The processor 10 may for example comprise any combination of analogue or digital electronics. In one embodiment the processor comprises a micro-processor.
Optionally, in some embodiments the control panel 2 may comprise in input/output (I/O) interface 16 in the form of an input device (for example a keypad) and a display device or the like. This may provide a user interface for the control panel 2. Alternatively, in other embodiments, a user interface may be provided by one of the primary peripheral devices 3, which may, for example, be a keypad.
The memory 12 may comprise both random access memory (RAM) 18 and non-volatile storage 20. The non-volatile storage 20 may be of any form such as, for example, of the form of read only memory, flash memory, or a hard disc drive. The processor 10 is arranged to write to and read from the memory 12.
The network interface 14 allows the control panel 2 to be connected to the network so as to receive and transmit data from and to the primary peripheral devices 3. The network interface 14 may comprise suitable control electronics for transmitting signals to, and receiving signals from, the cables 4. The processor 10 may be operable to control the network interface 14 so as to generate a clock signal on a clock line and a data signal on a data line. The frequency of the clock signal may determine the data rate for exchange of information with a primary peripheral device 3 which the control panel 2 is communicating with. The clock signal may be a square wave signal.
The memory 10, RAM 18, non-volatile storage 20, network interface 14 and I/O interface 16 are connected together by a bus 22. It will be appreciated that the control panel 2 shown in Figure 2 could be provided by a system on chip such that any or all of the components shown in Figure 2 are provided by a single chip. For example, in one embodiment, at least the processor 10 and memory 12 are both provided by a microcontroller.
Figure 3 is a schematic illustration of a primary peripheral device 3 according to an embodiment of the invention, which is suitable for connection to a security alarm system network. Each of the primary peripheral devices 3 of the security alarm system 1 shown in Figure 1 may comprise the primary peripheral device 3.
The primary peripheral device 3 comprises: a processor 24, a network interface 26 and a memory 28. The memory 28 may comprise non-volatile memory. The processor 24 is arranged to write to and read from the memory 28. In one embodiment, the processor 24 and memory 28 are both provided by a micro-controller.
The processor 24 is operable to send signals to and receive signals from the primary peripheral device 3 via the network interface 26. The network interface 26 may comprise suitable control electronics for transmitting signals to, and receiving signals from, the cables 4. The network interface 26 comprises two connectors 26a, 26b for connection to multi-core network cables 4. The two connectors 26a, 26b each comprise terminal blocks for each of four wires of a multi-core network cable 4. As shown in Figure 1, in general, a plurality of primary peripheral devices 3 is provided in series on each branch of the network formed by the cables 4. A first one of the connectors 26a may be used to connect the device to the control panel 2 or, alternatively, to a previous primary peripheral device 3 on the branch (i.e. a primary peripheral device 3 that is closer to the control panel 2). A second one of the connectors 26b may be used to connect the primary peripheral device 3 to a next primary peripheral device 3 on the branch (i.e. a primary peripheral device 3 that is farther away from the control panel 2). It will be appreciated that if the primary peripheral device 3 is the last primary peripheral device 3 on the branch then the second connector 26b may not be used.
Although in the embodiment shown in Figure 3 the network interface 26 comprises two connectors 26a, 26b for connection to multi-core network cables 4, it will be appreciated that in alternative embodiments, the network interface 26 may only comprise one connector for connection to multi-core network cables 4. Embodiments of primary peripheral devices 3 that only have a single connector for network cables 4 can be “daisy chained” together by connecting both of the network cables 4 (form the previous device and the next device) into the same connector, i.e. such that corresponding cores from each of the two cables terminate in the same terminal blocks. When wired this way the primary peripheral devices 3 are effectively connected in parallel. This saves some printed circuit board (PCB) space and cost. An advantage of having two connectors 26a, 26b (as shown in Figure 3) is that the second connector 26b (which is used to connect the primary peripheral device 3 to a next primary peripheral device 3 on the branch) can be isolated from the first connector 26a (which is used to connect the primary peripheral device 3 to the control panel 2 or a previous primary peripheral device 3 on the branch). This means that if there is a short circuit on the network at a point on a branch after a primary peripheral device 3 (i.e. a point on the branch that is farther away from the control panel 2), the primary peripheral device 3, and all networked devices that are closer to the control panel 2, can continue to operate normally. This is in contrast to primary peripheral devices 3 that only have one set of network terminals, wherein if there is a short circuit then the whole of that part of the network stops working.
In an embodiment, the control panel 2 is operable to determine a suitable data rate for at least one primary peripheral device 3 to which it is connected. The control panel 2 may be further operable to store the determined data rate for the primary peripheral device(s) 3 in the memory 12 (for example in non-volatile storage 20).
The control panel 2 is further operable to communicate with at least one primary peripheral device 3 using the determined data rate for that primary peripheral device 3. In this way, the control panel 2 is operable to use, in general, a different data rate for each primary peripheral device 3 connected to the network. In the event that the control panel 2 is communicating simultaneously with a plurality of different primary peripheral devices 3 (for example during a broadcast communication to all devices on the network), the control panel 2 is operable to communicate with each primary peripheral device 3 at the lowest determined data rate for the plurality of primary peripheral devices 3 to which the control panel 2 is connected.
The processor 10 is operable to generate and transmit data to and from the primary peripheral devices 3 across the network of the security alarm system 1. The processor 10 is further operable to determine a data rate for transmission to each of the primary peripheral devices 3 and is further operable to use said data rate when generating and transmitting data to that primary peripheral device 3.
The control panel 2 therefore allows for a suitable data rate to be determined for exchange of data between the control panel 2 and a primary peripheral device 3 across a network. It provides a particularly advantageous arrangement since it allows for different data rates to be used for communication with different primary peripheral devices 3. Furthermore, it allows the data rate for communication with a given primary peripheral device 3 to be determined more than once. For example, the data rate may be determined periodically or in response to a request or reported error.
Such a flexible control panel 2 that provides for the determination of the data rate for exchange of data between the control panel 2 and the primary peripheral devices 3 is beneficial because as security alarm systems become more advanced and sophisticated there is a need to pass more and more information between devices 3 connected to the control panel 2 via a network.
In an embodiment, the processor 10 is operable to determine a separate data rate for each of the primary peripheral devices 3 connected to the control panel 2. This allows, for example, lower data rates to be used for primary peripheral devices 3 that are separated from the control panel 2 by a relatively long distance of cable, so as to ensure that the data exchanged with such devices is not compromised, without slowing down the entire network. For example, the security alarm system may comprise a plurality of primary peripheral devices 3 that are connected to the control panel 2 by a relatively short length of cable 4 (for example 200 m or less) and a single primary peripheral device 3 that is connected to the control panel 2 by a relatively long length of cable 4 (for example of the order of 1 km). Under these circumstances, a lower data rate may be used for communication with the primary peripheral device 3 that is 1 km from the control panel 2 whereas communication with the other primary peripheral device 3 may proceed at the highest data rate of the system.
The processor 10 is operable to store the determined data rates in the memory 12 (for example in the non-volatile storage 20).
When the processor 10 is communicating simultaneously with a plurality of different primary peripheral devices 3, the processor 10 is operable to communicate with the primary peripheral devices 3 at the lowest determined data rate for those primary peripheral devices 3.
Two different embodiments for determine a data rate for transmission to and/or from a primary peripheral device 3 are now described.
According to a first embodiment of the invention, in order to determine a data rate for transmission to and/or from a primary peripheral device 3, the processor 10 may be operable to determine a response time for communication with that primary peripheral device 3.
The response time may be determined as the elapsed time between sending a signal from the control panel 2 to the primary peripheral device 3 and the control panel 2 receiving a reply from the primary peripheral device 3. For example, the processor 10 may be operable to start a timer as the signal is sent from the control panel 2 to the primary peripheral device 3 and to stop the timer when the reply from the primary peripheral device 3 is received.
This response time is a measure of the time taken for a signal to propagate from the control panel 2 to the primary peripheral device 3 and back again. There are various different factors which contribute to the response time. For example, the response time is dependent on the distance between the primary peripheral device 3 and the control panel 2, since the signal propagates at a finite speed. The response time is further dependent on the total capacitance of the line separating the primary peripheral device 3 and the control panel 2, which, in turn, is dependent on the distance between the primary peripheral device 3 and the control panel 2 (i.e. the total length of cable). This is because the greater the capacitance the greater the time period over which each transition from high to low is spread in the signal (and therefore the longer it takes for each device to register that the transition has occurred). The response time is further dependent on the number of intermediate devices that the signal propagates through. For example, each time a signal propagates through another primary peripheral device 3 and is relayed onto the next section of cable 4, there may be a delay. The response time is further dependent on the speed of any control electronics in the primary peripheral device 3 and any intermediate primary peripheral devices 3 via which the signal is sent.
As explained above, each of the cables 4 which connects the control panel 2 and primary peripheral devices 3 together comprises a multicore cable and may, for example, comprise a four core alarm cable. Two of the cores may be used to transmit power across the network and two of the cores may be used to send signals across the network. The two cores used for exchange of signals may comprise a clock line and a data line.
A typical exchange of information between the control panel 2 and a primary peripheral device 3 may involve a data packet being sent from the control panel 2 to the primary peripheral device 3 requesting some information and a reply packet of data containing the requested information being sent from the primary peripheral device 3 to the control panel 2. During such an exchange of information, the network interface 14 may generate a clock signal on the clock line for the duration of the exchange. The network interface 14 may be switchable from a sending state wherein it is operable to generate a data signal on the data line and a receive state wherein it is operable to receive data from the data line. A clock may be started when the network interface 14 transitions from the sending state to the receiving state. The clock may be stopped when the network interface 14 receives the data from the primary peripheral device 3. The time determined by the clock in this way may be the response time for that communication exchange.
The processor 10 is operable to control the clock signal such that, when the control panel 2 is communicating with a given primary peripheral device 3, the frequency of the clock signal is dependent on a previously determined response time for that primary peripheral device 3. In an embodiment, the frequency of the clock signal is dependent on an inverse of the previously determined response time for that primary peripheral device 3. For example, the frequency of the clock signal may be proportional to the inverse of the previously determined response time for that primary peripheral device 3 unless this would result in a frequency which exceeds a threshold frequency. If a determined frequency for the clock signal, which is proportional to the inverse of the previously determined response time for that primary peripheral device 3, exceeds a threshold frequency then the frequency of the clock signal may be set to the threshold frequency.
In practice communication with most primary peripheral devices 3 may proceed at the threshold frequency (which may be limited by the control electronics in the control panel 2 and primary peripheral devices 3). Only for communication with primary peripheral devices that are disposed far from the control panel 2 (i.e. which have large response times) will the data rate be reduced.
In an embodiment, each communication with a primary peripheral device 3 occurs at a data rate that is dependent on a response time determined during the previous communication with that primary peripheral device 3. A first communication with a primary peripheral device 3 may occur at a minimum data rate of so as to ensure that a response can be received from that primary peripheral device 3. The minimum data rate may be chosen so as to allow reliable communication between the control panel 2 and a primary peripheral device 3 over a maximum expected distance of a certain specification of cable 4. For example, the minimum data rate may be chosen to be sufficiently low that data send over the maximum expected distance of the specified type of cable will not be corrupted. For example, the minimum data rate may be chosen to be sufficiently low that data send over 1 km of standard 4 core alarm cable will not be corrupted. Standard 4 core alarm cable may, for example, have a typical resistance of around 100 Ω/km and a typical capacitance of around 45 nF/km.
According to a second embodiment of the invention, in order to determine a data rate for transmission to and/or from a primary peripheral device 3 the processor 10 is operable to successively send a plurality of signals to the primary peripheral device 3 at different data rates and determine whether or not the signals have been successfully received by the primary peripheral device 3. The signals may be referred to as “device present” commands. The data rates of the plurality of signals may range from a first data rate to a second data rate. The processor 10 may be operable to determine the data rate for transmission to the primary peripheral device 3 as data rate of the signals with the highest data rate that was successfully received by the primary peripheral device 3.
The processor 10 may be arranged to determine a data rate for transmission to the or each primary peripheral device 3 upon power up and/or in response to a network error and/or upon request (for example as requested by a user using a keypad connected to the network) and/or periodically.
A method implemented by the control panel 2 in accordance with this second embodiment for determining a data rate for transmission to and/or from a primary peripheral device 3 is now described with reference to Figure 4. At step 30, two different data rates are chosen: a first, minimum data rate and a second, maximum data rate. It will be appreciated that the two different data rates may be stored in memory 12 in the control panel 2 and step 30 may involve reading the first and second data rates from memory 12.
The first, minimum data rate may be chosen to be a minimum data rate that an operator or designer of the security alarm system 1 is willing to tolerate. That is, it may be chosen to be sufficiently high that the responsiveness of communications over the network will be at a tolerable although potentially sub-optimal level. The minimum rate may be chosen so as to allow reliable communication between the control panel 2 and a peripheral device over a maximum expected distance of a certain specification of cable 4. For example, the minimum data rate may be chosen to be sufficiently low that data send over the maximum expected distance of the specified type of cable will not be corrupted. For example, the minimum data rate may be chosen to be sufficiently low that data send over 1 km of standard 4 core alarm cable will not be corrupted.
Standard 4 core alarm cable may, for example, have a typical resistance of around 100 Ω/km and a typical capacitance of around 45 nF/km.
The second, maximum data rate may be chosen to be a desired maximum data rate that an operator or designer of the security alarm system 1 wishes to achieve. That is, it may be chosen to be sufficiently high that the responsiveness of communications over the network will be at an optimal level.
It will be appreciated that the first and second data rates may be selected or altered by a user of the system. This may be achieved, for example, using a keypad of the like to communicate over the network with the control panel 2.
At step 32 the control panel 2 sets a test broadcast rate equal to the first data rate. At step 34 the control panel 2 sends out a “device present” command over the network at the test data rate.
Upon successful receipt of such a device present command, each primary peripheral device 3 that is connected to the network is operable to send a response signal. At step 36, the control panel 2 determines which devices have successfully received the device present command.
At step 38 the control panel 2 compares the test data rate to the second data rate. If the test data rate is less than the second date rate then, at step 40, the test data rate is incremented and steps 34, 36 and 38 are repeated. If the test data rate is equal to or greater than the second date rate then, at step 42, for each primary peripheral device 3, the highest test data rate value which was successfully received is stored in memory 12.
During the loop formed by repeating steps 34, 36, 38 and 40 this device present command is repeated at a faster and faster data rate until the second or maximum data rate is reached. It will be appreciated that the increment in test data rate made at step 40 may be of any suitable size as desired or required. For example, at step 40 the test data rate may be incremented by a tenth of the difference between the second data rate and the first data rate. Such an arrangement provides eleven possible data rates for each of the primary peripheral devices.
The control panel 2 may be operable to implement the above-described method to determine a data rate for each primary peripheral device as and when required or desired. In some embodiments, the control panel 2 may be operable to implement the above-described method upon power up. That is, once the control panel 2 is connected to a power supply.
In addition, the control panel 2 may be operable to implement the above-described method in response to a network error such as, for example, one or more primary peripheral devices 3 are unresponsive or if packet error rates from one or more primary peripheral devices 3 increase. It will be appreciated that during normal operation of the network, from time to time primary peripheral devices 3 will fail to respond and data packets received from primary peripheral devices 3 will become corrupted. Therefore, it will be appreciated that the control panel 2 may be operable to implement the abovedescribed method to determine a data rate for each primary peripheral device 3 only once such errors have occurred more than would be reasonably expected or tolerated during normal operation of the network. Furthermore, it will be appreciated that the control panel 2 may be operable to implement the above-described method to determine a data rate only for a subset of the primary peripheral devices 3 which are affected by the network errors.
It will be appreciated that the processor 10 of the control panel 2 may be operable to perform any of the steps of the above-described method as appropriate.
The above-described control panel 2 is advantageous for a number of reasons, as now discussed.
For most security alarm systems the length of cable between each primary peripheral device 3 and the control panel 2 is fairly short, for example less than 200 m. At these lengths, the control panel 2 may be operable to communicate at the second data rate,
i.e. the maximum data rate. Only when the length of cable between a primary peripheral device 3 and the control panel 2 becomes greater, for example more than 500 m does the control panel 2 start to slow the data rate speed down. Note that the control panel 2 only operates at such lower data rates for the primary peripheral devices 3 that require it and primary peripheral devices 3 on the shorter cable lengths will still communicate with the control panel 2 at the full network speed (i.e. the second data rate).
As a result of the functionality that the control panel 2 is operable to adapt the data rate for each individual primary peripheral device, a responsive network is achievable even using standard low cost four core alarm cable (two cores for power and two cores for data) and relatively low cost driver circuitry (in the primary peripheral devices 3 and the control panel 2) even with relatively long cable lengths.
It will be appreciated that the security alarm system 1 illustrated in Figure 1 is a schematic representation of one of many possible configurations of a control panel 2, network cables 4, primary peripheral devices 3, secondary peripheral devices 5 and links 6. Other embodiments may comprise different numbers and combinations of network cables 4, primary peripheral devices 3, secondary peripheral devices 5 and links 6. In general the alarm system 1 will comprise one control panel 2. Although the embodiment shown in Figure 1 shows four branches of cables 4, in general the security alarm system 1 will comprise at least one branch of cables 4. Although the embodiment shown in Figure 1 shows eight primary peripheral devices 3 in general the security alarm system 1 will comprise at least two primary peripheral devices 3.
In some embodiments, the security alarm system 1 may not comprise any secondary peripheral devices 5. For example, all peripheral devices of the security alarm system 1 may be connected directly to the network via cables 4. Alternatively, in other embodiments, each primary peripheral device 3 may be connected to any number of secondary peripheral devices 5 as desired. In practice, the number of secondary peripheral devices 5 that can be connected to a primary peripheral device 3 may be limited in number by a number of physical ports of that primary peripheral device. For example the primary peripheral device 3 (which may for example be an expander) may have capacity to connect to up to eight or ten secondary peripheral devices 5 (which may each comprise a detector).
It will be appreciated that as used herein the terms data rate, data speed and data frequency may be synonymous and may mean the frequency of a data signal.
While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. The descriptions above are intended to be illustrative, not limiting. Thus it will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below.
Claims (14)
1. A control panel for connection to a security alarm system network, the control panel comprising:
a processor; and a network interface, the processor being operable to control the network interface so as to generate and transmit data to one or more peripheral devices across a network and to receive data and from the one or more peripheral devices across the network;
wherein the processor is operable to determine a data rate for transmission to at least one of the one or more peripheral devices and is further operable to use said data rate when generating and transmitting data to, or receiving data from, that peripheral device.
2. The control panel of claim 1 wherein the processor is operable to determine a separate data rate for each of a plurality of peripheral devices connected to the control panel.
3. The control panel of claim 1 or claim 2 further comprising a memory and wherein processor is operable to store one or more data rates determined by the processor in the memory.
4. The control panel of any preceding claim wherein when the processor is using the network interface to communicate simultaneously with a plurality of different peripheral devices, the processor is operable to control the network interface so as to communicate with the peripheral devices at the lowest determined data rate for those peripheral devices.
5. The control panel of any preceding claim wherein in order to determine a data rate for transmission to a peripheral device the processor is operable to determine a response time for communication with that peripheral device.
6. The control panel of claim 5 wherein the response time is determined as the elapsed time between sending a signal from the control panel to the peripheral device and the control panel receiving a reply from the peripheral device.
Ί. The control panel of claim 5 or claim 6 wherein the determined data rate for communication with a peripheral device is dependent on an inverse of a previously determined response time for that peripheral device.
8. The control panel of any one of claims 5 to 7 wherein the processor is arranged to determine a data rate for transmission of a data packet to or from at least one of the one or more peripheral devices based on a response time for a previously sent data packet.
9. The control panel of any one of claims 1 to 4 wherein in order to determine a data rate for transmission to a peripheral device the processor is operable to successively send a plurality of signals to the peripheral device at different data rates and determine whether or not the signals have been successfully received by the peripheral device.
10. The control panel of claim 9 wherein the processor is operable to determine the data rate for transmission to the peripheral device as the data rate of the signal with the highest data rate that was successfully received by the peripheral device.
11. The control panel of any preceding claim wherein the processor is arranged to determine a data rate for transmission to at least one of the one or more peripheral devices upon power up.
12. The control panel of any preceding claim wherein the processor is arranged to determine a data rate for transmission to at least one of the one or more peripheral devices in response to a network error.
13. The control panel of claim 12 wherein the network error includes one or more peripheral devices being unresponsive for a specified time period or an increase in a packet error rate from one or more peripheral devices.
14. A security alarm system comprising:
the control panel of any preceding claim; and one or more peripheral devices, wherein the control panel and the or each peripheral devices are connected to so as to form a network.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1617113.4A GB2554744B (en) | 2016-10-07 | 2016-10-07 | Control panel for a security alarm system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1617113.4A GB2554744B (en) | 2016-10-07 | 2016-10-07 | Control panel for a security alarm system |
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| Publication Number | Publication Date |
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| GB201617113D0 GB201617113D0 (en) | 2016-11-23 |
| GB2554744A true GB2554744A (en) | 2018-04-11 |
| GB2554744B GB2554744B (en) | 2021-11-24 |
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| GB1617113.4A Active GB2554744B (en) | 2016-10-07 | 2016-10-07 | Control panel for a security alarm system |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1699028A1 (en) * | 2005-03-01 | 2006-09-06 | Omron Corporation | Wireless alarm system with remote alarm receipt |
| US7580755B1 (en) * | 2004-11-19 | 2009-08-25 | Pacesetter, Inc. | Automatic data transmission rate adjustment |
| US20100067524A1 (en) * | 2006-09-28 | 2010-03-18 | Vinod Luthra | Method and system for selecting a data transmission rate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4239702C1 (en) * | 1992-11-26 | 1994-03-24 | Grundig Emv | Method for monitoring and operating a radio link between the central unit of an alarm system and its outstations containing monitoring sensors |
| JPWO2003009533A1 (en) * | 2001-07-11 | 2004-11-11 | 富士通株式会社 | Interface device and control method thereof |
| CN100426899C (en) * | 2005-09-13 | 2008-10-15 | 华为技术有限公司 | Apparatus and method for regulating interface transmission rate of transmission device |
| WO2016017995A1 (en) * | 2014-07-31 | 2016-02-04 | Samsung Electronics Co., Ltd. | System and method of controlling data transmission of external apparatus connected to gateway |
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2016
- 2016-10-07 GB GB1617113.4A patent/GB2554744B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7580755B1 (en) * | 2004-11-19 | 2009-08-25 | Pacesetter, Inc. | Automatic data transmission rate adjustment |
| EP1699028A1 (en) * | 2005-03-01 | 2006-09-06 | Omron Corporation | Wireless alarm system with remote alarm receipt |
| US20100067524A1 (en) * | 2006-09-28 | 2010-03-18 | Vinod Luthra | Method and system for selecting a data transmission rate |
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| Publication number | Publication date |
|---|---|
| GB2554744B (en) | 2021-11-24 |
| GB201617113D0 (en) | 2016-11-23 |
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