GB2553849A - Method of reducing device contact resistance - Google Patents

Method of reducing device contact resistance Download PDF

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GB2553849A
GB2553849A GB1615909.7A GB201615909A GB2553849A GB 2553849 A GB2553849 A GB 2553849A GB 201615909 A GB201615909 A GB 201615909A GB 2553849 A GB2553849 A GB 2553849A
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sic region
silicon layer
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electronic device
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Ward Peter
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Anvil Semiconductors Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H01L29/1008—Base region of bipolar transistors of lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Electrodes Of Semiconductors (AREA)

Abstract

Manufacturing a silicon carbide (SiC) based electronic device comprising: forming a first SiC region 110; forming a second SiC region in the first SiC region 120, 135 wherein the second SiC region has a higher doping concentration than the first SiC region; forming a silicon layer 130,140 having a predetermined thickness on the second SiC region; and forming a metal contact 150, 160 on the silicon layer to form an electrical contact to the second SiC region. This can be used to reduce the contact resistance of a device. The first and second SiC regions can comprise 3 step silicon carbide (3C-SiC), or 4 step hexagonal carbide (4H-SiC). The doping concentration in the silicon layer may be substantially the same as the doping concentration level of the second SiC region, and may be of the same doping type. The silicon layer may be formed at least partially on the first SiC region.

Description

(54) Title of the Invention: Method of reducing device contact resistance Abstract Title: Reducing contact resistance in a silicon carbide device (57) Manufacturing a silicon carbide (SiC) based electronic device comprising: forming a first SiC region 110; forming a second SiC region in the first SiC region 120, 135 wherein the second SiC region has a higher doping concentration than the first SiC region; forming a silicon layer 130,140 having a predetermined thickness on the second SiC region; and forming a metal contact 150, 160 on the silicon layer to form an electrical contact to the second SiC region. This can be used to reduce the contact resistance of a device. The first and second SiC regions can comprise 3 step silicon carbide (3C-SiC), or 4 step hexagonal carbide (4H-SiC). The doping concentration in the silicon layer may be substantially the same as the doping concentration level of the second SiC region, and may be of the same doping type. The silicon layer may be formed at least partially on the first SiC region.
Figure GB2553849A_D0001
At least one drawing originally filed was informal and the print reproduced here is taken from a later filed formal copy.
1/3
11 17
Figure GB2553849A_D0002
160
Figure GB2553849A_D0003
Figure 1
2/3
200 160
Figure GB2553849A_D0004
N- 3C-SiC
11 17
110
Figure 2
3/3
11 17
Figure GB2553849A_D0005
Figure 3
Method of Reducing Device Contact Resistance
FIELD OF THE INVENTION
This invention relates to a method of reducing contact resistance in a silicon carbide based electronic device, particularly but not exclusively, in a 3 step cubic silicon carbide (3C-SiC) based electronic device.
BACKGROUND TO THE INVENTION
One of the difficulties in device manufacturing on both 4 step hexagonal silicon carbide (4H-SiC) and 3C-SiC relates to the contact resistance between metal contacts and the semiconductor material. This contact resistance is high because the solubility of dopants in SiC is roughly one tenth of that in silicon (Si), and since diffusion is negligible in SiC it is difficult to make sure that the metal contact intercepts the dopant profile in the SiC in an optimum manner.
SUMMARY
One solution to this problem is to grow a thin (0.1 to 0.2) micron layer of Si on top of the SiC region. This layer may then be heavily doped p or n-type and the contact resistance is reduced by at least a factor of 10. An advantage of this technique is that the crystal quality of the Si layer is not important since it is not part of the active device. Again, being Si grown on SiC it is very easy to etch it away from regions of the device where it could give problems, for example the Gate region of a gate controlled transistor, e.g. a metal oxide field effect transistor (MOSFET).
According to one aspect of the present invention, there is provided a method of manufacturing a silicon carbide (SiC) based electronic device, the method comprising:
forming a first SiC region;
forming a second SiC region in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region; forming a silicon layer having a predetermined thickness on the second SiC region; and forming a metal contact on the silicon layer to form an electrical contact to the second SiC region.
According to a further aspect of the present invention, there is provided a method of reducing contact resistance of a silicon carbide (SiC) based electronic device, the method comprising:
forming a first SiC region;
forming a second SiC region in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region; forming a silicon layer having a predetermined thickness on the second SiC region; and forming a metal contact on the silicon layer to form an electrical contact to the second SiC region.
According to a further aspect of the present invention there is provided a method of forming an electronic contact of a silicon carbide (SiC) based electronic device, the method comprising:
forming a first SiC region;
forming a second SiC region in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region; forming a silicon layer having a predetermined thickness on the second SiC region; and forming a metal contact on the silicon layer to form an electrical contact to the second SiC region.
Advantageously, the band structure at the Si/SiC interface aligns very well to make the necessary conduction from the metal contact to the contact region (second SiC region). It is apparent from the electron affinity data that the conduction bands of n+ Si and n+ 3C-SiC align very well and so there is no interface resistance and advantageously it acts as a blocking contact to holes. In the case of p+ Si and p+ 3C-SiC, if the valence bands are aligned by dint of heavy doping then the lower conduction band in the Si acts to extract any minority carrier electrons. Advantageously any injected minority carrier population in the SiC recombine well before reaching the contact.
The silicon layer may be formed at least partly on the first SiC region.
The predetermined thickness of the silicon layer may be at least about 0.1 pm. The predetermined thickness of the silicon layer may be less than about 0.2 pm. The predetermined thickness of the silicon layer may be between about 0.1 pm and about 0.2 pm.
The doping type of the silicon layer may be the same as the doping type of the second SiC region.
The doping concentration level of the silicon layer may be substantially the same as the doping concentration level of the second SiC region.
The doping concentration of the second SiC region and the silicon layer may be about 1021 cm’3.
The first and second SiC regions each may comprise 3 step cubic silicon carbide (3CSiC).
The first and second SiC regions may each comprise 4 step hexagonal silicon carbide (4H-SiC).
According to a further aspect of the present invention, there is provided a silicon carbide (SiC) based electronic device comprising:
a first SiC region;
a second SiC region disposed in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region;
a silicon layer having a predetermined thickness disposed on the second SiC region; and a metal contact on the silicon layer to form an electrical contact to the second SiC region, wherein the silicon layer is configured to reduce contact resistance between the second SiC region and metal contact.
The silicon layer may be formed at least partly on the first SiC region.
The predetermined thickness of the silicon layer may be at least about 0.1 pm.
The predetermined thickness of the silicon layer may be less than about 0.2 pm.
The predetermined thickness of the silicon layer may be between about 0.1 pm and about 0.2 pm.
The doping type of the silicon layer may be the same as the doping type of the second SiC region.
The doping concentration level of the silicon layer may be substantially the same as the doping concentration level of the second SiC region.
The doping concentration of the second SiC region and the silicon layer may be about 1021 cm’3.
The first and second SiC regions may comprise 3 step cubic silicon carbide (3C-SiC).
The first and second SiC regions may comprise 4 step hexagonal silicon carbide (4HSiC).
The second SiC region may be a contact region. The metal contact may form an ohmic contact on the silicon layer and the second SiC region.
The electronic device may be any one of: a diode;
a metal oxide semiconductor field effect transistor (MOSFET); a bipolar junction transistor (BJT); an insulated gate bipolar transistor (IGBT); and a thyristor.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only.
Figure 1 is a schematic diagram of a lateral diode;
Figure 2 illustrates a schematic view of a SiC based MOSFET, and
Figure 3 illustrates a flow diagram of the manufacturing process of a contact region of a SiC based electronic device.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 is a schematic diagram of a lateral diode 100. The diode 100 includes an ntype epitaxial layer or the first SiC region 110 in which two heavily doped epitaxial layers 120, 135 are grown. One heavily doped layer is a p+ region 120 and the other heavily doped layer is an n+ region 135. The p+ region 120 and n+ region 135 form the second SiC region. Each of the second SiC region forms a heavily doped contact region. The doping concentration of the contact regions is about 102°cm'3. In one embodiment, the first SiC region 110 includes 3C SiC material. Alternatively, the first SiC region 110 includes 4H-SiC or 6 step hexagonal SiC (6H-SiC) material. Similarly, each of the second SiC regions 120, 135 includes 3C-SiC material. Alternatively, each of the second SiC regions 120, 135 includes 4H-SiC or 6H-SiC.
In the embodiment of Figure 1, metal contacts 150, 160 are formed on top of the contact regions or second SiC regions 120, 135. However, a thin silicon layer 130, 140 is formed between the metal contacts 150, 160 and the second SiC regions or contact regions 120, 135. In other words, the thin silicon layer 130, 140 is formed directly on the second SiC regions 120, 135 and the metal contacts 150, 160 are formed directly on the silicon layers 130, 140. The thickness of the silicon layer 130, 140 is generally 0.1 pm to 0.2 pm. It would be appreciated that other dimensions are also possible. The doping type of the thin silicon layer is generally the same as that of the corresponding contact region on which the silicon layer is formed. For example, in Figure 1, the p+ contact region 120 has a p+ silicon layer formed on it. The n+ contact region 135 has an n+ contact region 140 formed on it. The silicon layer 130, 140 is also heavily doped, for example, the concentration level of the silicon layer 130, 140 is substantially (almost) the same as the doping concentration level of the contact region or the second SiC region 120, 135. In one example, the doping concentration of the silicon layer 130, 140 is about 1021 cm'3.
The metal contacts 150, 160 are generally any suitable metal for SiC devices, for example, made of nickel, titanium silicide, Nickel silicide, platinum silicide. The metal contacts 150, 160 form ohmic contacts on the thin silicon layers 130, 140 and on the contact regions 120, 135.
Again, being Si grown on SiC it is very easy to etch it away from regions of the device where it could give problems, for example the Gate region of a gate controlled transistor, e.g. a metal oxide field effect transistor (MOSFET).
Advantageously, the band structure at the Si/SiC interface aligns sufficiently to make the necessary conduction from the metal contact to the contact region (second SiC region). It is apparent from the electron affinity data that the conduction bands of n+ Si and n+ 3C-SiC align sufficiently and so there is no interface resistance and advantageously it acts as a blocking contact to holes. In the case of p+ Si and p+ 3CSiC, if the valence bands are aligned by dint of heavy doping then the lower conduction band in the Si acts to extract any minority carrier electrons. Advantageously any injected minority carrier population in the SiC recombine well before reaching the contact.
Figure 2 illustrates a schematic view of a SiC based MOSFET. The MOSFET includes a n-type substrate or the first SiC region 110 in which p+ epitaxial layers 120, 125 are formed. The p+ epitaxial layers 120, 125 act as contact regions or second SiC regions. One p+ epitaxial layer 120 acts as a source and the other epitaxial layer 125 acts as a drain. Heavily doped thin silicon layers 130, 140 are formed directly on the contact regions 120, 125. The thickness of the thin silicon layers 130, 140 is about 0.1 pm to 0.2 pm. In this example, both the silicon layers 130, 140 are p+ doped (heavily doped) regions. Metal contacts or ohmic contacts 150, 160 are formed directly on the silicon layers 130, 140.
In Figure 2, a gate oxide 200 is formed between contact regions 120, 125 and a gate contact (not shown) is placed on the gate oxide 200. The silicon layers 130, 140 are etched away from the gate oxide 200 to a predetermined distance, for example about 0.5 pm, so that an active channel region underneath the gate oxide 200 does not have any interference with the silicon layers 130, 140.
The same principle of growing a thin silicon layer between the metal contact and SiC contact regions can apply to other semiconductor devices such as bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs) and thyristors. The principle can be equally applied to low voltage and high voltage semiconductor devices. It can equally be applied to vertical and lateral power semiconductor devices.
Figure 3 illustrates a flow diagram of the manufacturing process of a contact region of a SiC based electronic device.
In step 1, a first SiC region (usually a lowly doped substrate) is formed;
In step 2, a second SiC region (usually a heavily doped contact region) is formed within the first SiC region;
In step 3, a thin heavily doped silicon layer (usually about 0.1 pm to 0.2 pm) is formed on the heavily doped contact region. The thin silicon layer is then etched away as necessary from the active region;
In step 4, a metal contact on the thin silicon layer is formed to form an ohmic contact on 15 the contact region. The presence of the thin silicon layer between the metal contact and the contact region reduces contact resistance between the metal contact and SiC based contact region.
Although the invention has been described in terms of preferred embodiments as set 20 forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims (26)

CLAIMS:
1. A method of manufacturing a silicon carbide (SiC) based electronic device, the method comprising:
forming a first SiC region;
forming a second SiC region in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region; forming a silicon layer having a predetermined thickness on the second SiC region; and forming a metal contact on the silicon layer to form an electrical contact to the second SiC region.
2. A method of reducing contact resistance of a silicon carbide (SiC) based electronic device, the method comprising:
forming a first SiC region;
forming a second SiC region in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region; forming a silicon layer having a predetermined thickness on the second SiC region; and forming a metal contact on the silicon layer to form an electrical contact to the second SiC region.
3. A method of forming an electronic contact of a silicon carbide (SiC) based electronic device, the method comprising:
forming a first SiC region;
forming a second SiC region in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region; forming a silicon layer having a predetermined thickness on the second SiC region; and forming a metal contact on the silicon layer to form an electrical contact to the second SiC region.
4. A method according to any preceding claim, wherein the silicon layer is formed at least partly on the first SiC region.
5. A method according to any preceding claim, wherein the predetermined thickness of the silicon layer is at least about 0.1 pm.
6. A method according to any preceding claim, wherein the predetermined thickness of the silicon layer is less than about 0.2 pm.
7. A method according to any one of claims 1 to 4, wherein the predetermined thickness of the silicon layer is between about 0.1 pm and about 0.2 pm.
8. A method according to any preceding claim, wherein the doping type of the silicon layer is the same as the doping type of the second SiC region.
9. A method according to any preceding claim, wherein the doping concentration level of the silicon layer is substantially the same as the doping concentration level of the second SiC region.
10. A method according to any preceding claim, wherein the doping concentration of the second SiC region and the silicon layer is about 1021 cm'3.
11. A method according to any preceding claim, wherein the first and second SiC regions each comprise 3 step cubic silicon carbide (3C-SiC).
12. A method according to any one of claims 1 to 11, wherein the first and second SiC regions each comprise 4 step hexagonal silicon carbide (4H-SiC).
13. A silicon carbide (SiC) based electronic device comprising:
a first SiC region;
a second SiC region disposed in the first SiC region, the second SiC region having a higher doping concentration than the first SiC region;
a silicon layer having a predetermined thickness disposed on the second SiC region; and a metal contact on the silicon layer to form an electrical contact to the second SiC region, wherein the silicon layer is configured to reduce contact resistance between the second SiC region and metal contact.
14. An electronic device according to claim 13, wherein the silicon layer is formed at least partly on the first SiC region.
15. An electronic device according to claim 13 or 14, wherein the predetermined thickness of the silicon layer is at least about 0.1 pm.
16. An electronic device according to claim 13, 14 or 15, wherein the predetermined thickness of the silicon layer is less than about 0.2 pm.
17. An electronic device according to any one of claims 13 to 16, wherein the predetermined thickness of the silicon layer is between about 0.1 pm and about 0.2 pm.
18. An electronic device according to any one of claims 13 to 17, wherein the doping type of the silicon layer is the same as the doping type of the second SiC region.
19. An electronic device according to any one of claims 13 to 18, wherein the doping concentration level of the silicon layer is substantially the same as the doping concentration level of the second SiC region.
20. An electronic device according to any one of claims 13 to 19, wherein the doping concentration of the second SiC region and the silicon layer is about 1021 cm’3.
21. An electronic device according to any one of claims 13 to 20, wherein the first and second SiC regions comprise 3 step cubic silicon carbide (3C-SiC).
22. An electronic device according to any one of claims 13 to 20, wherein the first and second SiC regions comprise 4 step hexagonal silicon carbide (4H-SiC).
23. An electronic device according to any one of claims 13 to 22, wherein the second SiC region is a contact region.
24. An electronic device according to any one of claims 13 to 23, wherein the metal contact forms an ohmic contact on the silicon layer and the second SiC region.
25. An electronic device according to any one of claims 13 to 24, wherein the electronic device is any one of:
a diode;
a metal oxide semiconductor field effect transistor (MOSFET); a bipolar junction transistor (BJT); an insulated gate bipolar transistor (IGBT); and a thyristor.
26. A method of manufacturing a silicon carbide (SiC) based electronic device and a SiC based electronic device, substantially as hereinbefore described with reference to and as illustrated, in the accompanying drawings.
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