GB2504613A - Integrated diamond p-channel FETs and GaN n-channel FETs - Google Patents

Integrated diamond p-channel FETs and GaN n-channel FETs Download PDF

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GB2504613A
GB2504613A GB201312670A GB201312670A GB2504613A GB 2504613 A GB2504613 A GB 2504613A GB 201312670 A GB201312670 A GB 201312670A GB 201312670 A GB201312670 A GB 201312670A GB 2504613 A GB2504613 A GB 2504613A
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diamond
semiconductor device
channel
substrate
layer
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Dubravko Babic
Quentin Diduck
Earl Mccune
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Element Six Technologies US Corp
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Element Six Technologies US Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

Adjacent non overlapping n-GaN FET device 502 and p-diamond FET device 503 are integrally formed on a substrate 501. The two devices form a complementary pair that can be used for push-pull amplifiers or synchronous rectifiers and MMICs. The substrate may be a diamond substrate and the diamond FET p-channel may be formed in the diamond substrate surface. The p-channel may be formed by ion implantation.

Description

HIGH POWER COMPLIMENTARY FIELD-EFFECT TRANSISTORS
FIELD OF THE INVENTION
This application relates to the heterogeneous integration of gallium nitride-based electronic devices with electronic devices built on silicon, silicon carbide, and diamond.
BACKGROUND OF THE INVENTION
Complimentary p-channel and n-channel field-effect transistors are essential elements of digital electronics and many analog and switching power applications, such as, high-efficiency push-pull Class B amplification and switching amplifiers. Novel solid-state high-power amplifiers and power electronics rely on new materials like silicon carbide, gallium nitride, and in recent years, diamond. These materials lend themselves to efficient field-effect transistor realization: GaN gives rise to high-power and high-frequency n-channel HEMTs, n-type doping in a diamond substrate has not yet been developed, but p-channel MESFETs have successfully been built in diamond. Each of these materials on its own provides either an n-channel or a p-channel device, and hence building complimentary pairs for circuits is not available.
It is the objective of the present invention is to disclose complimentary pairs based on GaN and diamond transistors.
It is furthermore the objective disclose a complimentary pair of devices that has high thermal conductivity and can therefore be implemented in high power circuits.
It is also the objective of this invention to enable integration of p-channel and n-channel devices onto the same substrate and enable integrated circuits, including monolithic microwave integrated circuits (MMIC5) and complimentary MMICs.
SUMMARY OF THE INVENTION
This patent application discloses (a) heterogeneous integration of n-channel GaN field-effect transistors and p-channel diamond field-effect transistors, (b) methods for forming this integration, and (c) circuit configurations that take advantage of the disclosed preferred heterogeneous integration.
The gallium nitride (CaN) material system gives rise to microwave transistors with high-electron mobility (necessary for high-speed operation), high breakdown voltage (necessary for high power), and thermal conductivity that is greater than gallium arsenide (GaAs) or indium phosphide (lnP), and thus suitable for use in high power applications. CaN is also manufactured at temperatures closer to those used in silicon processing (-1000°C). Commercial devices in which CaN epilayers are grown on silicon and silicon carbide are presently available from manufacturers such as Cree, Inc., Triquint, and Nitronex, Inc of North Carolina.
The most investigated gallium-nitride high-power transistor structure is that of the high-electron mobility transistor (HEMT) 100, illustrated in Figure 1. This exemplary transistor 100 comprises a substrate 101 on top of which a layered structure 110 is grown. The layered structure 110 comprises a nucleation/transition layers 102, gallium nitride buffer layer 103, and barrier layer 104 forming a two-dimensional electron gas (2DEG) 105 as is well known in the art of manufacturing high electron mobility transistors. The field-effect transistor also features electrical contacts to the source 106, drain 107, and gate 108. Since GaN is a single crystal with a lattice constant that is different from the substrate, it is necessary to grow several layers to accommodate for the lattice constant change and absorb the dislocations. These layers are collectively referred to as the transition/nucleation layers 102, and typically comprise ternary AIGaN alloys or just AIN. The electrons in the 2DEG 105 have very high mobility and carry current from the source 110 to the drain 107.
This current path is commonly referred to as the channel. The density of the electrons in the channel determines the resistance between the source and the drain and is controlled with the voltage on the gate terminal 108 relative to the source 106 and the drain 107. Finally, using a small voltage applied to the gate terminal 108 one can control very large currents in the 2DEG 105-this is the fundamental requirement for current and power amplification in electronic devices. Since in the described HEMT, the current in the channel is conducted by the electrons, it is referred to as an n-channel field-effect transistor. The same epilayer structure does not lend itself to making channels in which the current is conducted by holes, namely, p-channel field-effect transistors.
Natural diamond is an excellent thermal conductor, but historically has not been available for electronic applications due to scarcity and price. Chemical-vapor deposited (CVD) diamond is polycrystalline and in this form can be used in electronics and micro-electromechanical systems due to its hardness, high thermal conductivity and high critical electric field. In the chemical vapor deposition process a substrate on top of which synthetic diamond is to be deposited is placed in a vacuum chamber, where methane and hydrogen are introduced and activated using either microwave plasma or tungsten filaments (or any other method known in the art of CVD diamond deposition). The typical wafer temperatures are around 800°C during the deposition process and the deposition rates are measured in micrometers (pm) per hour. The growth of synthetic diamond includes a nucleation phase in which conditions are adjusted to enhance the nucleation of diamond on the host substrate.
This may be done by seeding the surface with diamond powder and by forming a nucleating layer of suitable material on top of the surface. Nucleation layer means, in material deposition or crystal growth, a layer that helps start the growth or formation of another layer of material or stoichiometry. Examples of preferred nucleating layer materials are amorphous silicon nitride and amorphous silicon carbide. Other amorphous or polycrystalline materials known to aid in the nucleation of synthetic diamond may be used without departing from the scope of the present invention. Examples are silicon and other wide-gap semiconductor materials. Rather than depositing the nucleation layer in a separate process step, the surface may be prepared for synthetic diamond nucleation by ending the growth of a wide-gap semiconductor layered structure with a layer specifically formed to nucleate synthetic diamond. The choice of materials is a wide-gap semiconductor, such as aluminum nitride or silicon carbide, that may be crystalline or polycrystalline. In this latter embodiment, no additional deposition of a nucleating layer is necessary as the surface on which synthetic diamond is to be grown has already been prepared for nucleation. An improper choice of nucleating film may result in highly stressed films or with highly thermally resistive diamond layers. During the growth phase, the grain size of synthetic diamond increases and as a result synthetic diamond films are inherently rough after deposition.
Diamond is expected to be the most suitable material for high-power high-frequency electronic devices because of its high mobility for both electrons and holes, along with a high saturation velocity. To realize commercial p-channel and n-channel field-effect transistors, such transistors have to be formed on substrates with diameters of at least 100 mm. The donor levels of known n-type impurities is 470 meV below the conduction band which results in very low level of ionization at room temperature.
For this reason, there have not yet been any demonstrations of high quality n-channel field-effect transistors. p-channel field effect transistors have been demonstrated as several methods have be demonstrated to achieve p-doping and p-channels: hydrogen passivated surface creates high hole concentrations (1 xl 013 cm2), or delta-doping boron at high concentrations (growing layers or by implantation) or with alumina insulator below the gate. Figure 2 shows the structure of an exemplary diamond transistor 200 (prior art). It comprises a substrate 201 on top of which polycrystalline diamond layer 202 is grown. The transistor 200 has a source terminal 203, drain terminal 204, and a gate terminal 203. A p-channel 206 is formed by ion implantation or hydrogen diffusion. Typical structure of a diamond field-effect transistor is that of a MESFET: Metal-Semiconductor Field-Effect Transistor, a structure well known in the art of semiconductor devices. Examples of diamond FETs are published in the following publications: K. Hirama, et al., "Diamond MISFET fabricated on high-quality polycrystalline CVD diamond", Proc. 19th Int. Symp.
On Power Semiconductor Devices and ICs, May 27-30, 2007 Jeju, Korea, and K. Ueda, et al., "Diamond FET using high-quality polycrystalline diamond with ft of 45 GHz and fmax of 120 GHz", IEEE EDL vol 27, no. 7, p. 570 (2006).
In an embodiment of the present invention, a GaN-based n-channel field-effect transistor is integrated on the same chip with a diamond p-channel field-effect transistor. This structure allows for the creation of a high-power complimentary pair for use in high-frequency power amplifiers and power electronics circuits. A further advantage of this type of circuit is the improved thermal resistance of the GaN HEMT as it is integrated on top of a diamond substrate which has very high thermal conductivity.
In one embodiment, the integration of GaN with diamond uses metal bonding between GaN and diamond, wherein the bond involves brazing or soldering, and the metal used is either a solder or a multilayer stack that includes gold and refractory metals. In radio frequency (RF) electronics where the buried metal layers cause unacceptably high capacitance or lower breakdown voltages of the devices, a different type of integration is employed. In another embodiment, gallium nitride epilayers are atomically attached to diamond, one example is described in US patent 7,595,507.
In this latter case, GaN epilayers are insulated from the diamond substrate and RF devices can be made. In yet another embodiment, GaN epilayers may be attached to the diamond substrate using metal bonding, in which case the bond is conductive and the transistor may be used in power management where the frequencies are significantly lower than in RE power applications.
The term "wide-gap semiconductor technology" is widely used in the industry and it refers to electronic and optoelectronic device and manufacturing technology based on wide-gap semiconductors. In this application, for clarity, "wide-gap semiconductor" means (a) semiconductors comprising a bond between nitrogen (N) and at least one Group Ill element from the Periodic Table of the Elements (boron, aluminum, gallium, indium, and thallium), (b) semiconductors comprising a bond between carbon (C) and at least one Group IV element from the Periodic Table of the Elements (carbon, silicon, germanium, tin, and lead), or (c) semiconductors comprising a bond between oxygen (0) and at least one Group II element from the Periodic Table of the Elements (e.g. beryllium, magnesium, calcium, zinc, cadmium). Specifically, this application applies, but is not limited to, gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), aluminum gallium nitride (AIGaN), indium gallium nitride (InGaN), aluminum indium nitride (AIInN), zinc oxide (ZnO), silicon carbide (Sic), and diamond (C). Single-crystal means being of one crystal, or having a translational symmetry. This term is common for crystal growth, and is a requirement for most semiconductors. Polycrystalline means consisting of crystals variously oriented or composed of more than one crystal. Amorphous means a material having no real or apparent crystalline form. As is well known in the industry, single crystal wafers and substrates are made using bulk crystal growth techniques resulting in large so called boules, which are then cut to wafer shape. Electronic and optoelectronic devices manufactured out of single-crystal layers of different semiconductor properties are made by different single-crystal growth techniques. It well known in the industry that single-crystal layers for electronic and optoelectronic devices are formed in specially designed machines which enable precise growth of very thin single-crystal semiconductor layers on top of wafers or other thin semiconductor layers. The layers manufactured in such machines are commonly referred to as epitaxial layers and their thickness can vary anywhere from sub-nanometer to tens of micrometers. The machines that make them are referred to as epitaxial growth machines. Examples are Molecular Beam Epitaxy (MBE), Organo-Metallic Vapor-Phase Epitaxy (OMVPE) also referred to as metal organic chemical vapor deposition (MOCVD), and Liquid Phase Epitaxy (LPE).
Integration of devices means building all components of the circuit on a single chip (monolithic integration) or realizing inter-device connections using chip-level technology -metallization and substrate contacts (hybrid integration). Hybrid integration means that multiple (more than one) chips are completed and placed on a larger sub-assembly. Monolithic integration stands for device integrated on a chip where the devices are processed in sequence by processing on the same chip, rather than adding a device externally. Monolithic integration generally means that all of the devices and passives are realized using the same semiconductor (monolithic meaning same lattice constant). When integration of different devices is realized using devices that have different crystal structure, but are formed on the same chip or substrate, then we speak of heterogeneous integration.
The subject of this patent application is (a) heterogeneous integration of n-channel GaN FETs and p-channel synthetic diamond FETs, (b) methods for forming this integration, and (c) circuit configurations that take advantage of the disclosed preferred heterogeneous integration.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 (PRIOR ART) A typical structure of a AIGaN/GaN high-electron mobility transistor on a substrate that may be silicon carbide, silicon, or sapphire; Figure 2 (PRIOR ART) A typical structure of a diamond p-channel field-effect transistor on diamond substrate; Figure 3 A circuit diagram of a complementary pair including at least one p-
channel and one n-channel field effect transistor;
Figure 4 Illustration showing how (a) islands of epilayer (shaded) may be attached to a diamond (clear) substrate, and (b) the epilayer (shaded) opened in places to reveal the substrate material (clear); Figure 5 Illustration showing the structure and an exemplary circuit connections of a ri-channel field effect transistor realized in GaN epilayers and a p-channel transistor in the diamond epilayers on a substrate; and Figure 6 Illustration showing the structure and exemplary circuit connections of an n-channel field effect transistor realized in GaN epilayers and a p-channel transistor in the diamond substrate.
DETAILED DESCRIPTION OF THE INVENTION
The integration of an n-channel GaN FET and a p-channel diamond PET offers advantages to a number of circuit configurations commonly used in linear and switching circuits. One circuit embodiment employing this integration is shown in Figure 3 and referred to as the complimentary pair.
Class B push-pull amplifiers are of high interest in various amplification applications because they offer good linear performance at reasonably high energy efficiency.
The ideal Class B amplifier reaches an energy efficiency greater than 78%. In audio amplification technology, a conventional Class B amplifier output stage is usually realized using a complimentary PNP and NPN bipolar transistor or with a complimentary pair of p-channel and n-channel field-effect transistors. A sinusoidal signal driving a push-pull output stage is split in such a way to have the positive part of the signal activate the n-channel FET and the negative part of the signal activate the p-channel FET. Although complimentary FETs and BJTs are available in silicon technology and are widely used at audio frequencies, at RF and mm-wave frequencies where compound semiconductors are used the difference between n-channel and p-channel FET performance are vastly different, resulting in having the push-pull combination being essentially unused. The primary reason is majority carrier mobility. Electron mobilities are typically many times higher that hole mobilities in a semiconductor material system. For this reason, high-efficiency Class B RF amplifiers (push-pull) are realized using a pair of two similar n-channel FETs.
The common term for such amplifiers is "differential amplifiers". A push-pull circuit using all n-channel FETs necessarily involves power combining using either a transformer or at least one balun. Unfortunately, transformers are not practical at the RF and mm-wave frequencies and baluns limit the bandwidth of the amplifier. These circuit configurations and the issues related to their performance are described in publicly available references such as the book titled "RE power amplifiers for Wireless Communications" by Steve Cripps published by Artech House. The industry would greatly benefit from the use of a complimentary (p-channel) EET at high-frequencies (RE and mm-wave) and in applications which require very high powers and high-efficiencies. This is particularly enabling for microwave and mm-wave integrated circuits where the complimentary pair is integrated on the same substrate.
The circuit embodiment shown in Figure 3 shows a series connection of the disclosed transistors which is of particular interest. The circuit in Figure 3 shows a circuit comprising of an n-channel GaN FET 301 and p-channel diamond FET 302 connected in series with their drain terminals connected. The source of the diamond FET 302 is connected to a positive supply voltage 304. The input signal enters at 305 and drives the two transistors alternatively: while one is open the other closed.
the voltage at the output terminal 303 is either linearly controlled by the input voltage 305 in which case we speak of class B push-pull circuit or driven alternatively from the OFF to ON state, in which case the output is switched between the supply voltage and the ground.
This circuit configuration, along with various connections of drive circuitry at the gates of each disclosed EET device, are used to solve various circuit problems encountered when integrating RE functions into products. These circuit problems include but are not limited to switched voltage source supply, output power control, and control logic. For example, for a switched voltage supply application a signal at the operating frequency is applied to the gates of both devices. This signal is designed such that the n-channel device is turned ON when the p-channel device is turned OFF, and vice versa. In this manner the voltage sources of the power supply or the ground reference are selectively and alternatively connected to following circuitry.
This same circuit structure supports a completely different application: that of output power control, when the operating frequency drive signal is supplied only to the n-channel device. In this application the drive signal to the p-channel device is completely independent, such that the p-channel device acts to control the average current through the n-channel device when it is ON. This can be through action such as linear voltage or current regulation. It can also be implemented through what are known as class-S techniques within the art.
In modern applications it is also of growing importance to include some type of logic circuitry to control and possibly adapt the operation of the power circuitry to present operating conditions. It is recognized that this same circuit structure is used in complementary metal-oxide-semiconductor (CMOS) logic, a technology very well known in the art. This circuit structure therefore enables similar capabilities for MMIC implementations on a diamond substrate.
One alternative circuit embodiment for which the disclosed technology is particularly enabled by the technology disclosed herein. In this application, known as the "synchronous rectifier", there is a very tight requirement in the transfer of current flow from the p-channel FET to the n-channel FET while the inductor current continues to flow. If there is even a very short time when both FET devices are OFF (not enabled to conduct current) then the voltage at the common node with the inductor load may rise very fast to an extremely high value, sufficient to destroy one or both of the FF1 devices. On the other hand, if both FET devices are ON (fully enabled to conduct current) for any appreciable length of time then this provides a current path separate from the desired path through the inductor which may result in sufficiently large current flow to damage or destroy one or both of the FET devices.
Because of these two limits, it is the present practice in the art to operate this circuit at a significantly lower frequency such that the aforementioned problems can be more readily addressed. This result comes at a cost of lower efficiency, proportionally larger inductor values and costs, and a reduced ability to adjust the circuit output characteristics in a rapid manner. The present invention, in providing for very high speed complementary transistors on one common substrate, enables a solution to the above problems by nearly eliminating interconnect inductances while providing high speed operation and complementary structures as described above.
In one embodiment of the present invention, the diamond p-channel field-effect transistor (FET) is integrated with a GaN n-channel FET on the same substrate. An exemplary structure used to describe some of the embodiments is shown in Figure 5. A semiconductor device comprises a substrate 501 with some areas on its top surface covered with gallium nitride epilayers 502 and other areas on it top surface covered with diamond 503. Electrical contacts 504, 505, 506 disposed on the gallium nitride epilayers 502, together with the gallium nitride epilayers 502 form an electronic device such as an n-channel field-effect transistor 507. In one embodiment, the field-effect transistor 507 also comprises a two-dimensional electron gas (2DEG) 509 and hence forms a high-electron mobility transistor. In one embodiment, the gate terminal 505 of the transistor 507 forms a Schottky contact with the GaN epilayers 502, and in yet another embodiment, an insulating dielectric layer is sandwiched between the gate terminal 505 and the GaN epilayers 502 forming a metal-insulator- field-effect transistor (MISFET) on gallium nitride. In another embodiment, the field-effect transistor 507 is an enhancement-mode transistor. Electrical contacts 510, 511, 512 disposed on the diamond layer 503, together with the diamond layer 503 form an electronic device such as a p-channel field-effect transistor 513. In one embodiment, the field-effect transistor 513 includes a hole channel. In one embodiment, the gate terminal 511 of the transistor 513 forms a Schottky contact with the diamond layer 503, and in yet another embodiment, an insulating dielectric layer (not shown) is sandwiched between the gate terminal 511 and the diamond layer 503 forming a metal-insulator-field effect transistor (MISFET) on diamond. In yet another embodiment, illustrated in Figure 5, the electrical drain contact 506 on the field-effect transistor 507 is electrically coupled to drain contact 510 of the field-effect transistor 513.
In one embodiment, the substrate is made out of silicon, in another embodiment, the substrate is made out of silicon carbide, and in yet another embodiment the substrate is synthetic diamond. The diamond FET 513 and the CaN FET 507 may be enhancement or depletion mode FETs. Figure 5 illustrates biasing and electrical connections when the device shown in Figure 5 is used as a complimentary pair shown in Figure 4. In one embodiment, when the substrate 501 is made out of diamond, the diamond layer 503 is an integral pad of the substrate 501. In other words, the diamond 503 is not deposited, but is already present because the substrate is made out of diamond.
In yet another embodiment, illustrated with the help of Figure 6, a semiconductor device comprises a substrate 601 with some areas on its top surface covered with gallium nitride epilayers 602 and other areas on it top surface open. Electrical contacts 604, 605, 606 disposed on the gallium nitride epilayers 602, together with the gallium nitride epilayers 602 form an electronic device such as an n-channel field-effect transistor 607. In one embodiment, the field-effect transistor 607 also comprises a two-dimensional electron gas (2DEG) 609 and hence forms a high-electron mobility transistor. In one embodiment, the gate terminal 605 of the transistor 607 forms a Schottky contact with the GaN epilayers 602, and in yet another embodiment, an insulating dielectric layer is sandwiched between the gate terminal 605 and the GaN epilayers 602 forming a metal-insulator-field-effect transistor (MISFET) on gallium nitride. In another embodiment, the field-effect transistor 607 is an enhancement-mode transistor. Electrical contacts 610, 611, 612 are disposed in an area on the diamond substrate 6016 that has been etched to remove the top layer of diamond and reach higher quality diamond below the diamond substrate 601 surface.
The depth of the etch is sufficient to remove, what is referred to as, near-substrate diamond region which may contain high fraction of non-diamond components. The depth may be 100 nm deep. The electrical contacts 610, 611, and 612 together with the diamond substrate 601 form an electronic device such as a p-channel field-effect transistor 613. It is clear that other types of devices, such as, Schottky diodes may be made. In one embodiment, the field-effect transistor 613 includes a hole channel. In one embodiment, the gate terminal 611 of the transistor 613 forms a Schottky contact with the diamond substrate 601, and in yet another embodiment, an insulating dielectric layer is sandwiched between the gate terminal 611 and the diamond substrate 601 forming a metal-insulator-field effect transistor (MISFET) on diamond. In yet another embodiment, illustrated in Figure 6, the electrical drain contact 606 on the field-effect transistor 607 is electrically coupled to drain contact 610 of the field-effect transistor 613. In another embodiment, the bond between the gallium nitride epilayers 602 and the diamond substrate 601 may include a metal layer. In this case, the field-effect transistors may be used in power management.
In yet another embodiment, the bond between the gallium nitride epilayers 602 and the diamond substrate 601 may include a dielectric adhesion layer. The dielectric layer may be made out of silicon nitride, silicon carbide, or aluminum nitride. Furthermore, the dielectric layer may be amorphous or polycrystalline.
Figure 4(a) (top view) and 4(c) (cross-sectional view along 405) illustrates the embodiments in which the GaN epilayers form islands or mesas 402 on top of the substrate 401, while Figure 4(b) (top view) and Figure 4(d) (cross-sectional view along 406) illustrates the embodiment in which the openings 404 in the GaN epilayers 403 form wells on the wafer.
It is clear that the integration embodiment disclosed herein may be employed to integrate optoelectronic devices on GaN and in diamond with electronic circuitry without departing from the spirit of the invention.

Claims (15)

  1. CLAIMS1. A semiconductor device comprising: a substrate having a top surface; a multilayered structure layer disposed on at least a first part of said top surface having at least one first electrical contact on top of said multilayered structure layer; a diamond layer of disposed on at least a second part of said top surface having at least one second electrical contact on top of said diamond layer, said first electrical contact is electrically coupled to said second electrical contact; wherein said at least first part of said top surface and said at least second part of said top surface do not overlap.
  2. 2. A semiconductor device according to claim 1, wherein said multilayered structure layer comprises a conductive channel, wherein electrical conduction through said conductive channel is by means of electrons.
  3. 3. A semiconductor device according to claim I or claim 2, wherein said diamond layer comprises a conductive channel, wherein electrical conduction through said conductive channel is by means of holes.
  4. 4 A semiconductor device according to any preceding claim, wherein said semiconductor device is a part of a push-pull amplifier stage.
  5. 5. A semiconductor device according to any preceding claim, wherein said semiconductor device is a part of a synchronous rectifier.
  6. 6. A semiconductor device according to any preceding claim, wherein said substrate made out of material selected from a group including silicon, silicon carbide, aluminum nitride, and diamond.
  7. 7. A semiconductor device according to any preceding claim, wherein a dielectric layer is sandwiched between said multilayered structure layer and said top surface.
  8. 8. A semiconductor device according to claim 7, wherein said dielectric layer is made out of silicon nitride.
  9. 9. A semiconductor device according to any preceding claim, wherein a metal layer is sandwiched between said multilayered structure layer and said top surface.
  10. 10. A method of manufacturing a semiconductor device comprising the steps: growing gallium nitride epilayers on top of a substrate; removing said gallium nitride epilayers at least on a first area; growing diamond in said first area; creating a hole channel in at a part of said diamond layer; depositing electrical contacts on said gallium nitride epilayers; and depositing electrical contacts on said diamond layer.
  11. 11. A method according to claim 10, wherein said substrate is made out of material selected from a group including silicon, silicon carbide, aluminum nitride, and diamond.
  12. 12 A method according to claim 10 or claim 11, wherein said step of growing diamond includes growing diamond on top of at least a part of said gallium nitride layers.
  13. 13. A method of manufacturing a semiconductor device comprising the steps: attaching gallium nitride epilayers on top of a diamond substrate; removing said gallium nitride epilayers at least on a first area; creating a diamond etched area by etching diamond in at least a part of said first area to a depth; creating a hole channel in at a part of said etched diamond area; depositing electrical contacts on said gallium nitride epilayers; and depositing electrical contacts on said diamond layer.
  14. 14. A method according to claim 13, wherein said depth is greater than 100 nanometers.
  15. 15. A method according to claim 13 or claim 14, wherein said hole channel is formed by ion implantation.
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US20170018639A1 (en) * 2015-07-17 2017-01-19 Mitsubishi Electric Research Laboratories, Inc. Semiconductor Device with Multiple Carrier Channels
WO2023212856A1 (en) * 2022-05-05 2023-11-09 Innoscience (suzhou) Semiconductor Co., Ltd. Semiconductor device and method for manufacturing thereof

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US5278430A (en) * 1989-11-18 1994-01-11 Kabushiki Kaisha Toshiba Complementary semiconductor device using diamond thin film and the method of manufacturing this device
US5391895A (en) * 1992-09-21 1995-02-21 Kobe Steel Usa, Inc. Double diamond mesa vertical field effect transistor
US6025211A (en) * 1996-09-02 2000-02-15 Tokyo Gas Co., Ltd. Hydrogen-terminated diamond MISFET and its manufacturing method
WO2011020607A1 (en) * 2009-08-18 2011-02-24 Universität Ulm Semiconductor device and method for manufacturing a semiconductor device

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US5278430A (en) * 1989-11-18 1994-01-11 Kabushiki Kaisha Toshiba Complementary semiconductor device using diamond thin film and the method of manufacturing this device
US5391895A (en) * 1992-09-21 1995-02-21 Kobe Steel Usa, Inc. Double diamond mesa vertical field effect transistor
US6025211A (en) * 1996-09-02 2000-02-15 Tokyo Gas Co., Ltd. Hydrogen-terminated diamond MISFET and its manufacturing method
WO2011020607A1 (en) * 2009-08-18 2011-02-24 Universität Ulm Semiconductor device and method for manufacturing a semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170018639A1 (en) * 2015-07-17 2017-01-19 Mitsubishi Electric Research Laboratories, Inc. Semiconductor Device with Multiple Carrier Channels
WO2017014031A1 (en) * 2015-07-17 2017-01-26 Mitsubishi Electric Corporation Semiconductor device, and method for making semiconductor device
US9876102B2 (en) * 2015-07-17 2018-01-23 Mitsubishi Electric Research Laboratories, Inc. Semiconductor device with multiple carrier channels
WO2023212856A1 (en) * 2022-05-05 2023-11-09 Innoscience (suzhou) Semiconductor Co., Ltd. Semiconductor device and method for manufacturing thereof

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