GB2498525A

GB2498525A - A diamond field effect transistor

Info

Publication number: GB2498525A
Application number: GB201200749A
Authority: GB
Inventors: Richard John Lang; Michael John Uren; Richard Stuart Balmer; Paul Gideon Huggett; James Pilkington
Original assignee: Diamond Microwave Devices Ltd
Current assignee: Diamond Microwave Devices Ltd
Priority date: 2012-01-17
Filing date: 2012-01-17
Publication date: 2013-07-24
Also published as: GB201200749D0

Abstract

A diamond semiconductor field effect transistor, comprising: an n-doped diamond backing layer 330, a diamond buffer layer 332 formed on the backing layer, p-doped source and drain diamond contact layer regions 310S, 310D on the buffer layer or in the surface of the buffer layer opposite to the backing layer, the contact layer regions being spaced apart by a gate portion 334 of the buffer layer by a gate length, a dielectric layer 318 formed across the gate portion of the buffer layer and partially extending over the contact layer regions to form the diamond-dielectric interface, source and drain electrodes 312, 314 electrically contacting the contact layer regions, and a gate electrode 320 is provided on the dielectric, wherein the gate portion of the buffer layer has a density of interface states of less than 2 x 1013 cm- 2 and methods of manufacturing such a transistor. The low density of interface states is produced by wet etching followed by oxygen termination.

Description

A DIAMOND FIELD EFFECT TRANSISTOR

The present invention relates to diamond field effect transistors, and in particular metal-oxide-semiconductor field effect transistors (MOSFET5) formed on diamond semiconductor.

BACKGROUND

Due to physical limitations, silicon, indium phosphide and gallium arsenide devices are limited in their achievable output power capability, depending for example on the frequency to be amplified and the manner in which they are combined. A wider bandgap material, such as diamond, offers the potential of substantially higher power output per unit gate width at microwave frequencies and consequently higher achievable output powers. This is because a larger bias voltage, and hence the voltage amplitude of the microwave signal, can be supported across the transistor channel region over which the current is modulated. In effect this exploits the higher breakdown electric field of a wide bandgap semiconductor. As well as its high bandgap (5.47 eV), further attractions of the diamond system include high bulk thermal conductivity and high intrinsic carrier mobility.

Dopants in wide bandgap semiconductors tend to have higher ionisation energies than those of narrow bandgap semiconductors, resulting in low activation at room temperature. Common dopants in chemical vapour deposition (CVD) diamond and their ionization energies are: boron (0.37 eV) for p-type doping; and nitrogen (1.7 eV) and phosphorus (0.6 eV) for n-type doping.

As boron is readily incorporated into CVD diamond as a dopant impurity, much activity has focussed upon the production of unipolar devices using boron. However, at conventional doping levels, boron acceptors are only weakly activated at room temperature, due to their ionization energy. To mitigate this, the boron solid concentration must be increased to very high levels, where the conduction mechanism changes first from band type conduction to hopping, then at higher doping levels (>1019 cm3) eventually becoming metallic-like as the acceptor band begins to overlap the valence band maximum and the ionization energy approaches zero. This metallic-like conduction condition results in much lower bulk resistivity.

However, the high mobility of intrinsic diamond (up to 3800 cm2V1s1 for holes) is severely reduced when the material is doped, due to ionized impurity scattering. The metallic-like conduction condition requires dopant levels (NA) greater than 1020 cm3, with hole mobility between 1 and 3 cm2V1s1, severely limiting the maximum potential ohmic current transport between the source and drain contacts of a FET with a channel formed of a bulk highly boron doped layer.

Because of these design limitations in boron doped diamond, conventional device designs cannot be expected to yield high performance RF devices. Instead a more creative approach to device design is required in order to utilise the superior properties of intrinsic diamond. In particular it is desirable to achieve some degree of spatial separation between ionized acceptors and holes.

A known epitaxial arrangement that seeks to achieve such separation comprises a delta' doping layer that is overgrown with an adjacent intrinsic bulk layer. The delta layer is a very thin highly (boron) doped region that acts as a source of carriers (holes). The delta layer causes the formation of a quantum well (which is approximately a V-shape, having one vertical side, adjacent the intrinsic layer). The quantum well has at least one confined state, the ground state. The spatial extent of the ground state wavefunction of the quantum well in the delta layer substantially overlaps the intrinsic layer (typically the ground state wavefunction full width at half maximum is much wider than the thickness of the delta layer). Accordingly, carriers (e.g. holes) migrate from the low mobility delta doped layer into the quantum well within the intrinsic layer, where they have a high mobility. Consequently, conduction occurs in both the delta layer and in the intrinsic layer. Conduction in the intrinsic layer will typically be the dominant conduction mechanism, with quantum mechanical calculations predicting that for a delta layer thickness of 2 nm, 95% of the hole transport may take place within the delta layer, in the intrinsic layer. In such an epitaxial arrangement, greater migration of carriers into the intrinsic layer will occur with a thinner delta layer, having the same sheet charge density. Accordingly, the channel current will be greater for a narrower delta layer thickness (with the same sheet charge density), in contrast to a bulk doped layer where the channel current increases with layer width.

The delta doping layer has a sheet charge density in the region of 1013cm2 to enable full channel pinch-off by the gate. Accordingly, the highly doped delta doping layer has a thickness of less than 1 Onm, and advantageously is a monolayer.

Figure 1 illustrates a FET 100 having a delta doping layer 106 and adjacent intrinsic layer 118 formed on a substrate 102. The delta doping layer 106 is common beneath the source, gate and drain contacts of the FET 112, 120 and 114. Such a device is disclosed in W020061 17621.

Disadvantageously, as well as having high parasitic access resistance', such a device suffers from carrier scattering by the dopants.

To remove the disadvantage of scattering from dopants in the conductive channel beneath the gate, a further known device has no doping in the gate region (i.e. no doping in or adjacent the channel), which is contacted at its ends by doped contact layer regions beneath the source and drain electrodes (e.g. a P-i-F MISFET). Such a device is illustrated in Figure 2, in which a contact layer of p-doped diamond 208 has been etched through into the underlying intrinsic diamond 202, before a dielectric 218 and gate electrode 220 are deposited.

However, in such a device, the channel is formed at the diamond-dielectric interface, and disadvantageously prior devices of this type suffer from problems with interface states, beneath the gate, which inhibit the formation of a surface channel and limit carrier mobility. The channel region is defined by etching through the doped layer by a reactive ion etching (RIE) process. Following the reactive ion etching, the surface carbon bonds are chemically passivated by hydrogen or oxygen termination of the surface carbon bonds in a plasma passivation process (using a hydrogen or oxygen plasma), respectively producing a hydrogen-or oxygen-terminated surface.

Disadvantageously, hydrogen-terminated diamond surfaces are thermally and electrically unstable, making them unsuitable for use in commercial transistors.

Further, disadvantageously, diamond surfaces that have been reactively ion etched and then oxygen-terminated by an oxygen plasma process have a high density of interface states (well over 3x 1013 cm-2), about 1.7 eV above the valence band edge, which pins the Fermi level, producing an insulating diamond surface, which is again unsuitable for use in commercial transistors, except in the case that a high concentration of dopants is provided, with the associated disadvantage discussed above.

Further disadvantageously, devices of the type illustrated in Figure 2 rely on space-charge limited currents, in which the channel current is limited by current injection into the bulk of the intrinsic diamond layer. The space-charge limited current flows directly through the undoped bulk of the material and is not controlled at the surface, and requires that the gate length is very short (e.g. less than or equal to 100 nm) for realistic current densities. Since the current is not confined to the surface, RF gate modulation (transconductance) is poor.

SUMMARY OF THE DISCLOSURE

According to a first aspect of the invention, there is provided a diamond

semiconductor field effect transistor, comprising:

an n-doped diamond backing layer, a diamond buffer layer formed on the backing layer, p-doped source and drain diamond contact layer regions on the buffer layer or in the surface of the buffer layer opposite to the backing layer, the contact layer regions being spaced apart by a gate portion of the buffer layer by a gate length, a dielectric layer formed across the gate portion of the buffer layer and partially extending over the contact layer regions to form the diamond-dielectric interface, source and drain electrodes electrically contacting the contact layer regions, and a gate electrode is provided on the dielectric, wherein the gate portion of the buffer layer has a density of interface states of less than 2 x 1013cm2.

According to a second aspect of the invention, there is provided a method of manufacturing a diamond semiconductor field effect transistor, comprising: an n-doped diamond backing layer, a diamond buffer layer formed on the backing layer, p-doped source and drain diamond contact layer regions on the buffer layer or in the surface of the buffer layer opposite to the backing layer, the contact layer regions being spaced apart by a gate portion of the buffer layer by a gate length, a dielectric layer formed across the gate portion of the buffer layer and partially extending over the contact layer regions to form the diamond-dielectric interface, source and drain electrodes electrically contacting the contact layer regions, and a gate electrode is provided on the dielectric, wherein the gate portion of the buffer layer has a density of interface states of less than 2 x 1013 cm2, the method comprising forming the buffer layer on the backing layer, forming a p-doped contact layer on the buffer layer, providing an etch mask on the contact layer with a window corresponding to the gate portion, a first etching step of etching through the p-doped contact layer to the buffer layer with a reactive ion etching process, a second etching step of etching the buffer layer by a wet etching depth that is less than the thickness of the contact layer with a wet etching process, and passivating the surface of the buffer layer by oxygen-termination.

According to a third aspect of the invention, there is provided a method of manufacturing a diamond semiconductor field effect transistor, comprising: an n-doped diamond backing layer, a diamond buffer layer formed on the backing layer, p-doped source and drain diamond contact layer regions on the buffer layer or in the surface of the buffer layer opposite to the backing layer, the contact layer regions being spaced apart by a gate portion of the buffer layer by a gate length, a dielectric layer formed across the gate portion of the buffer layer and partially extending over the contact layer regions to form the diamond-dielectric interface, source and drain electrodes electrically contacting the contact layer regions, and a gate electrode is provided on the dielectric, wherein the gate portion of the buffer layer has a density of interface states of less than 2 x 1013 cm2, the method comprising forming the buffer layer on the backing layer, providing a selective area growth mask on the buffer layer that covers the gate region and has windows corresponding to source and drain contact layer regions, epitaxially growing the contact layer regions, and removing the growth mask.

The surface of the diamond in the gate portion, on which the dielectric is provided, may be an oxygen-terminated diamond surface.

The buffer layer may be a substantially intrinsic buffer layer and may have a thickness of less than half of the gate length.

The buffer layer may be a substantially intrinsic buffer layer and may have a thickness of iSto 25% of the gate length.

The buffer layer may be an n-doped buffer layer. The n-doped buffer layer may have a doping concentration of less than lxi 017 cm3, and preferably less than lxi 016cm3.

The contact layer regions may be delta doped contact layer regions.

The contact layer regions may have a thickness of 20 nm or less.

The contact layer regions may have a dopant concentration of 1 x i020cm3 or above.

The contact layer regions may have a dopant concentration of 1 x i021cm3 or above.

The surface of the diamond in the gate portion, on which the dielectric is provided, may be a wet-etched diamond surface.

A metal boride layer may be provided between the each contact layer region and the respective source or drain electrode.

A further p-doped layer may be provided between the each contact layer region and the respective source or drain electrode.

Each further p-doped layer may have a higher dopant concentration than each contact layer region.

Each further p-doped layer may be thicker than each contact layer region.

The wet etching depth may be 5 nm or less.

The wet etching process may be an oxidizing wet etching process and the surface passivation is produced by the wet etching process.

Exposed regions through windows in the growth mask may be etched by an oxidizing wet etch.

The growth mask may be removed by a reactive ion etch process.

The growth mask may be removed by a wet etch process.

The diamond surface in the gate region may be etched by an oxidizing wet etch process after the growth mask has been removed, which produces an oxygen terminated diamond surface in the gate region.

Advantageously, the n-doped backing layer or n-doped backing and buffer layers, shape the valence band adjacent the diamond-dielectric interface to provide a high level of carrier confinement against the interface. Beneficially this gives suppression of punch-through, in turn giving increased drain voltage handling, improved power efficiency, improved on-off switching ratio, and reduced off-state leakage current.

Beneficially it also provides reduced output conductance, which enables simpler control circuit design and improved RF performance.

Advantageously the wet-etched surface of the diamond buffer layer at the diamond-dielectric interface produces an interface with a low level of thermally and electrically stable interface states.

The doped contact regions are of sufficient thickness that they form a low sheet resistance access region to the channel in the diamond, at the diamond-dielectric interface, in the gate region.

Advantageously, the delta layer contact layer regions provides a high concentration of carriers in the adjacent buffer layer, which are localised beneath the contact layer regions when the device is in the off-state, and which flow through an ohmic contact into a channel in the diamond adjacent the diamond-dielectric interface in the on-state, where an inversion region is formed, providing a channel with high carrier mobility.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are further described hereinafter with reference to the accompanying drawings, in which: * Figure 1 shows a prior art FET having a delta doping layer and adjacent intrinsic layer formed on a substrate; * Figure 2 shows a prior art FEE having an intrinsic channel formed between bulk contact regions; * Figures 3A and 3B show a first FET according to the present invention; and * Figure 4 shows a second FET according to the present invention.

DETAILED DESCRIPTION

In the described embodiments, like features have been identified with like numerals, albeit in some cases having increments of integer multiples of 100 and typographical marks (e.g. primes). For example, in different figures, 100, 200, 300, 300' and 400 have been used to indicate an FET.

Figure 3A illustrates a diamond field effect transistor (FET) 300 according to a first embodiment of the present invention.

The FET 300 comprises an n-doped diamond backing layer 330 (e.g. substrate), a substantially intrinsic (not intentionally doped) diamond buffer layer 332, 5-20 nm thick highly p-doped (e.g. ptt-doped with greater than 1 x 1021 cm3 boron, being a density such that a substantial proportion of the dopants are activated) diamond contact layer regions 310S and 310D, a dielectric layer 318, source and drain electrodes 312 and 314 which provide ohmic contacts, and a gate electrode 320.

The diamond backing layer 330 is a diamond substrate, which may be formed by known means, such as high pressure, high temperature manufacturing or growth by chemical vapour deposition (CVD). The backing layer 330 has n-type doping (e.g. nitrogen or phosphorous doped diamond) with a concentration of 5 x 1016 cm3 to 5 x 1017 cm3.

The intrinsic diamond buffer layer 332 is grown onto the substrate 330 by CVD, and advantageously has low levels of impurities, to provide high charge carrier mobility in the gate portion 334 of the buffer layer. The surface of the diamond at the diamond-dielectric interface 336 in the gate region 334 has a low density of interface states, as a result of surface preparation by a wet etch which produces an oxygen-terminated surface, after the main reactive ion etch that patterns the contact layer to define the source and drain contact layer regions 310S and 310D.

The diamond contact layer regions 310S and 310D have a boron dopant concentration of over lxi 021 cm3.

The length L of the gate region 334 is between lOOnm and 1pm. Although the surface of the intrinsic buffer layer 332 has been shown with a recess in the gate region 334, this has been accentuated for the purposes of clarity. In practice the recessing would be small or substantially zero. The thickness T of the intrinsic buffer layer 332 within the gate region 334 is less than half of the length L of the gate region, and preferably about one fifth (e.g. 15 to 25%) of the length L of the gate region. E.g. in the case of a 250 nm long gate region 334, the intrinsic buffer layer 332 within the gate region is about 50 nm.

The dielectric layer 318 is a 64nm thick atomic layer deposited (ALD) aluminium oxide (A1203) dielectric. The dielectric may have a thickness of between 2 and nm. Alternatively, other dielectrics may be used, such as Si3N4, Hf02 and Zn02.

The gate electrode 320 is aluminium, and overlaps the edges of the contact layer regions 310, such that no part of the diamond surface is left electrically free-floating.

The source and drain electrodes 312 and 314 are provided by TiAu metallisation.

In operation, the FET 300 is normally off, with holes (positive carriers) present in the buffer layer 332 adjacent the interface with the contact layer regions 31 OS and 301 D, and no substantial concentration of holes present in the gate region 334. However, when a sufficient positive bias is applied to the gate 320 to bend the valence band in the gate region 334 of the buffer layer 332 adjacent the diamond-dielectric interface 336, until it is above the Fermi level in the source contact layer region 310S, adjacent the interface with the dielectric 318, an inversion region with a high density of holes is formed against the dielectric, in the gate region, which provides a conduction channel 338 beneath the gate with a high density of carriers. The channel 338 has high hole mobility, and provides an FET 300 with high frequency and power performance.

A first method of fabrication: After a layer of highly p-doped diamond contact layer has been deposited on the buffer layer, a mask is provided with a window corresponding to the gate region 334.

A first etching step uses reactive ion etching to etch through the contact layer to define the contact layer regions 310S and 310D at a high etch rate to etch a depth dd. Following the reactive ion etching step, a second etching step uses a slow wet etching process to make a shallow etch of depth d (d c dd) to remove surface damage left by the bombardment of high energy ions during reactive ion etching step.

The reactive ion etch uses a C12/Ar plasma to etch through the contact layer (e.g. 5-nm).

The oxidizing wet etch uses a 210°C H2S04/KN03 etch solution to etch away a lesser depth (e.g. 4 nm or less), to remove the surface region that has been damaged by the reactive ion etch stage. The wet etch is strongly oxidising, and produces an oxygen-terminated diamond surface (i.e. the surface carbon bonds are passivated with oxygen) with a low density of interface states.

Deposition of the source and drain electrodes 312 and 314 through a mask occurs at a convenient stage in the process, and may require annealing. Then the dielectric 318 is deposited and patterned with a mask followed by reactive ion etching to open a window to the contact region. The gate electrode 320 is deposited through a further mask to complete the gate region 334. The gate electrode 320 overlaps the contact layer regions 3105 and 310D to maintain electrical control across the full width of the device.

Alternatively, a second method of fabrication advantageously minimizes the depth of recess of dielectric in the gate region: A growth mask material is deposited on the buffer layer (which has previously been formed on the backing layer 330), for example being a 30-100 nm thickness of Si3N4.

An etch mask (e.g. patterned photoresist) is provided on the growth mask material, and the growth mask material is then patterned by a reactive ion etch process to form a selective area growth mask, which leaves the gate region covered, and which exposes windows in the growth mask material corresponding to the contact layer regions 310S and 310D. Shallow recesses (e.g. <5 nm) in the buffer layer may be formed through the windows in the etch mask. Any residual etch mask is removed.

An oxidizing wet etch described above (210°C H2S04/KNO3 etch solution) may optionally be used to remove plasma etch damage in the exposed buffer layer, through the windows in the growth mask.

The contact layer regions 310S and 310D are formed by epitaxial deposition of highly p-doped CVD diamond.

The growth mask is then removed. For example the growth mask may be removed by an HF acid or hot phosphoric acid step. Alternatively, the growth mask may be removed by a reactive ion etch process. Following removal of the growth mask, particularly following removal by the reactive ion etch process, the wet oxidizing etch may be used to remove damaged surface material, particularly in the gate region, in order to minimize the number of interface traps at the diamond-dielectric interface 336, by providing passivation of the diamond surface by oxygen termination.

The dielectric 318, gate electrode 320, and source and drain electrodes 312 and 314 are provided as before.

The FET 300' of Figure 3B differs from that of Figure 3A by the provision of a low resistance metal boride layer 344 (e.g. titanium boride) on the contact layer regions 310S' and 310D', which provides a lower access resistance between the source and drain electrodes 312 and 314 and the channel 338 in the gate region 334. In this case the contact layer regions 310S' and 31 OD' may be thinner than in Figure 3A, as the boride layer reduces the access resistance from the source and drain electrodes 312 and 314 to the channel 338 (i.e. like an electrical shunt to the boron doped layer 310S' and 310D').

Alternatively, or additionally, p-doped regions having a higher dopant concentration than the contact layer regions 310S' and 310D' may be provided on the contact regions, to provide a lower access resistance between the source and drain electrodes 312 and 314 and the channel 338 in the gate region 334.

Figure 4 illustrates a diamond field effect transistor (FEE) 300 according to a second embodiment of the present invention.

The FET 400 of Figure 4 differs from the FET 300 of Figure 3 in that the diamond buffer layer 432 is n-doped, in addition to the n-doped diamond backing layer 430.

The n-doped buffer layer has a doping concentration of less than 1 x 1016 cm3. The presence of n-type dopants in the buffer layer 432 may increase associated scattering mechanisms within the channel. However, advantageously this provides a deeper potential well to confine the carriers of the channel closer to the diamond-dielectric interface, minimizing disadvantageous short channel effects such as punch-through of current in the gate region.

The backing layer 430 and the buffer layer 432 are both n-type doped (e.g. nitrogen or phosphorous dopants), with doping concentrations of 1 x 1015 cm3 to 2 x 1017cm3.

The figures provided herein are schematic and not to scale.

Throughout the description and claims of this specification, the words "comprise" and "contain" and variations of them mean "including but not limited to", and they are not intended to (and do not) exclude other moieties, additives, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims

<claim-text>CLAIMS1. A diamond semiconductor field effect transistor, comprising: an n-doped diamond backing layer, a diamond buffer layer formed on the backing layer, p-doped source and drain diamond contact layer regions on the buffer layer or in the surface of the buffer layer opposite to the backing layer, the contact layer regions being spaced apart by a gate portion of the buffer layer by a gate length, a dielectric layer formed across the gate portion of the buffer layer and partially extending over the contact layer regions to form the diamond-dielectric interface, source and drain electrodes electrically contacting the contact layer regions, and a gate electrode is provided on the dielectric, wherein the gate portion of the buffer layer has a density of interface states of less than 2 x 1013 cm2.</claim-text> <claim-text>2. A transistor according to claim 1, wherein the surface of the diamond in the gate portion, on which the dielectric is provided, is an oxygen-terminated diamond surface.</claim-text> <claim-text>3. A transistor according to claims 1 or 2, wherein the buffer layer is substantially intrinsic buffer layer and has a thickness of less than half of the gate length.</claim-text> <claim-text>4. A transistor according to claim 3, wherein the buffer layer is substantially intrinsic buffer layer and has a thickness of 15 to 25% of the gate length.</claim-text> <claim-text>5. A transistor according to claims 1 or 2, wherein the buffer layer is an n-doped buffer layer.</claim-text> <claim-text>6. A transistor according to any preceding claim, wherein the contact layer regions are delta doped contact layer regions.</claim-text> <claim-text>7. A transistor according to any preceding claim, wherein the contact layer regions have a thickness of 2Onm or less.</claim-text> <claim-text>8. A transistor according to any preceding claim, wherein the contact layer regions have a dopant concentration of 1 x 1020 crri3 or above.</claim-text> <claim-text>9. A transistor according to claim 6, wherein the contact layer regions have a dopant concentration of 1 x 1021 cm3 or above.</claim-text> <claim-text>10. A transistor according to any preceding claim, wherein the surface of the diamond in the gate portion, on which the dielectric is provided, is a wet-etched diamond surface.</claim-text> <claim-text>11. A transistor according to any preceding claim, wherein a metal boride layer is provided between the each contact layer region and the respective source or drain electrode.</claim-text> <claim-text>12. A transistor according to any preceding claim, wherein a further p-doped layer is provided between the each contact layer region and the respective source or drain electrode.</claim-text> <claim-text>13. A transistor according to claim 12, wherein each further p-doped layer has a higher dopant concentration than each contact layer region.</claim-text> <claim-text>14. A transistor according to claim 12 or 13, wherein each further p-doped layer is thicker than each contact layer region.</claim-text> <claim-text>15. A method of manufacturing a diamond semiconductor field effect transistor, comprising: an n-doped diamond backing layer, a diamond buffer layer formed on the backing layer, p-doped source and drain diamond contact layer regions on the buffer layer or in the surface of the buffer layer opposite to the backing layer, the contact layer regions being spaced apart by a gate portion of the buffer layer by a gate length, a dielectric layer formed across the gate portion of the buffer layer and partially extending over the contact layer regions to form the diamond-dielectric interface, source and drain electrodes electrically contacting the contact layer regions, and a gate electrode is provided on the dielectric, wherein the gate portion of the buffer layer has a density of interface states of less than 2 x 1013 cm2, the method comprising forming the buffer layer on the backing layer, forming a p-doped contact layer on the buffer layer, providing an etch mask on the contact layer with a window corresponding to the gate portion, a first etching step of etching through the p-doped contact layer to the buffer layer with a reactive ion etching process, a second etching step of etching the buffer layer by a wet etching depth that is less than the thickness of the contact layer with a wet etching process, and passivating the surface of the buffer layer by oxygen-termination.</claim-text> <claim-text>16. The method according to claim 13, wherein the wet etching depth is less than 5nm.</claim-text> <claim-text>17. The method according to claims 13 or 14, wherein the wet etching process is an oxidizing wet etching process and the surface passivation is produced by the wet etching process.</claim-text> <claim-text>18. A method of manufacturing a diamond semiconductor field effect transistor, comprising: an n-doped diamond backing layer, a diamond buffer layer formed on the backing layer, p-doped source and drain diamond contact layer regions on the buffer layer or in the surface of the buffer layer opposite to the backing layer, the contact layer regions being spaced apart by a gate portion of the buffer layer by a gate length, a dielectric layer formed across the gate portion of the buffer layer and partially extending over the contact layer regions to form the diamond-dielectric interface, source and drain electrodes electrically contacting the contact layer regions, and a gate electrode is provided on the dielectric, wherein the gate portion of the buffer layer has a density of interface states of less than 2 x 1013 cm2, the method comprising forming the buffer layer on the backing layer, providing a selective area growth mask on the buffer layer that covers the gate region and has windows corresponding to source and drain contact layer regions, epitaxially growing the contact layer regions, and removing the growth mask.</claim-text> <claim-text>19. The method of claim 18, wherein exposed regions through windows in the growth mask are etched by an oxidizing wet etch.</claim-text> <claim-text>20. The method according to claims 18 or 19, wherein the growth mask is removed by a reactive ion etch process.</claim-text> <claim-text>21. The method according to claims 18 or 19, wherein the growth mask is removed by a wet etch process.</claim-text> <claim-text>22. The method according to claims 20 or 21, wherein the diamond surface in the gate region is etched by an oxidizing wet etch process after the growth mask has been removed, which produces an oxygen terminated diamond surface in the gate region.</claim-text> <claim-text>23. A diamond semiconductor field effect transistor substantially as hereinbefore described with reference to the accompanying description and any one of Figures 3a, 3b and 4.</claim-text> <claim-text>24. A method of manufacturing a diamond semiconductor field effect transistor substantially as hereinbefore described with reference to the accompanyingdescription and any one of Figures 3a, 3b and 4.</claim-text>