GB2493798A - A fractional PLL frequency synthesizer employing 1-bit delta-sigma modulation with distributed error feedback - Google Patents

Abstract

A fractional PLL frequency synthesizer employing 1-bit delta-sigma modulation with distributed error feedback Delta-sigma modulators are widely used in fractional PLL synthesizers in radio tuners.  Distributed error feedback 125,127,129 relocates transmission  zeros of the noise transfer function (NTF) from the point z=1 (0 Hz) to conjugate points near z=1 on the unit circle in the z-plane. By locating a pair of conjugate zeros of a third order sigma-delta modulator near the edge of the PLL €™s loop bandwidth, the PLL modulation noise floor is flattened within the loop bandwidth and the maximum noise floor is reduced by 2-3 dB. The technique is beneficial to the design of a fractional PLL, either by improving the noise floor of a stable signal carrier, or when directly modulating the carrier within the loop bandwidth for continuous phase/frequency modulation using the frequency control word as the modulation input.

Description

Description

L Technical field of the Invention control the frequency division ratio so as to reshape the noise floor over the PLL bandwidth (Fig.]).

The invention i-elates to Fractional PLL that employs a single bit Delta-Sigma modulation scheme for The basic PLL structure is shown in the upper frequency and modulation control, in particular to section (150) of Fig. I. The VCO output signal Ho apply distributive error feedback to the Delta-Sigma (161) is divided down by the multi-module modulation scheme. The new scheme could reassign prescaler(154) N times to compare with a frequency the zeros of the NTF away from z=I ( DC) on the reference Ui (156). The low pass filtered phase error z-plane to a complex conjugate location close by the of the 2 signals (159) is to be used in a negative edge of the modulation bandwidth / PLL loop feedback loop to control the VCO (160) so as to bandwidth. This will reduce the maximum force the two signals to be in phase.

modulation noise at the edge of the bandwidth, and Ho /N = Hi. or fo/N=fref flatten the inband noise floor. The carrier signal to noise and modulation signal to noise ratio could be In most of the application, the reference frequency is improved by 2-3dB. This technique is suitable to be chosen to be the channel spacing of the RF system, applied to the design of Fractional PLL that generate so that the channel could be selected by just altering stable catTier signal with tine programmable the division ratio N (Integer PLL).

frequency steps or signals of continuous fref = channel spacing phase/frequency modulation within the PLL loop bandwidth. In the 2T case, signal could be Channel Carrier = N K fref (N is integer) modulated onto the signal carrier directly from the fractional frequency division control word. The frequency accuracy obtainable depends on the PLL loop bandwidth and the number of phase 11. Background of Invention comparison over the lock in cycle. The lock in time should be>> than the period of the reference signal Delta-Sigma modulator converts an analog signal / Tref=l/fref.

multi-bit data into a single bit data stream, the time average of which equals the onginal signal/data [1]. In case there is a requirement that the frequency adjustment is smaller then fref, one simple option is In UK patent application No:GBI 114269.2, a new to continuously alter the prescaler division ratio N -A modulation scheme is proposed ( Fig 10) -In a between 2 integer values N and N-i-I where single bit distributive feedback E-A modulation loop, the error in quantization, obtained from the fs/(N+1) <fref < fs/N.

difference of the input and output of the quantizer, is the output of the phase detector will be low pass multiplied by a small gain factor and feedback to filtered by the loop filter and the VCO frequency the summation points of each integrator in the loop, value will lie in between the 2 steady cases The modified architecture has advantage that the transmission zeros and poles of the NTF could be N frefc fo c (N +1) * fref.

designed independently with the error feedback In general, switching the division ratio N by n I coefficients and quantization feedback coefficients. penods and division ratio N+l by n2 penods. The In particularly, the transmission zeros of the NTE output frequency will be could be located away from zero frequency on the unit circle of the z-plane, either a wider region of fo -fref * (ni + n2) / n I / N + n2 / (N+1) 1 (1) low quantization noise region is resulted around zero A better noise performance could be obtained if the frequency or a separated frequency band of low total number of ni and n2 remain the same, but the 2 quantization noise can be formed. This feature can division ratio events to be randomised. A well be exploited by implementing the proposed A established technique: A-modulation scheme could modulation scheme in fractional PLL synthesizer to be able to generate the required randomised bit stream from the fractional word for the purpose.

The arrangement of the PLL prescaler is such that an B! Cascaded integration loop with single bit output integer word control the selection of the value of N. and a I bit data stream control the prescaler to be Fig. 3 shows a PLL using a 3" order cascaded operating as div N or div N+k, where k is an integer integration ioop E-A modulator. The transfer function call be summarized as between -3 and 3. The PLL itself is doing the timing average (low pass filter) of the events over the loop X bandwidth. Y = This is a general principle of the design of the (z-I)3 + a3(z-1)2 + a2(z-I) + a1 Fractional PLL Frequency Synthesizer. c * There are several A-Z modulation structures -4-(6) commonly used in the fractional PLL synthesizers. z1)2 + a3(z-l)2 + a2(z-l) + a1 They are summarized in the following paragraphs. A distributive feedback of the output with Al MASH algorithm multiplication coefficient are designed to locate the poles of the transfer function to be inside the unit Fig. 2 summarised a 3 order MASH structure LA circle of the z-plane to meet the convergence modulator to control the frequency division ratio of requirement. The conversion error is proportional to the PLL loop. The conversion error a1 in a l order (z-l)3. Examples of such design could be found in -A modulator (203) is fed into another l order patents US2IXI2/0145472 and WO 98154840.

modulator (208), the conversion error a2 again is fed into another P order modulator (213) and so forth. There are also PLLs that use E-A modulation The result of the 1S1 modulator can be related to the scheme where a 2 order Cascade Integration loop input bit stream and the error as is combined with a]SI order loop using a MASH structure. Examples could be found in [2] and patent Y 1(z) = X(z) + a1 (1 -z') (2 IJS5,079,52I.

The signals in the 2 and 3rd modulators can be related as Cl E-A modulation scheme with FIR correction Y2(z) = -aj + g*(j -z') (3) Fig 4 summarised a modulation scheme employing Y3(z) = -a2 + a3(l -z4) (4) FIR/IIR en-or corrections. In contrast to the scheme mentioned in A and B, no integration (accumulator) The data of resuhed conversions are feedforward is used in the modulation loop. In the particular with compensation for delays in respective modulator and combined to give a final output. example, the signals in the modulation loop could be summarised as Y(z) = Yl(z) + (1 -z') * Y2(z) Y(z) = X(z) + a*(l -zj3 C) +0 -z)2 Y3(z) Examples of such design could be found in patents = X(z) + c*(l -z')3 (5) IJS4.800,342 and US 2003/0025565.

This results in a multi-order -A modulator, the All the above early algorithms have multiple zeros conversion en-or of which is given by (l-z1Y, z=i or DC in the noise transfer function, or where N is the number of modulators cascaded.

NTF -a*(lz7' (8) Examples are found in [I], and patent EP 0,125.790 A2 -The noise spectrum at low frequency could be The output of the MASH structure is the summation approximated by the N' power of the expression of several I bit data, so as to say a multi-bit data. nffl= a *2<(2T)*sin (wT/2Y (9) The PLL prescaler need to be a multi-module In another word, the error / quantization noise is divider that can handle divN, div(N+ I)."-,div(N+P) operations in respond to the final output of the proportional to the Nth power of frequency. PLL MASH modulator, loop filter at the output of the phase detector removes the high frequency noise outside the loop bandwidth. Within the loop bandwidth, low the zero of the NTF. ( The PLL structure was frequency signal will appear together with a mentioned in patent US 2002/0145472) quantization noise floor that is given by eq.(9).

The loop equation can be formulated as x The clear DC signal will generate the carrier, and the y = quantization noise will generate fm noise on the 2 { a1+a2tz-1) +a3[tz-1)2+gi] sides of the carrier, with a spectrum that is power of +a4(z-l)[tz-1)2+g1]--[tz-l)2+gl][-l)2+g2]} the deviation from the carrier. This will impose a degradation of the SNR at the edge of the loop 8[( z-lf+gij[(z-l)2+g2] bandwidth. To colTect the degradation, one option is + to increase the phase comparison speed ( or sample { ai+a2(z-1) +a3[z-I)2+gi] speed) of the PLL. However, a new generation of Z-A modulator introduces a new dimension to (12) improve the degradation -locate the zeros of the NTF in other than DC location, in particular at Assume gi, g2 c< 1, the NTF has complex zero at complex conjugate pair location near the edge of the z=1+i*gi, I -i'igt, I+i*lg2, Ii*gz loop bandwidth where the quantization noise And the poles of the STF and NTF are zeros of the normally peak. The redistribution of modulation polynominal noise will give a minimum around the zero position a1+a2(z-l)+az-1)2+a4(z-l)3 +(z-l)4 =0 and push the noise power to outside the loop band to be filtered by the low pass loop filter. The following The poles could be designed according to well defined LPF. eg: Butterworth, and the 4 complex paragraphs describe the present art of PLL that employ Z-A modulators having zero of the NTF zeros to be chosen close to the zeros of inverted locate at complex conjugate positions other than Chebyshev II filter. z= 1.

The NTF has more uniform noise floor spectrum inside the signal pass band, instead of the monotonic DI Modification of the MASH with frequency: NTF (wI w.

The Pt order converter ( 513 of Fig. 5) in the final stage of the MASH structure could be modified to introduce a pair of conjugate zero to its NTF. The F! FIRIIIR compensation signals in the final stage could be summarized as: Y3(z) = -81 + *(Ikz+z2) (lo) Fig. 7 shows a E-A loop employing EIRIIIR structure in the feedback path to introduce complex The output could then be given as poles in the feedback path, thereby produces a pair Y(z) =X(z)+c*(lz *(lkzH+z2) (11) of complex zero in the NTF. This will help to improve the modulation noise floor around the edge By choosing kc2, a pair of conjugate zero will be of the signal bandwidth. The transfer function of introduced in the NTF together with 2 zero at z=l. the loop could be summarized as patent WO 03/028218, similar technique but not Y(z) = X(z)*z" -4-identical could also be found in patent USo.069.535).

c*( I +K0'z'+Kj *z2+K2*z3 +K;*z4) (13) El Local feedback in Cascade Integration Loop The coefficients K's are chosen such that the NTF -A modulation scheme in Fig 3 emp'oying cascade could appear as the following form: integration with single bit quantization and distributive feedback can be modified to include NTF (14) local feedback Fig6. This will add complex pairs to (Detail described in patent US 2006/001751 III. OBJECT OF INVENTION IV. Sumiflary of Invention Fractional PLL synthesizer structure that uses The invention is a modification of the cascade cascaded integration -A modulation with single bit integration E-A modulation loop used in Fractional quantizer is well known for its ease of PLL Frequency Synthesizer: the error in implementation and less prone to spurfl noise quantization, obtained from the 2's compliment of degradation. The object of the invention is to modify final stage of the accumulator, is shifted down by L the -A modulation scheme such that a pair of zero bits and feedback to the summation points of each in the noise transfer function NTF could be accumulator input in the loop ( Fig 1). hi this way, relocated from the z=l ( DC) location to a pair of a pair of complex conjugate zeros can be formed in complex conjugate zero on the unit circle of the z-the NTF of the modulation loop. The formulation of plane. By optimizing the location of the conjugate the transfer functions for 3' and 4Eh order loop are zero's position around the corner of the PLL summarized in the following paragraphs (described passband, a modulation noise minimum appears at in UK patent application No:GB1114269.2).

the location where it used to be the maximum of the Simplified diagram of the scheme are drawn in noise floor. Modulation noise power is pushed to Fig lOa and b.

further away from the edge of the loop passband and Al 3' order system (Hg. Ella) be attenuated by the loop filter. Part of the modulation noise power is pushed towards the signal The transfer function can be summarized as carrier, where it used to have a minimum. A proper balance could be obtained where the inband noise - floor is more or less constant over the PLL -bandwidth and have a reduced maximum noise (z-1) + a3(-l) + a4-l) + a1 floor (2-3dB). This technique is applicable to a c * (z-1) * [ (z-l) + c (z-l) -1-ci] PLL design for a stable signal carrier with a fine + (15) programmable step, as well as for a PLL design z-l1 + a3(z-1)2 + a2(z-l) + a1 where modulation signals with continuous phase/frequency trajectory having a bandwidth less The zeros of the NTF are located at than that of the PLL to be modulated onto the z = 1 carrier through the frequency control data word = 1-c1/2 ± V[ (c/2)2_ c2] (16) input to the Z-A modulator. if (c3 /2)2 c2< 0. then a pair of complex zero exist, Fig. 1 summarized a 311 order E-A loop with and the zeros are located on the unit circle of the z distributed error feedback and together with plane if c2 = c3, eg: a PLL structure with multi-module prescaler. let z1 = iii + f3 Fig. S summarized a 4* order -A loop with a pair (a1)2 + (f3)2= (I -c3/2)2 + c2 -(c3/2)2 of complex transmission zeros and pair of = I DC transmission zeros on the NTF.

Furthermore. if c, c3 <<I. then the complex zeros Fig. 9 summanzed the extra logic gates and are close by the DC or z1 -=1 connection for the implementation of the error feedback sinaI path.

B/ 4orderloop(FiglOb) Fig. 11 summarized the performance study of noise shaping function of the 3 order -A The transfer function can be summanzed as: modulator with and without distributive error feedback.

Fi.l2 summarized the noise floor of a 4! order -4 --PLL controlled by a 3 order -A modulator (z-1) + a4z-1Y + a3(z-1) + a2(z-l) + a1 with and without distributive error feedback c *(z lf* [(z-I)2 + c4 (z-1)+ c3] + (z-l)4 + a4z-1)3 + a3-l)2 + a(z-I) + a (17) Similar to the case A, if c4=c1, and c4, c ccl. then achieved and with a reduction of maximum noise the NTF has 2 zeros at z=l and a pair of complex floor of 2-3dB. Fig.II compares the NTF of a zeros on the unit circle close by 1. standard 3n1 order -A modulator and that with a complex conjugate zero. Figl2 compares the The implementation of the scheme to a 3 order resulted PLL noise floor of the synthesized cascaded integration E-A modulator for the PLL fractional frequency carrier signal.

application (Fig. 1) can be easily achieved by feedback the 2's compliment (quantizer error a) of The result shows that relocating the zeros of the the final accumulator (120), after a shift down of L NTF of the E-A modulator to a complex conjugate bits (125) (for a feedback coefficient of l/2L), to the location around z=l and close by the PLL inputs (110) of signal adders (108,116) in the 2md bandwidth could improve the noise floor of the PLL and 3rd stage. synthesizer. This is beneficial for the application of a stable signal carrier, or for the application of a The operation can further be simplified by continuous phase/frequency modulation signal combining the adder for the quantized bit feedback where the modulation bandwidth is about the order and the error data feedback together ( Fig. 9) . Let of the PLL bandwidth.

the input registrar of the adder(905) to be separated into 2 sections, an upper section of 8 bits for the integer value and a lower section of 16 bits for the fractional value. Normally the quantized bit V. Specific Description of the Embodiment feedback coefficients are integers 1< a1 < 256, and the error feedback coefficients are fraction values The preferred embodiment of the invention is shown c1c 1/28 (for transmission zeros close to z=l). Then Fig 1. The Fractional Frequency Synthesizer quantized bit (909), after multiplied by a1. will composed of 2 building blocks: phase lock loop always stay in the upper section of the registrar (150) and a 3 order digital Delta-Sigma Modulator structure. The error data (908), after shifted down by with distributive error feedback (100). The PLL 2L bits, will always stay in the lower section of the consists of a prescaler (154), which is controlled by registrar structure. The data / sign bit are set in the an integer division control word (151) to select the registrar input in 2's compliment format after the main division ratio N shift down/multiply operation. Only one input registrar (905) will combine the operation of N= floor( Fvco/Fref) (18) summing the quantized feedback (910) and the error Where Fvco and Fref are the frequency of the feedback (911). In this way, the addition of a few required signal and the reference signal.

simple logic gates and niultiplexers are required.

and the structure can be programmed to alter NTF Also the prescaler is controlled by a 1 bit control conjugate zero positions for different applications by signal (152) to select either to carry out div N or just altering the data shift down position. div N+k operation, where k =-3 to 3 is an integer selected by an internal registrar.

Fig. 9 summarized the simplified scheme and logic gates connection described using a1=4 and c1=1/21 as The prescaler takes an RF signal output( 161) from an example. the VCO (160), frequency divides by N or N+k and gives an output Fs (153) to one input of the An example of the study is given for a 3 order frequency phase detector (162). Another input of the modulator scheme employed in a 4th order PLL. PLL detector is the output signal Fref (156) of the loop bandwidth is optimized at 200Hz to give a frequency reference (155). The frequency phase carrier signal of 260MHz of 40Hz error using a detector will then produce a narrow current pulse phase detection frequency of 72KHz. The noise (157) proportional to the phase difference (Os -Ri) floor around the PLL passband had been compared between the 2 inputs. The cmTent pulse (157) will be with and without applying the distributive dm1 integrated and low pass filtered by the loop filter feedback to the E-A modulator. It is noticed that (158) with a filter character given by F(s). This carefully locating the complex zero locations around filtered output (1159) will be used to control the the edge of loop passband, a fiat noise floor could be frequency of the VCO (160) output signal Fvco( 161). This Fvco signal will be used as a adders is then the result of the operation a1*Y(z) + system output and also be feedback to the prescaler *2L (detail of circuit block is summarized in Fig.9).

for further phase adjustment. The feedback control A single step operation of the adder will carry out forces the Fvco signal, after divided down to Fs, to the quantized bit feedback and error feedback be always in phase with the reference signal Fref. procedure.

The signal Es (153) will also clock the delay The signal connection between the PLL block (150) elements in the Delta-Sigma Modulator (100). and Delta-Sigma Modulator (100) are summarized as below: The Delta-Sigma Modulator (100) composed of 3 accumulators, each is formed by a pair of adder The frequency control word, the integer part N of (106,113,120) and feedback registrar (i07,ll4,121) eq.i9 will be input to the integer div input (151) of to feed the corresponding output data back to one of the prescaler. The fractional part X of eq. 19 will be the adder's 2 inputs. The other input of the adder put to the input (101) of the Delta-Sigma Modulator will take on the signal to be accumulated. The (100).

adders can-ied out signed 24 bit (total of 25 bits operation. The lower 16 bit of the data bus is The synthesized output signal will be obtained from assigned to be the fractional part of the data, and the the ouput Fvco (161) of YCO (160). The output of upper 8 bits to be integer part of the data. A word the prescaler Fs (153) will be used to clock the delay elements in the Modulator block (100).

representing the fraction frequency to be synthesized is calculated base on the following relation: The output bit of the modulator Y(z) is the 2's Fvco = NFref -g.Fref (19a) compliment of signed bit (123) of the output of the final accumulator (120,121). Y(z) bits will be fed to X = ai2'g (19b) the prescaler fracbon control input (152) in the PLL block (150).

This word X is to be applied to the input (101) of the modulator (100). This completes the close loop operation of the 2 blocks.

Adder (103) subtracts the input X(z) by the quantized data ai*Y(z) and output (104) to the 1St accumulator (106, 107). Adder (108) subtracts the A 2nd alternative of the embodiment of the invention output (109) of the jSE accumulator by the quantized is a 4th order -A modulation loop shown in Fig. 8.

feedback (135) a1<Y(z) and add the error feedback data (110). and output (ill) to the 2 accumulator The word X given by eq.19 is to be applied to the (113, 114). Adder (116) subtracts the 2' input (801) of the modulator.

accumulator output (115) by the quantized feedback (117) a3*Y(z) and add the error feedback data (110), Adder (803) subtracts the input X(z) by the and output (118) to the 3td accumulator (120,121). quantized data ai*Y(z) and output (804) to the P The 2's compliment of sign bit (123) of the output accumulator (806, 808). Adder (810) subtracts the (122) of the accumulator is the quantized bit, and output (807) of the accumulator by the quantized the 2's compliment of remaining bits are the error feedback (809) a2*Y(z) and output (811) to the 2 accumulator (813, 815). Adder (817) subtracts the in quantization. output (814) of the 2 accumulator by the quantized The detail of performing the error feedback task is feedback (816) a3*Y(z) and add the error feedback summarized in this paragraph. The data bits (except data (843). and output (818) to the 3td accumulator the signed bit) of output of the final stage (820,822). Adder (824)subtracts the 3 accumulator accumulator (124) is shifted down by bits (126) output (821) by the quantized feedback (823) and inverted (128) to form an input word (110) to a4*Y(z) and add the error feedback data (843), and the lower part of the input registrar of adder (116) output (825) to the 4th accumulator (827,829). The and (108), The inverted signed bit output (137) is 2's compliment of the signed bit (830) of output multiplied by the integer feedback coefficients a2 (828) of the 4th accumulator is the quantized bit, and and a3 and set to the upper part of the input registrar the remaining bits are the error in quantization.

of adder (108. 116). The input registrar of the 2 The detail of performing the error feedback task is summarized in this paragraph. The data bits (except the signed bit) of output of the final stage accumulator (831) is shifted down by 21 bits (833) and inverted (836) to foim an input word (843) to the lower part of the input registrar of adder (817) and (824). The inverted signed bit output (845) is multiplied by the integer feedback coefficients a and a4 and set to the upper part of the input registrar of adder (817, 824). The input registrars of the 2 adders are then the result of the operation a*Y(z) c*2' (detail of circuit block is sunmiarized in Fig.9).

A single step operation of the adder will carry out the quantized bit feedback and error feedback procedure.

The interaction of this block with the PLL is the same as the preferred embodiment described in the previous paragraph.

S

List of Figures Fig. I Fractional PLL Frequency Synthesizer with Delta-Sigma Modulator Employing Cascade integration and distributive error feedback Fig. 2 Mash Sigma-Delia Modulator for Fractional PLL Fig. 3 Delta-Sigma Modulator employing Cascaded Integration for Fractional PLL Fig. 4 Sigma-Delta Modulator with FIR/lW Error Feedback structure for Fractional PLL Fig. 5 Mash Sigma-Delta Modulator with conjugate transmission zero Fig. 6 Delta-Sigma Modulator for Fractional PLL employing Cascaded Integration and local feedback to introduce zero in NTF Fig. 7 Sigma-Delia Modulator with FIR/hR feedback structure and have zero in NTF Fig. 8 4th order Delta-Sigma Modulator employing Cascaded Integration and r distributive error feedback LI') Fig. 9 Efficient implementation of the Quantisation Error Feedback Fig. 1 Oa 3"' order Delta-Sigma Modulator with Distributive Error Feedback ° Fig.lOb 4th order Delta-Sigma Modulator with Distributive Error Feedback Fig. I Ia Noise Transfer Function of 3"' order noise shaper without Error Feedback Fig. II b Noise Transfer Function of 3"' order noise shaper with Error Feedback Fig. 12 PLL modulation noise floor improvement -Optimizing the conjugate transmission zeros around the edge of loop BW