GB2469629A

GB2469629A - Synthesising a local oscillator waveform

Info

Publication number: GB2469629A
Application number: GB0906726A
Authority: GB
Inventors: James Murdoch
Original assignee: ITI Scotland Ltd
Current assignee: ITI Scotland Ltd
Priority date: 2009-04-20
Filing date: 2009-04-20
Publication date: 2010-10-27
Also published as: GB0906726D0

Abstract

Synthesising a waveform comprises generating a waveform having a predetermined frequency; generating a plurality of waveforms, each shifted by a different sequential number of cycles of a clock, from 0 to nmax-1 clock cycles, and combining at least two of the shifted plurality of waveforms to synthesise a waveform. The clock has a frequency Fref; and the predetermined frequency is at least less than Fref/2nmax. A clock frequency Fref can be selected by multiplexer 463 and divided by at least 2nmaxby divider 471 to generate the predetermined frequency that is fed to shift register 473 whose shifted output waveforms are combined by multiplexors 475, 483 and digital to analogue converters 493,495 to form in-phase and quadrature waveforms (figs 6f and 6g). A phase locked loop (fig 4, 401) circuit can generate different frequency signals that are mixed with the synthesised waveform, and selected by band multiplexers (fig 4, 427, 433). The waveform synthesized has low harmonics and is suitable for use with an Ultra Wide Band (UWB) system.

Description

METHOD AND APPARATUS FOR SYNTHESISING A WAVEFORM AND

METHOD AND APPARATUS FOR GENERATING A LO SIGNAL

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for synthesising a waveform and method and apparatus for generating a local oscillator (LO) signal. In particular, but not exclusively, it relates to synthesising a reduced harmonic waveform for generating a LO signal suitable for use in an Ultra Wide Band (UWB) system.

BACKGROUND OF THE INVENTION

UWB systems require that the LO signal can generate many different clock frequencies and be able to switch between these frequencies quickly.

Figure 1 is a schematic block diagram of known apparatus for generating a LO signal for an UWB system as disclosed, for example by Sandner et al, "A Wimedia/MBOA-Compliant CMOS RF Transceiver for UWB", IEEE ISCC Digest of Technical papers, volume 49, pp122-123, 2006.

The apparatus comprises a phase-locked loop circuit 101 having an input connected to a reference frequency signal fref and an output connected to the input of a divider 103.

The output of the divider 103 is connected to an 1-ROM 105, an 1-DAC 107 and a first single side band (SSB) mixer 109 of an I-channel 125. The output of the divider 103 is also connected to a Q-ROM 111, a Q-DAC 113 and a second SSB mixer 115 of a 0-channel 127. The 1-ROM 105 and the Q-ROM 111 comprise respective input terminals 129, 131 connected to receive a hop control signal.

The 1-ROM 105 and the Q-ROM 111 are connected to its respective 1-DAC 107 and Q-DAC 113. The outputs of the 1-DAC 107 and the output of the Q-DAC 113 are connected to respective inputs of the first SSB mixer 109 and to respective inputs of the second SSB mixer 115. The output of the first SSB mixer 109 is connected to the input of first and second buffers 117, 119 of transmit and receiver channels of the I-channel 125. The output of the second SSB mixer 115 is connected to the input of first and second buffers 121, 123 of transmit and receiver channels of the Q-channel 127.

In operation, the phase-locked loop circuit 101 generates an output signal of 8.448GHz. This signal is input into the divider 103 halving the frequency and generating an output signal of 4.224GHz. This signal is then provided to the 1-ROM 105 and the 1-DAC 107 and the first SSB mixer 109, the Q-ROM 111, the Q-DAC 113 and the second SSB mixer 115.

The 1-DAC 107 and the Q-DAC 113 comprise current-steering 4-bit DACs running at the sample rate of 4.224GHZ output from the divider 103. The l-DAC 107 and the 0-DAC 113 generate 3 waveforms having frequencies of � 264MHz and -792MHz. The digital code required to generate these lIQ waveforms are stored in respective 1-ROM 101 and Q-ROM 111 in the form of a lookup table.

One of the stored waveforms in each channel 125, 127 is selected by the hop control signal and output to the respective first and second single side band mixers 109, 115 via the l-DAC 107 and Q-DAC 113. This is then mixed with the output of the phase-locked loop circuit 101 to generate an output waveform (LO signal) having frequencies of 3.432 GHz, 3.960GHz or 4.488GHz required by the UWB system.

The LO signals generated by the apparatus of Figure 1 are buffered and transferred to the respective transmit and receiver channels of the I-channel 125 and the Q-channel 127.

Figure 2(a) illustrates the waveforms generated by a conventional switching mixer commonly used in RF transceivers. The baseband signal is mixed (effectively multiplied) with a square-wave L02 signal. The resulting unconverted signal comprises a plurality of baseband signals located at odd multiples (harmonics) of the LO frequency. Typically a high-Q filter is needed to attenuate these harmonics.

Alternatively a Harmonic-Rejection Mixer signal as disclosed by Weldon et al, "A 1.75-GHz Highly Integrated Narrow-Band CMOS Transmitter With Harmonic-Rejection Mixers", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 may be used. These are generated as shown for example in Figure 2(b). The baseband signal is multiplied with a 3-bit, amplitude-quantized sinusoid signal fLOh (t). As a result, the third and fifth harmonics are rejected as shown in Figure 2(b). Because the first harmonic of fLQ2h (t) is located at seven times the fundamental frequency, the first significant copy of the unconverted baseband signal is also located at seven times the fundamental frequency. This harmonic is usually at a reasonably low power and can be more easily filtered out. fLQ2h (t) is generated by adding three square waves as shown in Figure 3.

SUMMARY OF THE INVENTION

The present invention seeks to provide simplified synthesis of a low harmonics waveform and provide a LO signal generated with the correct frequency and phase suitable for use with required UWB frequency having reduced harmonic content.

This is achieved according to a first aspect of the present invention by a method of synthesising a waveform, the method comprising the steps of: generating a waveform having a predetermined frequency; generating a plurality of shifted waveforms, each waveform shifted by a different sequential number of cycles of a clock, the sequence of number of clock cycles being from 0 to umax -1 and the clock having a clock frequency fref combining at least two of the shifted plurality of waveforms to synthesise a waveform; wherein the predetermined frequency is at least less than ff/2flmax This is also achieved according to a second aspect of the present invention by a waveform synthesiser comprising: means for generating a waveform having a predetermined frequency; means for generating a plurality of shifted waveforms, each waveform shifted by a different sequential number of cycles of a clock, the sequence of number of clock cycles being from 0 to nmax -1 and the clock having a clock frequency fref means for combining at least two of the shifted plurality of waveforms to synthesise a waveform; wherein the predetermined frequency is at least less than Jref/2flmax The synthesiser can be simplified to generate a waveform having reduced harmonics content. Further, as the frequency of the synthesised waveform is determined from the shift parameters of the shifting means i.e. the number of clock cycles. The frequency and the phase of the synthesised waveform can be quickly changed making the synthesised waveform particularly suitable for mixing in a UWB system due to the simplified implementation to synthesise the waveform, for example, the synthesised waveform maybe realised by two multiplexing stages.

This is also achieved according to a third aspect of the present invention by a method of generating a local oscillator signal, the method comprising the steps of: generating a plurality of phase-locked loop signals, each having a different frequency; synthesising a waveform according to the first aspect above in phase with the plurality of phase-locked loop signals; mixing the synthesised waveform with each of the phase-locked loop signals; selecting one of the plurality of mixed signals for a local oscillator signal output.

This is also achieved according to a fourth aspect of the present invention by a method of generating an in-phase local oscillator signal and a quadrature local oscillator signal, the method comprising the steps of: generating a plurality of in-phase phase-locked loop signals, each having a different frequency; generating a plurality of quadrature phase-locked loop signals, the frequency of each of the plurality of quadrature phase-locked loop signals corresponding to the frequency of each of the plurality of in-phase phase-locked loop signals; synthesising an in-phase waveform, according to the method of the first aspect above, in phase with the plurality of in-phase phase-locked loop signals; synthesising a quadrature waveform, according to the first aspect above, in phase with the plurality of quadrature phase-locked loop signals; mixing the synthesised in-phase waveform with each of the in-phase phase-locked loop signals; mixing the synthesised quadrature waveform with each of the quadrature phase-locked loop signals; selecting one of the plurality of mixed in-phase signals for an in-phase local oscillator signal output; and selecting one of the plurality of mixed quadrature signals for a quadrature local oscillator signal output.

This is also achieved according to a fifth aspect of the present invention by apparatus for generating a local oscillator signal, the apparatus comprising: a phase-locked loop circuit for generating a plurality of phase-locked loop signals, each having a different frequency; a synthesiser, according to the second aspect above, for synthesising a low harmonic waveform in phase with the plurality of phase-locked loop signals; a plurality of mixers for mixing the synthesised low harmonic waveform with each of the phase-locked loop signals; a multiplexer for selecting one of the plurality of mixed signals for a local oscillator signal output.

This is achieved according to a sixth aspect of the present invention by apparatus for generating an in-phase local oscillator signal and a quadrature local oscillator signal, the apparatus comprising: a phase-locked loop circuit for generating a plurality of in-phase phase-locked loop signals, each having a different frequency and a plurality of quadrature phase-locked loop signals, the frequency of each of the plurality of quadrature phase-lock loop signals corresponding to the frequency of each of the plurality of in-phase phase-locked loop signals; a synthesiser according to the second aspect above for synthesising an in-phase low harmonic waveform in phase with the plurality of in-phase phase-locked loop signals and synthesising a quadrature low harmonic waveform in phase with the plurality of quadrature phase-locked loop signals; a plurality of mixers for mixing the synthesised in-phase low harmonic waveform with each of the in-phase phase-locked loop signals and mixing the synthesised quadrature low harmonic waveform with each of the quadrature phase-locked loop signals; a first multiplexer for selecting one of the plurality of mixed in-phase signals for an in-phase local oscillator signal output; and a second multiplexer for selecting one of the plurality of mixed quadrature signals for a quadrature local oscillator signal output.

The resulting synthesised low harmonic waveforms can be mixed with phase-locked loop signals to generate the many different clock frequencies required by a UWB

system, for example.

The clock frequency may be selectable. The waveform having a predetermined frequency may be generated by dividing the clock by a number equal to at least fref/2hlmax. The plurality of shifted waveforms may be formed by shifting the generated waveform by 0 clock cycle; and shifting each subsequent shifted waveform by an additional clock cycle to n -1 clock cycles. For example, umax �= 4 and wherein at least 4 shifted waveforms are generated.

At least two of the shifted plurality of waveforms to synthesise a waveform may be combined by combining at least an inverse of the generated waveform shifted by 3 clock cycles, the generated waveform shifted by 0 clock cycles and the generated waveform shifted by 1 clock cycle to generate a first synthesised waveform and/or by combining at least the generated waveform shifted by 2 clock cycles, the generated waveform shifted by 1 clock cycles and the generated waveform shifted by 3 clock cycles to generate a second synthesised waveform.

The resulting combined waveform has 3 and 5th harmonics suppressed and one component of the waveform is multiplied by si. Thus the synthesised waveform has reduced harmonic content. The synthesiser for synthesising such a waveform is simplified.

The synthesiser may generate an in-phase synthesised waveform and a quadrature synthesised waveform such that signal an in-phase LO signal and a quadrature LO signal may be generated. As a result I and 0 phase matching is linked to input clock.

The improved I and 0 phase matching meets UWB system requirements.

BRIEF DESCRIPTION OF DRAWINGS

For a more complete understanding of the present invention, reference is made to the following description in conjunction with the accompanying drawings, in which: Figure 1 is a simple schematic block diagram of a known apparatus for generating an LO signal; Figure 2(a) illustrates the waveforms generated by a conventional switching mixer commonly used in RF transceivers; Figure 2 (b) illustrates the waveforms for generating a harmonics-rejection mixer signal; Figure 3 illustrates generation of a harmonics-rejection mixer signal; Figure 4 is a simple schematic block diagram of apparatus for generating a LO signal according to an embodiment of the present invention; Figure 5 is simple schematic block diagram of the waveform synthesiser of the apparatus of figure 4; and Figures 6(a) to (g) illustrate the waveform outputs at stages of the waveform synthesiser of Figure 5.

DETAILED DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

The apparatus 400 for generating a LO signal, according to an embodiment of the present invention, is shown in Figure 4. The apparatus 400 comprises a phase-locked loop circuit 401 connected to a reference clock 403. The phase-locked loop circuit 401 comprises a plurality of I-output terminals 405 and a plurality of Q-output terminals 407.

Each of the plurality of I-output terminals 405 and the plurality of Q-output terminals 407 provide an output signal of different frequencies. In the particular embodiment of Figure 4, the phase-locked loop circuit 401 comprises 3 I-output terminals 405 and 3 0-output terminals 407. The first I-output terminal 406_i and the first Q-output terminal 408_i output a signal having a frequency of 2.112 GHz. The second I-output terminal 406_2 and the second 0-output terminal 408_2 output a signal having a frequency of 8.448 GHz. The third I-output terminal 406_3 and the third Q-output terminal 408_3 output a signal having a frequency of 4.224 GHz.

The first I-output terminal 406_i is connected to a first input of a first mixer 409 and a first input of a second mixer 411. The second I-output terminal 406_2 is connected to a second input of the first mixer 409 and a second input of the second mixer 411. The first Q-output terminal 408_i is connected to first input of a third mixer 413 and a first input of a fourth mixer 415. The second Q-output terminal 408_2 is connected to a second input of the third mixer 413 and a second input of the fourth mixer 4i 5.

The output of the first mixer 409 and the third mixer 4i3 are connected to respective inputs of a first SSB mixer 417_i. The second I-output terminal 406_2 and the second Q-output terminal 408_2 of the phase-locked loop circuit 401 are connected to respective inputs of a second SSB mixer 417_2. The output of the second mixer 411 and the fourth mixer 415 are connected to respective inputs of a third SSB mixer 41 7_3. The third I-output terminal 406_3 and the third Q-output terminal 408_3 of the phase-locked loop circuit 401 are connected to respective inputs of a fourth SSB mixer 4i7_4. Input terminals 419_i to 4i9_4 and 421_i to 421_4 of each of the SSB mixers 417_i to 4i7_4 are connected to the first and second output terminals 497, 499 of a waveform synthesiser 461.

A first output of each of the SSB mixers 417_i to 4i7_4 is connected to first input terminals 425_i to 425_4 of a first band multiplexer 413. A second output of each of the SSB mixers 417_i to 417_4 is connected to second input terminals 435_i to 435_4 of a Q-multiplexer 433. A terminal 427 of the first band multiplexer 423 is connected to receive a band selection signal. A terminal 437 of a second band multiplexer 433 is connected to receive the band selection signal via a terminal 431 of the first band multiplexer 423. Alternatively, the band selection signal is connected directly to the terminal 437 of the second band multiplexer 433. The output terminal 429 of the first band multiplexer 423 is connected to a first output terminal 441 of the apparatus 400.

The output terminal 439 of the second band multiplexer 433 is connected to a second output terminal 443 of the apparatus 400.

The waveform synthesiser 461 will be described in more detail with reference to Figures 4, 5 and 6(a) to (g).

The waveform synthesiser 461 comprises a first input terminal 462 and a second input terminal 464. The first and second input terminal 462, 464 are connected to respective inputs 465, 467 of a reference multiplexer 463. A terminal 469 of the reference multiplexer 463 is connected to receive a frequency select signal. The output of the reference multiplexer 463 is connected to the clock input of a divider 471. The output of the divider 471 is connected to the clock input of a shift register 473. In an alternative embodiment, the shift register may be replaced by a series of delay buffers in parallel connected stages, each stage shifting each subsequent waveform by a clock cycle. A first output terminal 474 and a second inverse output terminal 476 of the shift register 473 are connected to respective input terminals of a first phase multiplexer 475 and a second phase multiplexer 483.

A terminal 476 of the first phase multiplexer 475, and terminal 482 of the second phase multiplexer 483 via terminal 481 of the first phase multiplexer 475 are connected to receive a phase select signal. Alternatively, the phase select signal may be fed directly to the terminal 482 of the second phase multiplexer 483. The output of the first phase multiplexer 475 is connected to the input of a first 3-bit DAC 493. The output of the second phase multiplexer 483 is connected to the input of a second 3-bit DAC 495.

The output of the first DAC 493 is connected to the first output terminal 497 of the waveform synthesiser 461 and the output of the second DAC 495 is connected to the second output terminal 499 of the waveform synthesiser 461.

In operation one of the frequencies fref input on the first and second input terminals 462, 464 (for example 2.112 GHz or 6.336 GHZ) is selected by the reference multiplexer 463 according to the frequency select signal on terminal 469 of the reference multiplexer 463. The output of the reference multiplexer is divided by the divider 471 by 2 h1max Therefore for umax 4' fref is divided by 8. The resulting waveform is shown in Figure 6(b). This waveform is then shifted n (4) times by the shift register 473 to generate four waveforms. The first waveform shifted by 0 clock cycle as shown in Figure 6(b). The second waveform shifted by 1 clock cycle as shown in figure 6(c). The third waveform is shifted by 2 clock cycles as shown in figure 6(d).

The fourth waveform is shifted by 3 clock cycles (flmax -1)as shown in figure 6(e).

These 4 waveforms are output on a first output terminal 474 of the shift register 473.

An inverse of the first to fourth waveforms are output via a second output terminal 476 of the shift register 473. An inverse of the first waveform, the third and fourth waveforms are input on a first input terminal 477 of the first phase multiplexer 475 and a second input terminal 487 of the second phase multiplexer 483. The first, second and third waveforms are input on a second input terminal 479 of the first phase multiplexer 475 and the first input terminal 485 of the second phase multiplexer 483. The selected waveforms input on respective input terminals of the first phase multiplexer 475 and the second phase multiplexer 483 are selected by virtue of the phase select signal. The output of the first phase multiplexer 475 is input into a first DAC 493 and the output of the second phase multiplexer 483 is input into a second DAC 495. The selected waveforms are combined to generate the waveform shown in figures 6(f) and (g) A first combination is a combination of an inverse of the fourth waveform, the first and second waveforms as shown in figure 6(f), i.e. an I and Q waveform. A second combination is the combination of the second, third and fourth waveforms as shown in figure 6(g), i.e. an I and -Q waveform. The first DAC 493 generates a first in-phase output and the second DAC 495 generates a second quadrature output in which the middle DAC bit is multiplied by -ñ to produce the appropriate output waveform with the 3rd and order harmonics cancelled to produce first and second synthesised waveforms in which the first is the quadrature of the second synthesised waveform on the respective output terminals 497, 499 of the waveform synthesiser 461.

The synthesised waveforms are then mixed with the output of the phase-locked loop circuit 401 by the SSB mixers 417_i to 417_4. The specific output of the required frequency for the appropriate UWB band is selected by first and second band multiplexers 423, 433 in accordance with the band selection signal on terminals 427 and 437 of the first and second band multiplexers 423, 433. The output of the first and second band multiplexers 423, 433 is an in-phase LO signal output on the first output terminal 441 and a LO signal with a 90° phase shift (a quadrature LO signal) on the second output terminal 443.

Although embodiments of the present invention have been illustrated in the accompanying drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous modifications without departing from the scope of the invention as set out in the following claims.