GB2463866A - High-speed CMOS image sensors - Google Patents

High-speed CMOS image sensors Download PDF

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Publication number
GB2463866A
GB2463866A GB0817458A GB0817458A GB2463866A GB 2463866 A GB2463866 A GB 2463866A GB 0817458 A GB0817458 A GB 0817458A GB 0817458 A GB0817458 A GB 0817458A GB 2463866 A GB2463866 A GB 2463866A
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high speed
cmos image
image sensor
speed cmos
array
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GB0817458D0 (en
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Wai Hung Chan
Keith Roger Taylor
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SPECIALISED IMAGING Ltd
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

Through silicon vias are used to connect CMOS image sensors arranged on a silicon die surface with memory, processing or shift register circuits arranged either on the back surface of the silicon die or on a further integrated circuit die. Multichip modules having three dies are also described. The top surface of the image sensor only contains photodiode sensors which increases the photosensitive area of the sensor. This configuration allows high speed readout from active pixel sensors.

Description

Improvements in high-speed image sensors
DESCRIPTION
Background
High speed CMOS image sensors have been developed over recent years to enable images to be captured at rates of several thousands of images per second. The fundamental limitation in the speed of operation of these devices is the time that it takes to read out the image data from the sensor. Faster frame rates can be achieved by reading out smaller areas of the image sensor which limits the usefulness of these devices at very high frame rates. Two main approaches have been taken to allow the speed increases that have already been achieved. The first approach is to convert the pixel charge from analogue to digital locally, and read out the data through parallel busses using LVDS signalling -this has the big advantage of simplifying the external circuitry, but readout speed is now limited by the bandwidth of this interface, and a significant amount of useful light sensing area has to be sacrificed to accommodate the data conversion and storage functions. The second (and faster readout) approach is to use parallel analogue outputs -digitisation is carried out (in parallel) off-chip which adds significantly to the complexity of the camera system. Readout i-ate is limited by the capacitance of the analogue busses which can also cause ghosting effects due to crosstalk between these sensitive connection paths.
An alternative early approach to high speed image sensors (using CCD devices) was to employ a frame transfer technology, but to optically mask strips of pixels along the readout axis such that by shifting each pixel along the readout register. the integrated image was moved under the optical mask and therefore stored, after a second exposire period, the next image could also be shifted along the readout axis to be stored under the mask. In this way, up to 16 images have been stored on the chip before final readout at normal rates. This approach can give very high acquisition speeds for small numbers of frames, albeit at the expense of usable image pixels, and significant moire artefacts are sometimes introduced due to the pattern of exposed pixels. Extending this concept to the CMOS domain using local storage has resulted in sensors with local pixel data storage of up to frames at each photosite, but again this has come at the expense of light sensitive area, and therefore sensitivity. Additionally, the number of available pixels over the sensor area has had to be reduced to accommodate the local digitisation and storage elements.
Improvements Increasing the readout rate of frames in image sensors is fundamentally limited by the physics of the devices -i.e. large area arrays have large capacitance output structures which restrict the bandwidth for analogue readout techniques. High speed digital readout is limited by the number of parallel paths that can be accommodated in the physical device and therefore by the number of bits per frame that have to be transmitted over each path.
The invention described here allows the speed of image capture of a CMOS image sensor to be increased by arranging local pixel data storage on the image sensor local to the light sensitive pixels without sacrificing sensitivity by reducing the active pixel area as a result of adding these functions. Image sequence readout can be carried out post-capture at modest readout rates thereby simplifying the overall system design. Using shift-register storage elements means that pixel (and therefore image) rates are achievable at many millions per second, and with very high fill-factors to allow the sensitivity required for achieving image capture in sub-microsecond timescales.
The idea behind this invention is to move the processing and storage circuitry away from the photosites. but using conventional methods would involve very dense interconnects which iii themselves would erode the available photosensitive area. In view of recent and ongoing developments in Through-Silicon-Via technology (TSV) for stacked memory applications, a new approach where photosensitive pixels are created on one die with ISV's connecting each of these photosites to signal processing and memory elements located vertically below, either on another die or on the back surface of the die, would allow both enhanced processing/digitising capability and increased memory capacity local to the pixels. This architecture would lead to high speed image sensors with perhaps several hundred frames of niemory at speeds only liniited by the rate at which the samples could be digitised and transferred to the local storage. Resultant sensors would also be able to niaximise detection area per pixel (limited mainly by the cross-sectional area of the ISV's) and therefore greatly improve sensitivity over conventional designs.
By arranging the local pixel memory as shift-registers, it is then possible to run the sensor at maximum framing rate indefinitely, with the last few hundred frames (limited by storage area available) being stored locally in the shift registers. Given that the function of writing to the shift register memory can be stopped on demand by an external signal, then images of subject behaviour leading up to a trigger event could be recorded and further enhance the camera system for applications where triggers are not easily obtained from the event under observation. Furthermore, with correctly controlled timing of the signal used to stop writing to the storage elements, events both before and after a trigger may be recorded.
The proposed system may be extended even further by arranging the shift register outputs to couple to additional set of TSV's allowing connection to additional layer(s) of on-sensor storage. In this way the area restriction in storage capacity can be overcome allowing niore extensive image storage at the fastest speed of sensor operation without having to overconie the bandwidth problenis normally associated with high speed sensor readout.
Detail Description
Three variants of CMOS image sensor pixels are shown. In figure 1 a passive pixel sensor (PPS) consists of a diode photosite connected using a transistor to a word line and a bit line -the charge in each pixel is read out via a column charge amplifier located outside of the pixel array. Although PPS has small pixel size and large fill factor, it suffers from slow readout speed and low signal to noise ratio. Figure 2 shows an active pixel sensor (APS) which tries to solve these problems by having a buffer amplifier in each pixel, which is normally implemented with three or four transistors. In comparison to PPS, APS has larger pixel size and lower fill factor, but its readout is faster and has higher signal to noise ratio. Figure 3 shows a digital pixel sensor (DPS) where each pixel has an ADC and all ADCs operate in parallel. With an ADC per pixel, massively parallel AID conversion and high speed digital readout become practical, eliminating analogue AID conversion and readout bottlenecks. The main drawback of DPS is its large pixel size due to the increased number of transistors per pixel.
Figure 4 shows the new improved pixel architecture where the top layer die only needs to contain the photosite diodes and through-silicon-vias, thereby maxiniising photosensitive area. All of the remaining circuitry normally associated with a DPS is now located on the attached second die, together with extra nieniory elements arranged as a shift register to allow local storage of many sequential pixels for each photosite.
Figure 5 shows two possible schemes, both using through-silicon-vias. The first scheme shows a double-sided wafer with photosites on the upper surface connected through the silicon using TSVs to ADC and memory elements on the bottom surface of the substrate. The second scheme shows a similar arrangenient with photosites on the top of the upper substrate, but in this instance, the ADC and storage elements are on a second die which is electrically connected to the underside of the first die using solder balls or similar connection method. With this arrangement, it is possible to also include through-silicon vias in the lower die to allow connections through the second layer of silicon to a further storage layer below as shown in figure 6.
Figure 7 shows a block diagram of the basic pixel elements indicating the flow of data from photosite to A to D converter, then through the memory shift-register. The addition of an enable line which controls the data flow through the shift register allows data from the A to D converter to be either written into the memory shift register or ignored. When the enable line is active, data from the A to D converter will be stored in the memory array. Because the array is arranged as a shift register, as new data is clocked into the start of the register, old data reaching the readout end of the shift register will be lost. As soon as the enable line becomes inactive, A to D data will be ignored while the data already stored in memory will be retained. The clock signal to the shift registers is selected between pixel clock for writing and a separate readout clock for reading. Careful control of the enable and clock lines allows pixel by pixel readout through the normal CMOS readout structures enabling previously recorded image sequences to be transferred to a p.c for analysis.
Figure 8 represents a typical high-speed event being recorded by a camera utilising the high-speed image sensor described herein. The camera in this example is triggered by an acoustic triggering device which responds to the shockwave generated by the event before sending a trigger signal to the camera. Because the speed of sound is around 340 mIs, it will take over 300 microseconds for the shockwave to reach the detector if it is 10 centimetres from the event. If the camera is to record at one million frames per second, then the trigger will arrive at the camera approximately 300 frame periods after the event. Clearly for the camera to record the event we cannot use this trigger to start recording since the event is long over by the time the trigger reaches the camera. However, since the previous frames captured by the already running sensor have been stored in the shift register memory elements, the event is already held in this memory so by stopping the recording process after the trigger, the images from before and after the trigger can be subsequently read out of the sensor.

Claims (2)

  1. Improvements in high-speed image sensorsCLAIMS1 A high speed CMOS image sensor incorporating through-silicon-via-technology or similar interconnection means to electronically couple separate substrates or layers containing on one substrate or layer image sensing circuitry and on a separate substrate or layer image digitisation processing and or storage circuitry.
  2. 2 A high speed CMOS image sensor according to claim 1, configured to spatially separate image sensing and image processing functions, thereby to increase light sensitivity by allowing larger image sensing area per pixel 3 A high speed CMOS image sensor according to claim 1, configured to spatially separate image sensing and image processing functions as a means to allow more die space for local data storage elements associated with each pixel thereby increasing the number of frames that can be recorded.4 A high speed CMOS image sensor according to any preceding claim, incorporating shift register or first-in-first-out (FIFO) storage elements for local storage of image data to allow serial writing and reading of that data.A high speed CMOS image sensor according to any preceding claim, further comprising means for responding to a triggered enable signal associated with the writing function of local shift register storage elements to allow storage of both pre and post trigger pixel data under control of that enable signal.6 A high speed CMOS image sensor according to claim 5 arranged to further extend the local shift register storage capacity for pixel data, thereby allowing an increased number of frames to be recorded.7 A high speed CMOS image sensor comprising a first substrate or layer formed with an array of light-sensitive devices and a second substrate or layer formed with an array of circuits capable of processing or otherwise operating on electrical signals output from said light-sensitive devices; and an array of silicon vias coupling respective ones of said devices to respective ones of said circuits.8 A method of making a high speed CMOS image sensor comprising the steps of: forming an array of light-sensitive devices upon or within a first substrate or layer of semiconductive material; forming an array of circuits capable of processing or otherwise operating on electrical signals output from said light-sensitive devices upon or within a second substrate or layer of semiconductive material and forming an array of silicon vias through said semiconductive material to couple respective ones of said devices to respective ones of said circuits
GB0817458A 2008-09-24 2008-09-24 High-speed CMOS image sensors Withdrawn GB2463866A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102280456A (en) * 2011-05-11 2011-12-14 北京大学 Infrared focal plane array seeker integrated structure and manufacturing method
WO2014166707A1 (en) * 2013-04-11 2014-10-16 Siemens Aktiengesellschaft Production method of a sensor chip and computerized tomography detector
US20180192861A1 (en) * 2011-05-12 2018-07-12 DePuy Synthes Products, Inc. Image sensor with tolerance optimizing interconnects
US10750933B2 (en) 2013-03-15 2020-08-25 DePuy Synthes Products, Inc. Minimize image sensor I/O and conductor counts in endoscope applications
US11089192B2 (en) 2012-07-26 2021-08-10 DePuy Synthes Products, Inc. Camera system with minimal area monolithic CMOS image sensor
US11344189B2 (en) 2013-03-15 2022-05-31 DePuy Synthes Products, Inc. Image sensor synchronization without input clock and data transmission clock

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JPS59128878A (en) * 1983-01-13 1984-07-25 Fujitsu Ltd Solid-state image pickup device
US4956687A (en) * 1986-06-26 1990-09-11 Santa Barbara Research Center Backside contact blocked impurity band detector
US20060043569A1 (en) * 2004-08-27 2006-03-02 Benson Peter A Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
WO2007043718A1 (en) * 2005-10-11 2007-04-19 Tae-Seok Park Wafer level package using silicon via contacts for cmos image sensor and method of fabricating the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102280456A (en) * 2011-05-11 2011-12-14 北京大学 Infrared focal plane array seeker integrated structure and manufacturing method
US11432715B2 (en) 2011-05-12 2022-09-06 DePuy Synthes Products, Inc. System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects
US11848337B2 (en) 2011-05-12 2023-12-19 DePuy Synthes Products, Inc. Image sensor
US20180192861A1 (en) * 2011-05-12 2018-07-12 DePuy Synthes Products, Inc. Image sensor with tolerance optimizing interconnects
US10537234B2 (en) * 2011-05-12 2020-01-21 DePuy Synthes Products, Inc. Image sensor with tolerance optimizing interconnects
US10863894B2 (en) 2011-05-12 2020-12-15 DePuy Synthes Products, Inc. System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects
US11026565B2 (en) 2011-05-12 2021-06-08 DePuy Synthes Products, Inc. Image sensor for endoscopic use
US11109750B2 (en) 2011-05-12 2021-09-07 DePuy Synthes Products, Inc. Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
US11179029B2 (en) 2011-05-12 2021-11-23 DePuy Synthes Products, Inc. Image sensor with tolerance optimizing interconnects
US11682682B2 (en) 2011-05-12 2023-06-20 DePuy Synthes Products, Inc. Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
US11766175B2 (en) 2012-07-26 2023-09-26 DePuy Synthes Products, Inc. Camera system with minimal area monolithic CMOS image sensor
US11089192B2 (en) 2012-07-26 2021-08-10 DePuy Synthes Products, Inc. Camera system with minimal area monolithic CMOS image sensor
US10750933B2 (en) 2013-03-15 2020-08-25 DePuy Synthes Products, Inc. Minimize image sensor I/O and conductor counts in endoscope applications
US11344189B2 (en) 2013-03-15 2022-05-31 DePuy Synthes Products, Inc. Image sensor synchronization without input clock and data transmission clock
US11253139B2 (en) 2013-03-15 2022-02-22 DePuy Synthes Products, Inc. Minimize image sensor I/O and conductor counts in endoscope applications
US10881272B2 (en) 2013-03-15 2021-01-05 DePuy Synthes Products, Inc. Minimize image sensor I/O and conductor counts in endoscope applications
US11903564B2 (en) 2013-03-15 2024-02-20 DePuy Synthes Products, Inc. Image sensor synchronization without input clock and data transmission clock
WO2014166707A1 (en) * 2013-04-11 2014-10-16 Siemens Aktiengesellschaft Production method of a sensor chip and computerized tomography detector

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