GB2456640A

GB2456640A - SRAM devices

Info

Publication number: GB2456640A
Application number: GB0724420A
Authority: GB
Inventors: Stephen Felix
Original assignee: Icera LLC
Current assignee: Icera LLC
Priority date: 2007-12-14
Filing date: 2007-12-14
Publication date: 2009-07-29
Anticipated expiration: 2027-12-14
Also published as: GB2456640B; GB0724420D0

Abstract

The 6T SRAM device comprises switching circuitry arranged to disconnect the power supply line lvdd of a column of SRAM memory cells during a write operation to that column allowing the supply connection of the column to float. The power supply is reconnected to the memory cell column during a read operation. The arrangement is used in low power, low voltage sub 65nm devices without using separate power supply circuitry for the memory and logic circuits.

Description

Memory Device

Field of the Invention

The present invention relates to the precharging of a column of memory cells in a memory device.

Background

CMOS memory circuits typically use the ubiquitous six transistor (6T) cell as storage for each binary bit'. Such "6T-SRAM" circuits can be found in practically every microprocessor, DSP (Digital Signal Processor) or ASIC (Application Specific Integrated Circuit) chip manufactured using CMOS technology.

The amount of power consumed by a digital CMOS integrated circuit (IC) is approximately proportional to the square of the power supply voltage. Thus, lowering the power supply voltage is a highly effective way of reducing an IC's power consumption.

However at lower supply voltages, logic circuits slow down and memory cells can fail to be written or fail to retain their contents when read (read upset). Any one of these failure mechanisms can prevent a lower supply voltage from being deployed.

6T SRAM cells built in modern, small geometry CMOS processes of 65nm and below are particularly affected strongly by random process variations because they are made from very small transistors in order to maximise storage density (the measurement of 65nm and below refers to the gate width of the transistors used). The magnitude of such random variations is typically proportional to the reciprocal of the square root of the channel area of the transistor.

Typically, a single chip will contain millions of 6T SRAM cells. The aforementioned random process variations mean that inevitably, some cells are particularly susceptible to the write failure or read upset failure at low supply voltages. It is a common practise to build in spare (redundant) SRAM cells that can be used to replace defective cells or such weak' cells. This can certainly help. But more can still be done.

The minimum supply voltage required for reliable operation of the SRAM can be significantly higher than the supply voltage necessary to run the logic at a particular speed.

Some chip designers have solved this dilemma pragmatically by separating the power supply for the SRAM from the associated address decoding and read-write logic. This is described in the following references: M.Khellah et al. "A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS", ISSCC Dig Tech. Papers, pp624-625, Feb 2006; and J.PiIle et al. "Implementation of the CELL Broadband EngineTM in a 65nm SQl Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V", ISSCC Dig. Tech. Papers, pp.322-323, Feb 2007.

However, this technique is more costly and complicated to implement than a single, unified power supply. It also suffers from the disadvantage that charge stored locally across one supply cannot be used to help maintain the voltage across the other supply.

It would be advantageous to lower the safe operating voltage of the SRAM, allowing power savings, without resorting to dual (separate) power supplies for the SRAM and associated logic respectively.

Low voltage cell writeability can be improved by temporarily driving the supply voltage to the cell being written. This technique is described in the following references: K. Zhang et al., "A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply", IEEE J. Solid-State Circuits, Vol.41, pp. 146-1 51, 2006.

M.Yabuuchi et aL, "A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations", ISSCC Dig.

Tech. Papers, pp.326-327, Feb 2007.

Nonetheless, there is still further scope to improve the low voltage writeability of memory cells.

Summary

According to one aspect of the present invention, there is provided a memory device comprising: a plurality of columns of memory cells, each column having a respective supply voltage connection to the cells of that column, each column having one or more respective bit-lines, and each column being connected to a plurality of word lines; and switching circuitry arranged to disconnect the supply connection of a column from a supply voltage during a write operation to that column, allowing the supply connection of said column to float.

Thus the cell supply voltage is not "driven" to a different voltage during a write operation, as in the Zhang and Yabuuchi references above, Instead, the cell supply voltage is allowed to drift by falling naturally of its own accord (or rising if the supply voltage is negative). Thus there is no need to drive the cell supply voltage to a particular level during writes, thus reducing the complexity of the circuitry, the area taken up on silicon, and the cost.

In embodiments, the memory device may comprise precharge circuitry for precharging the one or more bit-lines of said column prior to a write operation; and the switching circuitry may be arranged to connect the supply connection of said column to the supply voltage during the precharge, and to disconnect the supply connection of said column from the first supply voltage allowing the supply connection of that column to float during the write operation following said precharge.

The switching means may be arranged to connect the supply connection of said column to the supply voltage during at least one of a read operation and a standby.

The memory device may comprise control means configured to prevent the floating voltage of the supply connection drifting beyond a predetermined limit when disconnected during the write operation.

The memory device may comprise at least one of: read logic, write logic, and addressing logic operating at substantially said supply voltage.

Each column may be of thirty-two memory cells or less.

The memory device may be an SRAM device. The memory cells may be 6T SRAM cells.

The gate width of transistors constituting said memory cells may be 65nm or less.

According to another aspect of the present invention, there is provided method of writing to a memory device comprising a plurality of columns of memory cells, each column having one or more respective bit-lines and being connected to a plurality of word lines, the method comprising: providing a supply voltage to a supply connection of each column; and disconnecting the supply connection of a column from the supply voltage during a write operation to that column, allowing the supply connection of the column to float.

For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made by way of example to the accompanying drawings

Brief Description of the Drawings

Figure 1 is a schematic block diagram of a memory array, and Figure 2 is a circuit diagram of a column of memory cells.

Detailed Description

An SRAM memory device is described with reference to Figure 1. The device comprises an N by M array 2 of memory cells 4, with M columns and N rows where M and N are each any integer. A plurality (M) of bit lines BL0. . . BLM1 and a plurality (N) of word lines WLO...WLN.i are formed in the device. Within each column m, each cell 4 is connected to a bit line BLm of the respective column.

Within each row n, each cell 4 is connected to a word line WL of the respective column. The bit lines BL and world lines WL are connected to address decoding, reading and writing logic (not shown) as known in the art. For each bit line BL, there may also be formed a respective corresponding inverse bit line BL (not shown), which is not strictly necessary but improves tolerance to noise.

In operation, access to a cell 4 is enabled by asserting its corresponding word line WL (only one word line WL is asserted at any one time). The address decoding logic takes an address and decodes it into a signal onto the relevant word line WL. In a read cycle, the read logic reads the stored binary value of each cell 4 of the addressed word line WL from each of the respective bit lines BL0.. .BLM1. In a write cycle, the write logic stores a binary value in each cell 4 of the addressed word line WL by driving that value onto each of the respective bit lines BLO...BLM.I. In standby state, no word line WL is asserted and each cell 4 simply stores its respective value.

A column m of memory cells is described in relation to Figure 2. The column comprises a bit line BLm, an inverse bit line BLm, a column power supply line lvdd, N memory cells 4 to 4N-1, and write logic comprising write circuitry 6. The write logic will also comprise additional write logic (not shown) to determine which write line (write_0 or write_I) of which column 1...M should be asserted depending on the data and address arriving at the memory device, and to assert the relevant write line and corresponding precharge line (precharge_m) with the correct relative timing to achieve the desired write, as will be discussed in more detail below. A power supply rail Vdd provides a supply voltage for the write circuitry 6 and cells 4 to 4 of each column I to M-1 in the array 2.

The write circuitry 6 comprises a first transistor of a first type P1, a second transistor of the first type P2, a first transistor of an opposite second type NI, a second transistor of the second type N2, a third transistor of the first type P3, a fourth transistor of the first type P4, a fifth transistor of the first type P5, a sixth transistor of the first type P6, and a seventh transistor of the first type P7. The memory cell 4 comprises an eighth transistor of the first type P8, a ninth transistor of the first type P9, a third transistor of the second type N3, a fourth transistor of the second type N4, a fifth transistor of the second type N5, and a sixth transistor of the second type N5. Each transistor has a control terminal, a first conducting terminal, and a second conducting terminal. The first type is preferably PMOS (p-type Metal Oxide Semiconductor Field Effect Transistor) and the second type is preferably NMOS (n-type Metal Oxide Semiconductor Field Effect Transistor), in which case the control terminal is the gate, the first conducting terminal is the source, and the second conducting terminal is the drain.

In the memory cell 4, the eighth PMOS transistor P8 and a ninth PMOS transistor Pg connected as a first cross coupled pair, a third NMOS transistor N3 and a fourth NMOS transistor N4 connected a second cross-coupled pair, and a fifth NMOS transistor N5 and a sixth NMOS transistor N6 connected as access transistors. This is a conventional "6T" memory cell arrangement which in itself is well-known in the art, but which is described here for completeness.

The sources of the eighth and ninth PMOS transistors P8 and P9 are each connected to the supply line lvdd. The sources of the third and fourth NMOS transistors N3 and N4 are each connected to ground. The drain of the eighth PMOS transistor P8 is connected to the drain of the fourth NMOS transistor N3 forming a first node (I) therebetween, and the drain of the ninth PMOS transistor P9 is connected to the drain of the fourth NMOS transistor N4 forming a second node (ii) therebetween. The gate of the ninth PMOS transistor P9 and the gate of the fourth NMOS transistor N4 are each connected to the first node (I) (between the drains of the eighth PMOS transistor PB and third NMOS transistor N3). The gate of the eighth PMOS transistor P8 and the gate of the third NMOS transistor N3 are each connected to the the second node (ii) (between the drains of the ninth PMOS transistor and fourth NMOS transistor N4). The source of the fifth NMOS transistor N5 is connected to said first node (i), and the source of the fifth PMOS transistor is connected to said second node (ii). The drain of the fifth PMOS transistor N5 is connected to the bit line BL, and the drain of the sixth PMOS transistor N6 is connected to the inverse bit line BL. The gates of the fifth and sixth NMOS transistors N5 and N6 are each connected to the respective In operation, due to the cross-coupling of the gates of the eighth PMOS transistor P8 and third NMOS transistor N3 to the second node (ii) between the drains of the ninth PMOS transistor P9 and fourth NMOS transistor N4, and vice versa, then the cell 4 only has two stable states. In the first stable state, the eighth PMOS transistor P8 and fourth NMOS transistor N4 are on whilst the ninth PMOS transistor N9 and third NMOS transistors N3 are off. This means the first node (i) between the drains of the eighth PMOS transistor P8 and third NMOS transistor N3 is connected to the supply line Ivdd and so is at a logic-high, whilst the second node (ii) between the drains of the ninth PMOS transistor P9 and fourth NMOS N4 is connected to ground and so is at a logic low. In the second stable state, the ninth PMOS transistor P9 and third NMOS transistor N3 are on whilst the eighth PMOS transistor P8 and fourth NMOS transistor N4 are off. This means the second node (ii) between drains of the ninth PMOS transistor P9 and fourth NMOS transistor N4 is connected to the supply line Ivdd and so is at a logic high, whilst the first node (i) between the drains of the eighth PMOS transistor P8 and third NMOS transistor N3 is connected to ground and so is at a logic-zero. The stable state which the cell 4 is in represents the bit stored therein, with the first stable state being taken to represent a logic-one and the second stable state being taken to represent a logic-zero.

Note that for brevity, the components of only one cell 4 are illustrated in detail in Figure 2, but it will be understood that the other cells 4, to 4N-1 have the same composition and operate in the same way. Each other cell 4, to 4NI is also connected to the bit line BL, inverse bit line BL, power supply line lvdd and respective word line in the same manner as the first cell 4.

In a read cycle, the address decoding logic (not shown) asserts a signal on the desired word line, thus causing the access transistors N5 and N6 of each cell 4 on that word line to conduct. This means the first node (i) is conductably connected to the bit line BL and the second node (ii) is conductably connected to the inverse bit line BL. So in the first stable state, a logic-high appears on the bit line BL and a logic-low appears on the inverse bit line BL, thus representing a logic-one. And in the second stable state, a logic-low appears on the bit line BL and a logic-high appears on the inverse bit line BL, thus representing a logic-zero. The value appearing on each bit line BL0. . . BLM.1 is then read by the read logic (not shown).

The write circuitry 6 for each column m comprises: precharge circuitry in the form of the first PMOS transistor P1, second PMOS transistor P2 and a precharge line (precharge_m); write devices in the form of the first NMOS transistor NI and second NMOS transistor N2; a zero write line (write_0) and a one write line (write_i); additional driving devices in the form of the third PMOS transistor P3 and fourth PMOS transistor P4; and voltage control circuitry in the form of the fifth PMOS transistor P5, sixth PMOS transistor P6 and seventh PMOS transistor P7.

The first PMOS transistor P1 is connected between the bit line BL and the supply rail Vdd, with its source connected to the supply rail Vdd and its drain connected to the bitline BL. The second PMOS transistor P2 is connected between the inverse bit line BL and the supply rail Vdd, with its source connected to the supply rail Vdd and its drain connected to the inverse bit line BL. The gates of the first and second PMOS transistors P1 and P2 are each connected to the precharge line (precharge_m) for the respective column. The first NMOS transistor Ni has its drain connected to the bit line BL, its source connected to ground, and its gate connected to the zero write line (write_U). The second NMOS transistor N2 has its drain connected to the inverse bit line BL, its source connected to ground, and its gate connected to the one write line (write_I). The third PMOS transistor P3 has its source connected to the supply rail Vdd, its drain connected to the bit line BL, and its gate connected to the inverse bit line BL. The fourth PMOS transistor P4 has its source connected to the supply rail Vdd, its drain connected to the inverse-bit line BL, and its gate connected to the bit line BL.

The fifth and sixth PMOS transistors P5 and P6 form a switch connected between the overall supply rail Vdd for the array and the supply line lvdd for a respective column of cells 4o to 4N1. The fifth PMOS transistor P5 has its source connected to the supply rail Vdd and its gate connected to the one write line (write_i). The sixth PMOS transistor has its source connect to the drain of the fifth PMOS transistor P5, its gate connected to the zero write line (write_0), and its drain connected to the column supply line lvdd. The seventh PMOS transistor P7 has its source connected to the supply rail Vdd, and its gate and drain connected to the column supply line lvdd.

Note that apart from devices P5, P6, P7 and the fact that supply line lvdd is not connected directly to the supply rail Vdd, all of the circuitry shown in Figure 2 is in itself normal for a column of SRAM cells but is included herein to provide context.

When the column is on standby, no signal is asserted on the precharge line (prechargem), so the first and second PMOS transistors P1 and P2 do not conduct and the bit line BL and inverse bit line BL are left floating. During a read cycle, again no signal is asserted on the precharge line (precharge_m) and the bit line BL and inverse bit line BL take a voltage level as determined by the state of the cell of the selected word line as described above.

In a write cycle, the address decoding logic (not shown) asserts a signal on the desired word line, thus causing the access transistors N5 and N6 of each cell 4 on that word line to conduct. As in the read cycle, this means the first node (i) is conductably connected to the bit line BL and the second node (ii) is conductably connected to the inverse bit line BL. However, for a write, this time values are to be forcibly driven onto the bit line BL and inverse bit line BL instead of being read from those lines.

To achieve this, the additional write logic (not shown) first asserts a signal on the precharge line (precharge_m). This causes the first and second PMOS transistors P1 and P2 to conduct, thus "precharging" the bit lines of the respective column by forcing both the bit line BL and inverse bit line BL high.

Because the access transistors N5 and N6 of the cell of the selected word line are also on and thus conducting, this means the first and second nodes (I) and (ii) are both also forced high. This is not a stable state for the cell.

After the precharge, the additional write logic (not shown) de-asserts the precharge line (precharge_m) and then asserts a signal on either the zero write line (write_O) or the one write line (write_i), but not both, depending on the data to be written, If the zero write line (write_0) is asserted and not the one write line (write_1)then the first NMOS transistor Ni conducts to ground whilst the second NMOS transistor N2 does not, and so the bit line BL is forced to a logic-low whilst the inverse bit line BL is unaffected. Thus the first node (i) of the cell of the selected word line is forced to logic-low whilst the second node (ii) remains at a logic-high, and the cell falls into the first stable state representing a logic-zero. If on the other hand the one write line (write_I) is asserted and not the zero write line (write_0) then the second NMOS transistor N2 conducts to ground whilst the first NMOS transistor Ni does not, and so the inverse bit line BL is forced to a logic-low whilst the bit line BL is unaffected. Thus the second node (ii) of the cell of the selected word line is forced to logic-low whilst the first node (i) remains at a logic-high, and the cell falls into the second stable state representing a logic-one.

Turning now to the voltage control circuitry, the switch formed by the fifth and sixth PMOS transistors P5 and P6 acts to connect the column supply line lvdd to the Vdd supply rail whenever no cell in the column is being written. So during a precharge or read, the column supply line is forced to the supply voltage Vdd, but during a write the column supply voltage is allowed to float.

When no signal is asserted on either the zero write line (write_O) or the one write lines (write_I) such that both are low (i.e. during read, standby or precharge), then the column supply line tvdd is kept high through devices P5 and P6 which are both on (conducting). The fifth and sixth PMOS transistors P5 and P6 must be strong enough to restore lvdd all the way to Vdd (within -lOmV), even at the SPFN or FPFN high temperature process corners otherwise read stability could be compromised.

However, when a signal is asserted on either the zero write line (write_0) or one write line (write_i) such that either goes high, then the fifth and sixth PMOS transistors P5 and P6 turn off (don't conduct) so the column supply line lvdd is allowed to float, causing its voltage to "droop" in order to assist writing a cell with poor write margin.

The seventh PMOS transistor P7 is provided to prevent the column supply line lvdd from drooping too far. The seventh PMOS transistor P7 allows the voltage of the column supply line lvdd to droop by some amount during a write operation, but ensures that the cell column supply voltage is not depressed too low (allowing the unwritten cells in the column to maintain their contents).

Note that the number of cells per bit line should be kept small, preferably thirty-two or less. This is in order to minimize capacitance on the column's supply line lvdd, allowing its voltage to droop in a timely manner and thus allow marginal cells to be written at speed. Coincidently, keeping the columns small (e.g. eight, sixteen or thirty-two cells) also reduces the bit line capacitance which mitigates the read-upset problem.

It will be appreciated that the above embodiments are described only by way of example. For example, in another embodiment, a single transistor can be used instead of fifth and sixth PMOSs P5 and P6. The only requirement being that the switch is turned off only while a cell in the column is being written.

Further, there is scope to alter the mechanism by which the column supply line is allowed to droop. For example, by grounding the gate of the seventh PMOS P7, putting two such devices in series, and/or adding such devices in parallel are all options to ensure neither too little droop to write marginal cells at FPSN (cold) or too much droop at SPFN (hot) where other unwritten cells on the bit line are most likely to be susceptible to data retention problems. Or device P7 could be eliminated entirely as long as the time that the switch can remain off is limited enough to avoid node lvdd drooping too low (corrupting the contents of the other cells in the column).

Further, although thirty-two is the preferred maximum number cells per column, large numbers are not precluded if a lower speed can be tolerated or if more quickly responding components are used. Further, a negative supply voltage Vdd could be used, in which case the column supply line would drift by rising when allowed to float. Further, although the above has been describe in relation to a particular 6T SRAM memory cell, the principle of the invention may be applied to other types of cell such as 8T cell or to types of memory other than SRAM.

Further, PMOS and NMOS transistors could be swapped around, different kinds of transistor other than MOSFETS could be used.

Other variations and applications of the present invention may be apparent to a person skilled in the art given the disclosure herein. The scope of the invention is not limited by the described embodiments, but only by the following claims.

Claims

Claims 1. A memory device comprising: a plurality of columns of memory cells, each column having a respective supply voltage connection to the cells of that column, each column having one or more respective bit-lines, and each column being connected to a plurality of word lines; and switching circuitry arranged to disconnect the supply connection of a column from a supply voltage during a write operation to that column, allowing the supply connection of said column to float.
2. The memory device of claim 1, comprising: precharge circuitry for precharging the one or more bit-lines of said column prior to a write operation; wherein the switching circuitry is arranged to connect the supply connection of said column to the supply voltage during the precharge, and to disconnect the supply connection of said column from the first supply voltage allowing the supply connection of that column to float during the write operation following said precharge.
3. The memory device of claim I or 2, wherein the switching means is arranged to connect the supply connection of said column to the supply voltage during at least one of a read operation and a standby.
4. The memory device of any preceding claim, comprising control means configured to prevent the floating voltage of the supply connection drifting beyond a predetermined limit when disconnected during the write operation.
5. The memory device of any preceding claim, comprising at least one of: read logic, write logic, and addressing logic operating at substantially said supply voltage.
6. The memory device of any preceding claim, wherein each column is of thirty-two memory cells or less.
7. The memory device of any preceding claim, wherein the memory device is an SRAM device.
8. The memory device of claim 7, wherein the memory cells are 6T SRAM cells.
9. The memory device of any preceding claim, wherein the gate width of transistors constituting said memory cells is 65nm or less.
10. A method of writing to a memory device comprising a plurality of columns of memory cells, each column having one or more respective bit-lines and being connected to a plurality of word lines, the method comprising: providing a supply voltage to a supply connection of each column; and disconnecting the supply connection of a column from the supply voltage during a write operation to that column, allowing the supply connection of the column to float.
11. The method of claim 10, comprising: precharging the one or more bit-lines of said column prior to a write operation; connecting the supply connection of said column to the supply voltage during the precharge, and to disconnect the supply connection of said column from the first supply voltage allowing the supply connection of that column to float during the write operation following said precharge.
12. The method of claim 10 or II, comprising connecting the supply connection of said column to the supply voltage during at least one of a read operation and a standby.
13. The method of any of claims 10 to 12, comprising preventing the floating voltage of the supply connection drifting beyond a predetermined limit when disconnected during the write operation.
14. the method of any of claims 10 to 13, comprising operating at least one of: read logic, write logic, and addressing logic at substantially said supply voltage.
15. The method of any of claims 10 to 14, wherein each column is of thirty-two memory cells or less.
16. The method of any of claims 9 to 15, wherein the gate width of transistors constituting said memory cells is 65nm or less. **** * S. *. S S... * . * 5* * S 5 *5*S S... * **

S *..

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16. The method of any of claims 10 to 15, wherein the memory device is an SRAM device.

17. The method of any of claims 10 to 16, wherein the memory cells are 6T SRAM cells.

18. The method of any of claims 10 to 17, wherein the gate width of transistors constituting said memory cells is 65nm or less.

Amendments to the claims have been filed as follows 1. A memory device comprising: a plurality of columns of memory cells, each column having a respective supply voltage connection to the cells of that column, each column having one or more respective bit-lines, and each column being connected to a plurality of word lines; switching circuitry arranged to disconnect the supply connection of a column from a supply voltage during a write operation to that column, allowing the supply connection of said column to float; and control means configured to prevent the floating voltage of the supply connection drifting beyond a predetermined limit when disconnected during the write operation.

:. 2. The memory device of claim 1, comprising: precharge circuitry for precharging the one or more bit-lines of said column prior to a write operation; :.:::. wherein the switching circuitry is arranged to connect the supply connection of said column to the supply voltage during the precharge, and to disconnect the supply connection of said column from the first supply voltage allowing the supply connection of that column to float during the write operation following said precharge. * I

3. The memory device of claim I or 2, wherein the switching means is arranged to connect the supply connection of said column to the supply voltage during at least one of a read operation and a standby.

4. The memory device of any preceding claim, comprising at least one of: read logic, write logic, and addressing logic operating at substantially said supply voltage.

5. The memory device of any preceding claim, wherein each column is of thirty-two memory cells or less.

6. The memory device of any preceding claim, wherein the memory device is an SRAM device. tc)

7. The memory device of claim6, wherein the memory cells are 6T SRAM cells.

8. The memory device of any preceding claim, wherein the gate width of transistors constituting said memory cells is 65nm or less.

9. A method of writing to a memory device comprising a plurality of columns of memory cells, each column having one or more respective bit-lines and being connected to a plurality of word lines, the method comprising: providing a supply voltage to a supply connection of each column; disconnecting the supply connection of a column from the supply voltage during a write operation to that column, allowing the supply connection of the column to float; preventing the floating voltage of the supply connection drifting beyond a :::: predetermined limit when disconnected during the write operation. *... * . S...

10. The method of claim 9, comprising: :,:::. precharging the one or more bit-lines of said column prior to a write operation; connecting the supply connection of said column to the supply voltage during the precharge, and to disconnect the supply connection of said column from the first supply voltage allowing the supply connection of that column to float during the write *SSSS* * operation following said precharge.

11. The method of claim 9 or 10, comprising connecting the supply connection of said column to the supply voltage during at least one of a read operation and a standby.

12. the method of any of claims 9 to 11, comprising operating at least one of: read logic, write logic, and addressing logic at substantially said supply voltage.

13. The method of any of claims 9 to 12, wherein each column is of thirty-two memory cells or less. a

14. The method of any of claims 9 to 13, wherein the memory device is an SRAM device.

15. The method of any of claims 9 to 14, wherein the memory cells are 6T SRAM cells.