GB2435694A

GB2435694A - Peak voltage detector circuit

Info

Publication number: GB2435694A
Application number: GB0604272A
Authority: GB
Inventors: Alison Burdett
Original assignee: Toumaz Technology Ltd
Current assignee: Toumaz Technology Ltd
Priority date: 2006-03-03
Filing date: 2006-03-03
Publication date: 2007-09-05
Also published as: GB0604272D0

Abstract

A peak voltage detector circuit comprising a comparator (A1) for comparing an input voltage (VA) against an output voltage (VB) stored by a capacitance (C1); the comparator (A1) switching a charging current (I1), such that the capacitance (C1) is charged so long as the input voltage (VA) exceeds the output voltage (VB). The output voltage (VB) therefore increases to, and remains at, the peak of the input voltage (VA). The accuracy of prior art voltage peak detector circuits is affected by the magnitude of the charging current (I1): too high a charging current (I1) will result in overshoot, with the stored output voltage (VB) exceeding the peak input voltage (VA); too low a charging current (I1) will result in the capacitance (C1) taking too long to reach the point where the output voltage (VB) equals the input voltage (VA). To overcome this problem and to increase accuracy, the present invention is a peak voltage detector circuit in which the charging current (I1) is proportional to the difference between the input voltage (VA) and the output voltage (VB). The circuit also includes means (S1) for discharging the capacitance (C1) and thereby resetting the circuit.

Description

PEAK DETECTOR CIRCUiT This invention relates to a circuit for detecting

a peak voltage in a variable voltage signal.

A typical known peak detector circuit is shown in Figure 1 of the accompanying drawings. A capacitor Cl stores an output voltage VB which is periodically reset to ground by a switch SI. A control circuit (not shown) controls the operation of the resetting switch SI, and the sampling of the output voltage VB. When the resetting switch Si is opened, the peak detector circuit operates to establish the peak of an input variable voltage VA. An amplifier Al operating as a comparator receives as inputs the input voltage VA and the voltage VB on the capacitor Cl, and provides an output to control a switch S2. The switch S2 is connected between a current supply II and selectively either the capacitor Cl or ground. When the input voltage VA rises above the voltage VB at the capacitor, the output of the comparator Al is high, closing switch S2 to position 1 and allowing the current source Ii to flow into the capacitor Cl. As the capacitor Cl charges up, the voltage VB rises. When the voltage VB equals or just exceeds VA, the comparator output switches to low, and switch S2 is opened to position 2, disconnecting the current Ii from the capacitor Cl. Capacitor Cl ceases being charged, and cannot discharge, so it holds the peak voltage seen at VA, which may then be read as the output voltage VB. If the input voltage VA subsequently rises above the previously held peak voltage at VB, switch S2 will once again close to position 1, and the capacitor Cl will charge towards the new peak voltage. Once the new peak voltage has been found and sampled, the capacitor Cl must again be reset by temporarily closing switch SI.

The accuracy of this conventional peak detector circuit is determined, to a large part, by the speed at which the comparator Al output can switch from high to low.

During this switching period dT while switch S2 is at position i, current II continues to flow into the capacitor Cl, resulting in a peak voltage that may be higher, sometimes significantly higher, than the true peak input voltage VA. This overshoot can be calculated approximately as dV = a II.dT, where a is a constant. This overshoot can be minimized by reducing the value of the charging current Il, but the problem then is that the circuit will take longer to reach the peak voltage, as shown in Figure 2, which is a graph of voltage V against time T, for a sinusoidal input voltage VA. As shown in Figure 2, there is an overshoot or error dV above the true peak voltage VB of the input voltage VA. This overshoot occurs over the interval dT immediately following the actual peak. The magnitude of dV depends upon the slope of the rise in VB, which is a function of the current 11.

Accordingly, the purpose of the present invention is to overcome this problem.

The invention provides a peak detector circuit comprising a capacitance for storing an output voltage as the peak of an input voltage, means for resetting the stored output voltage by discharging the capacitance, and means for charging the capacitance with a current proportional to the difference between the input and output voltages.

In order that the invention may be better understood, preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1, to which reference has already been made above, is a circuit diagram of a conventional peak detector; Figure 2 is a graph of voltage against time for input and output voltages in the circuit of Figure 1; Figure 3 is a circuit diagram of a peak detector circuit according to a first embodiment of the present invention; and Figure 4 is a circuit diagram of a peak detector circuit according to a second embodiment of the present invention.

With reference to Figure 3, the current source for charging the capacitor Cl with the input current II, consists of a transconductance cell GM!, with its output connected to the switch S2. The transconductance cell GM1 receives as inputs the variable input voltage VA, and the output voltage VB which is the voltage stored on the capacitor Cl.

Other than this, the circuit is the same as that shown in Figure 1.

The magnitude of the charging current II is no longer fixed, as in Figure 1, but instead it is made proportional to the residual voltage difference between the input signal and the capacitor Cl, i.e. the difference between VB and VA. The transconductance cell GM1 senses this voltage difference and generates an output current GM(VA -VB) = Ii. At the start of the peak detection phase, when the voltage difference VA -VB is large, the charging current II is large and the capacitor Cl is charged quickly towards the voltage VA. When the capacitor voltage VB almost reaches VA, the charging current II becomes very low; for this reason, switching delays of the comparator Al cause little overshoot dv.

It will be appreciated that the current II may not be exactly a linear function of the voltage difference VA -VB, and the term "proportional" in the context of the present invention is not intended to be a strict linear relationship.

An alternative circuit is shown in Figure 4, in which the charging current Ii provided by the transconductor OMI is the function GM(VA -VB) when VA is greater than VB, but II = 0 if VA is less than or equal to VB. The comparator Al and switch S2 are omitted in this embodiment. In this case, the charging current II automatically turns off when the output voltage VB on the capacitor Cl = VA.

Various alternatives to the circuit components illustrated in Figures 3 and 4 are envisaged, and in particular the invention is not limited to the use of specific amplifier types or switches, and the voltage could be stored on any form of capacitance, not necessarily a single capacitor.

The peak detector circuit can be controlled by an appropriate control circuit which may comprise a data processor such as a microprocessor, arranged to sample the output voltage VB periodically, and to reset the voltage using the switch SI periodically, or when it is determined that the input voltage VA has been reduced in amplitude, necessitating a reassessment of its peak voltage. Since such control circuitry is conventional, it is not illustrated in this specification.

Claims

CLAIMS: I. A peak detector circuit comprising a capacitance for storing

an output voltage as the peak of an input voltage, means for resetting the stored output voltage by discharging the capacitance, and means for charging the capacitance with a current proportional to the difference between the input and output voltages.

2. A peak detector circuit according to claim 1, in which the charging means comprises an amplifier connected to receive as inputs the input and output voltages and to provide as output a current proportional to the voltage difference.

3. A peak detector circuit according to claim 2, in which the amplifier is a transconductance cell.

4. A peak detector circuit according to any preceding claim, comprising a control amplifier and a switch, the switch connected between an output of the charging means and the capacitance and operable by an output of the control amplifier in response to the difference between the input and output voltages, whereby the current output of the charging means is switched to the charging means to charge the capacitance only when the input voltage exceeds the output voltage.

5. A peak detector circuit according to any preceding claim, in which the resetting means comprises a switch connected selectively to ground the output voltage.

6. A peak detector circuit according to any preceding claim, comprising a control circuit for sampling the output voltage periodically, and resetting the output voltage periodically.

7. A peak detector circuit, substantially as described herein with reference to Figures 3 and 4 of the accompanying drawings.