GB2428327A - Display and tape carrier package structure - Google Patents
Display and tape carrier package structure Download PDFInfo
- Publication number
- GB2428327A GB2428327A GB0608759A GB0608759A GB2428327A GB 2428327 A GB2428327 A GB 2428327A GB 0608759 A GB0608759 A GB 0608759A GB 0608759 A GB0608759 A GB 0608759A GB 2428327 A GB2428327 A GB 2428327A
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- display
- chip
- substrate
- disposed
- circuit board
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- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000002955 isolation Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000002861 polymer material Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims 6
- 239000004020 conductor Substances 0.000 claims 3
- 229920000620 organic polymer Polymers 0.000 claims 3
- 239000000565 sealant Substances 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 abstract description 39
- 239000002245 particle Substances 0.000 abstract description 16
- 239000010408 film Substances 0.000 description 16
- 230000002159 abnormal effect Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000003566 sealing material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Wire Bonding (AREA)
Abstract
A display (200) (see fig 4) including a display panel (210), a circuit board (220) and a tape carrier package structure (230) is provided. The circuit board (220) is disposed at the display panel (210). The tape carrier package structure (230) includes a substrate (232) having an opening (232a), a plurality of leads (234), a chip (236), and a blocking bar (238). The substrate (232) is between the display panel (210) and the circuit board (220). A plurality of leads (234), each having an inner lead (234a) and outer lead (234b), are disposed around the opening (232a) on the substrate (232). Some of the outer leads (234b) are electrically connected to the display panel (210), and other outer leads (234b) are electrically connected to the circuit board (220). The chip (236) has a plurality of contact points (236a), and is disposed at the opening (232a) of the substrate (232). The contact points (236a) are electrically connected to the inner leads (234a). Moreover, the blocking bar (238) is disposed on the substrate (232) between the chip (236) and the display panel (210). The blocking bar (238) stops particles (260) from getting into the gap formed near the bonding region of the display panel (210) and the top (230). Thereby preventing short circuit.
Description
DISPLAY AND TAPE CARRIER PACKAGE STRUCTURE
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a display. More particularly, the present invention relates to a display with a tape canier package (TCP) structure or with a package structure of chip on flexible printed circuit board (chip on FPC, COF).
2. Description of Related Art
As the video technology advances drastically, a variety of display devices has been developed. In general, a conventional display includes a display panel for displaying image. The display panel is controlled by a circuit board. The chip on the circuit board computes and provides digital signals in order to control the pixels of the display panel for displaying image and to generate a frame of image. In general, a package structure has to be electrically connected between the circuit board and the display panel.
A conventional tape carrier package (TCP) structure or a chip on flexible printed circuit board (chip-on-FPC, COF) package structure is a design for packaging the semiconductor chip to a small size unit. The technology is broadly used to package the liquid crystal display driving integrated chip (LDI).
FIG. 1 is a schematic top view of a display using a conventional tape carrier package structure. Referring to FIG. 1, a display 100 includes a display panel 110, at least a circuit board 120 and at least a tape carrier package structure 130. The circuit board 120 is disposed at a side of the display panel 110, and the tape carrier package structure 130 is electrically connected between the display panel 110 and the circuit board 120.
FIG. 2 is a schematic cross-sectional view of the tape carrier package structure along line A-A' of FIG. 1. Referring to FIG. 1 and FIG. 2, the tape carrier package structure 130 includes a substrate 132, a plurality of leads 134 and a chip 136. The substrate 132 has an opening 1 32a. The leads 134 are disposed around the opening 132a of the substrate 132, and each lead 134 has an inner lead 134a and an outer lead 1 34b. A portion of the outer lead I 34b is electrically connected to the display panel 110 and another portion of the outer lead 1 34b is electrically connected to the corresponding circuit board 120 by using anisotropic conductive film (ACF) 140. The chip 136 is disposed close to the opening 132a of the substrate 132.In addition, the chip 136 has a plurality of contact points 1 36a electrically connected to the inner lead 1 34a. Moreover, a sealing material 150 covers the chip 136 of the tape carrier package structure 130.
However, in the package process of the display panel 110 and the circuit board 120 using the tape carrier package structure 130, the influence of particles on the yield of the package process should be considered.
FIG. 3 is a schematic cross-sectional side view of the tape carrier package structure, a portion of the display panel and a portion of the circuit board along line B- B' of FIG. 1. Referring to FIG. 3, a conventional tape carrier package structure 130 is electrically connected to the display panel 110 and the circuit board 120 by using the anisotropic conductive film 140. However, a bevel region 112 is generally designed on the display panel 110. Since variation may occur when bonding the package structure and the display panel 110, in general, the anisotropic conductive film 140 is moved towards the inner side of the display panel 110 for adhesion so that the anisotropic conductive film 140 may be far away from the bevel region 112.
However, as described above, a larger space is formed in the bonding region of the display panel 110 and the anisotropic conductive film 140. Consequently, particles are easily to fall in the space. Accordingly, abnormal short circuit or open circuit may be occurred between the package structure 130 and the display panel 110.
SUMMARY OF THE INVENTION
Therefore, the present invention is directed to a display for preventing accumulation of particles in the region between the display panel and the package structure. Therefore, the yield of manufacturing the display may be enhanced and the lifetime of the display is also increased.
In addition, the present invention is also directed to a carrier package structure for preventing accumulation of particles in the region between the display panel and the package structure. Therefore, the yield of manufacturing the display may be enhanced and the lifetime of the display is also increased.
The present invention provides a display. The display comprises a display panel, at least a circuit board and at least a tape carrier package structure. The circuit board is disposed at a side of the display panel, and the tape carrier package structure is disposed between the display panel and the circuit board. The tape carrier package structure comprises a substrate, a plurality of leads, a chip and a blocking bar or protrusion. The substrate includes an opening. The leads are disposed around an opening of the substrate, and each of the leads comprises an inner lead and an outer lead. In addition, a portion of the outer leads is electrically connected to the display panel, and another portion of the outer leads is electrically connected to the circuit board correspondingly. The chip is disposed at the opening of the substrate and comprises a plurality of contact points electrically connected to the inner leads. The blocking bar is disposed on the substrate between the chip and the display panel.
In one embodiment of the present invention, the tape carrier package structure further comprises another blocking bar disposed on the substrate between the chip and the circuit board.
In one embodiment of the present invention, the blocking bar and the substrate are formed as an integral structure.
In another embodiment of the present invention, the blocking bar is adhered to the substrate.
In one embodiment of the present invention, the display further comprises an anisotropic conductive film disposed between the outer leads of the tape carrier package structure and the display panel so that the tape carrier package structure and the display panel are electrically connected.
In one embodiment of the present invention, the display further comprises an anisotropic conductive film disposed between the outer leads of the tape carrier package structure and the circuit board so that the tape carrier package structure and the circuit board are electrically connected.
In one embodiment of the present invention, the display further comprises a sealing material covering the chip of the tape carrier package structure.
The present invention further provides a display. The display comprises a display panel and at least a package structure of chip on FPC. The package structure of chip on FPC is disposed at a side of the display panel. Each package structure of chip on FPC comprises a flexible printed circuit board, a chip and a blocking bar. The flexible printed circuit board comprises at least two isolation layers and at least a conducting wire layer disposed between the two isolation layers. The chip is disposed on the flexible printed circuit board. Wherein, the chip comprises a plurality of contact points electrically connected to the conductive layer of the flexible printed circuit board. The blocking bar is disposed on the isolation layer of the flexible printed circuit board between the chip and the display panel.
In one embodiment of the present invention, the blocking bar and the isolation layer of the flexible printed circuit board may be formed as an integral structure.
In another embodiment of the present invention, the blocking bar may be adhered to the isolation layer of the flexible printed circuit board.
In one embodiment of the present invention, the display may further comprise an anisotropic conductive film disposed between the package structure of chip on FPC and the display panel so that the package structure of chip on FPC and the display panel are electrically connected.
The present invention provides a tape carrier package structure. The tape carrier package structure comprises a substrate, a plurality of leads, a chip and a blocking bar.
The substrate has an opening. A plurality of leads is disposed around the opening of the substrate. Each lead comprises an inner lead and an outer lead. The chip is disposed at the opening of the substrate and comprises a plurality of contact points electrically connected to the inner leads. The blocking bar is disposed on the substrate at a side of the chip.
In one embodiment of the present invention, the tape carrier package structure further comprises another blocking bar disposed on the substrate at another side of the chip.
In one embodiment of the present invention, the blocking bar and the substrate may be formed as an integral structure.
In another embodiment of the present invention, the blocking bar may be adhered to the substrate.
In one embodiment of the present invention, the tape carrier package structure may further comprise an anisotropic conductive film disposed between the outer leads of the tape carrier package structure and the display panel so that the tape carrier package structure and the display panel are electrically connected.
In one embodiment of the present invention, the tape carrier package structure may further comprise an anisotropic conductive film disposed between the outer leads of the tape carrier package structure and the circuit board so that the tape carrier package structure and the circuit board may be electrically connected.
In one embodiment of the present invention, the tape carrier package structure may further comprise a sealing material for covering the chip of the tape carrier package structure.
Accordingly, in the present invention, since a carrier package structure with blocking bar or a package structure of chip on FPC with blocking bar is provided, when the display is packaged, particles are prevented from entering the region between the panel and the package structure. Therefore, the problem of short circuit or open circuit between the package structure and the display panel is prevented, the yield of manufacturing the display is improved and the lifetime of the display is enhanced.
One or part or all of these and other features and advantages of the present invention will become readily apparent to those skilled in this art from the following description wherein there is shown and described one embodiment of this invention, simply by way of illustration of one of the modes best suited to carry out the invention.
As it will be realized, the invention is capable of different embodiments, and its several details are capable of modifications in various, obvious aspects all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWiNGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic top view of a display using a conventional tape carrier package structure.
FIG. 2 is a schematic cross-sectional view of the tape carrier package structure along line A-A' of FIG. 1.
FIG. 3 is a schematic cross-sectional side view of the tape carrier package structure, a portion of the display panel and a portion of the circuit board along line B- B' of FIG. 1.
FIG. 4 is a schematic top view of a display according to one embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view of the tape carrier package structure along line C-C' of FIG. 4.
FIG. 6 is a schematic cross-sectional side view of the tape carrier package structure, a portion of the display panel and a portion of the circuit board along line C- C' of FIG. 4.
FIG. 7 is a schematic local back-side view of a tape carrier package structure of FIG. 4.
FIG. 8 is a schematic view of a display packaged by chip on FPC structure according to one embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view of a flexible printed circuit board along line E-E' of FIG. 8.
DESCRIPTION OF EMBODIMENTS
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
FIG. 4 is a schematic top view of a display according to one embodiment of the present invention. Referring to FIG. 4, a display 200 comprises a display panel 210, at least a circuit board 220 and at least a tape carrier package structure 230. The display panel 210 includes a display area 212 and a non-display area 214. The display area 212 includes a plurality of scan lines 21 2a and a plurality of data lines 21 2b. A plurality of pixel units 212c are defined by the scan lines 212a and the data lines 212b. If the display 200 is a liquid crystal display (LCD), each pixel unit 212c comprises, for example, a thin film transistor (TFT) (not shown), a liquid crystal layer (not shown) and a color filter (not shown). The pixel unit 2l2c displays images via the voltage signals provided by the scan lines 21 2a and the data lines 21 2b. In addition, some peripheral circuits disposed in the non-display area 214 may be adopted for electrically connection with the tape carrier package structure 230.
Referring to FIG. 4, the circuit board 220 is disposed at a side of the display panel 210, and the tape carrier package structure 230 is disposed between the display panel 210 and circuit board 220. Therefore, the tape carrier package structure 230 is used for electrically connecting the display panel 210 and the circuit board 220.
FIG. 5 is a schematic cross-sectional view of the tape carrier package structure along line C-C' of FIG. 4. Referring to FIG. 5, the tape carrier package structure 230 comprises a substrate 232, a plurality of leads 234, a chip 236 and a blocking bar 238.
The substrate 232 comprises an opening 232a. The leads 234 are disposed around the opening 232a of the substrate 232, wherein each lead 234 comprises an inner lead 234a and an outer lead 234b. As shown in FIG. 4, by using the anisotropic conductive film 240, a portion of the outer leads 234b are electrically connected to the display panel 210, and another portion of the outer leads 210 are electrically connected to the corresponding circuit board 220.
Referring to FIG. 5, the chip 236 is disposed around the opening 232a of the substrate 232 and comprises a plurality of contact points 236a. Wherein, the contact points 236a are electrically connected to the inner lead 234a. In one embodiment of the present invention, a sealing material 250 may further provide for covering the chip 236 in the tape carrier package structure 230 to avoid the damage of the chip 236 and the contact points 236a contacted to the inner leads 234a by moisture or oxygen. The blocking bar 238 shown in FIG. 4 and FIG. 5 will be described in detail as follows.
FIG. 6 is a schematic cross-sectional side view of the tape carrier package structure, a portion of the display panel and a portion of the circuit board along line C- C' of FIG. 4. FIG. 7 is a schematic local back-side view of a tape carrier package structure of FIG. 4. Referring to FIG. 6and FIG. 7, note that the blocking bar 238 disposed over the substrate 232 between the chip 236 and the display panel 210 is to prevent particles 260 from entering the region between the display panel 210 and the carrier package structure 230. Therefore, the package structure with the blocking bar 238 eliminates the abnormal short circuit or open circuit due to the particles 260.
Referring to FIG. 6 and FIG. 7, in another embodiment of the present invention, each tape carrier package structure 230 may further comprise another blocking bar 238a disposed over the substrate 232 between the chip 236 and the circuit board 220 to prevent the particles 260 from entering the region between the carrier package structure 230 and the circuit board 220. In other words, if the two blocking bar 238, 238a are disposed simultaneously, prevention of the particles 260 entering the carrier package structure 230 can be improved.
In addition, in one embodiment of the present invention, the blocking bar 238 and the substrate 232 may be, for example, formed as an integral structure. In other words, the blocking bar 238 may be formed on the carrier tape of the manufacturing tape carrier package structure 230 when the carrier tape is manufactured. Moreover, the blocking bar 238 may also be adhered on the substrate 232.
Referring to FIG. 4 and FIG. 6, in one embodiment of the present invention, an anisotropic conductive film 240 may further be disposed between the outer lead 234b of each tape carrier package structure 230 and the display panel 210 50 that the tape carrier package structure 230 and the display panel 210 can be electrically connected. In addition, another anisotropic conductive film 240 may also be disposed between the outer lead 234b of each tape carrier package structure 230 and the circuit board 220 so that the tape carrier package structure 230 and the circuit board 220 can be electrically connected. The anisotropic conductive film 240 comprises a gel composed of metal particles and polymer material. The carrier package structure 230, the display panel 210 and the circuit board 220 can be electrically connected for transmitting electronic signals by using the anisotropic conductive film 240.
In the present invention, since the tape carrier package structure 230 includes a blocking bar 238, and the blocking bar 238 may be disposed on the substrate 232 at a side of the chip 236a, so that the blocking bar 238 may be provided for preventing the entering of the particles 260 into the region between the chip 236 and the display panel 210. Therefore, the abnormal short circuit or open circuit due to the particles 260 can be avoided.
In another embodiment of the present invention, each tape carrier package structure 230 may comprise, for example, another blocking bar 238a (as shown in FIG. 6) disposed on the substrate 232 at another side of the chip 236. The blocking bar 238a and substrate 232 may be formed as an integral structure or adhered on the substrate 232. The tape carrier package structure 230 with the blocking bar will effectively block particles. Therefore, the tape carrier package structure 230 of the present invention will enhance the yield of electricity contact. Thus, the present invention may not only be applied to various displays, but also to package structures such as mobile phones, notebooks or other electronic products so that the stability of the electronic products can be enhanced.
FIG. 8 is a schematic view of a display packaged by chip on FPC structure according to one embodiment of the present invention. Referring to FIG. 8, the display 300 comprises a display panel 310 and at least a package structure 320 of chip on flexible printed circuits board (chip on FPC, COF). The display panel 310 comprises a display area 312 and a non-display area 314. The display area 312 comprises a plurality of scan lines 31 2a and a plurality of data lines 31 2b. Wherein, a plurality of pixel units 312c is defined by the scan lines 312a and the data lines 312b. If the display 300 is a liquid crystal display, each pixel unit 312c comprises, for example, a thin film transistor (TFT) (not shown), a liquid crystal layer (not shown) and a color filter (not shown). If the display 300 is an organic electroluminescence display (OLED), thus the pixel unit 31 2c comprises, for example, an active component (not shown) and an organic electroluminescence (OEL) component (not shown). Accordingly, the pixel unit 31 2c displays images by the electronic signals transmitted from the scan lines 31 2a and the data lines 312b.
Referring to FIG. 8, the package structure 320 of chip on FPC is disposed at a side of the display panel 310. Each package structure 320 of the chip on FPC includes a flexible printed circuit board 322, a chip 324 and a blocking bar 326.
FIG. 9 is a schematic cross-sectional view of a flexible printed circuit board along line E-E' of FIG. 8. Referring to FIG. 9, the flexible printed circuit board 322 comprises at least two isolation layers 322a and 322b and at least a conducting wire layer 322c disposed between the two isolation layers 322a and 322b. The chip 324 is disposed over the flexible printed circuit board 322. In addition, the chip 324 comprises a plurality of contact points 324a electrically connected to the conductive layer 322c of the flexible printed circuit board 322. Referring to FIG. 8, note that the blocking bar 326 is disposed on the isolation layer 322b of the flexible printed circuit board 322 between the chip 324 and the display panel 310. The blocking bar 326 will prevent particles (not shown) from entering the region between the display panel 310 and the chip 324 so that the abnormal short circuit or open circuit due to the particles can be avoided.
Next, referring to FIG. 9, in one embodiment of the present invention, the blocking bar 326 and the isolation layer 322b of the flexible printed circuit board 322 may be formed as an integral structure or may be adhered to the isolation layer 322b of the flexible printed circuit board 322.
Referring to FIG. 8, in one embodiment of the present invention, an anisotropic conductive film 330 may further be disposed between the package structure 320 of the chip on FPC and the display panel 310 so that the package structure 320 of the chip on FPC and the display panel 310 may be electrically connected for transmitting electronic signals.
In summary, the display and tape carrier package structure of the present invention have the following advantages.
(1) The package structure of the display of the present invention includes blocking bar for preventing particles from entering the region between the chip and the panel. Therefore, the problem of abnormal short circuit or open circuit of the electronic components can be avoided.
(2) Application of the package structure of the present invention will enhance the yield of manufacturing the display so that the lifetime of the display can also be improved.
(3) The package structure of the present invention can be adopted for the package process of other electronic products to upgrnde the stability of the electronic products.
The foregoing description of the embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed.
Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defmed by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
Claims (22)
- CLAIMS: 1. A display, comprising: a display panel; a circuit board,disposed on a side of the display panel; and a tape carrier package structure, including: a substrate having an opening disposed in between the display panel and the circuit board; a plurality of leads, disposed on the substrate and around the opening of the substrate, and each of the leads having an inner lead and an outer lead, wherein, a portion of outer leads are electrically connected to the display panel, and an another portion of outer leads are electrically connected to the circuit board; a chip, having a plurality of contact points, is disposed at the opening of the substrate, and the contact points are electrically connected to the inner leads; and a protrusion, disposed on the substrate between the chip and the display panel.
- 2. The display of claim 1, wherein the protrusion comprises a strip shape.
- 3. The display of claim 1 or 2, wherein the protrusion comprises a plurality of block shapes.
- 4. The display of claim 1, 2 or 3, wherein the protrusion and the substrate are formed as an integral structure.
- 5. The display of any one preceding claim, wherein the protrusion's material composition comprises a non-conducting material.
- 6. The display of any one preceding claim, wherein the protrusion's material composition comprises an organic polymer material.
- 7. The display of any one preceding claim, wherein further comprising a sealant, encapsulating the chip in the Chip on FPC in tape carrier package.
- 8. A display, comprising: a display panel; and a package structure of chip on a flexible printed circuit board (chip on FPC) comprising: a flexible printed circuit board, disposed on a side of the display panel, wherein the flexible printed circuit board comprises a plurality of isolation layers and is disposed at a conducting wire layer between the isolation layers; a chip, comprising of a plurality of contact points, disposed on the flexible printed circuit board, wherein the contact points are electrically connected to the conductive layer; and a protrusion, disposed on the flexible printed circuit board between the chip and the isolation layers.
- 9. The display of claim 8, wherein the protrusion comprises a strip shape.
- 10. The display of claim 8 or 9, wherein the protrusion comprises a plurality of block shapes.
- 11. The display of claim 8, 9 or 10, wherein the protrusion and the substrate are formed as an integral structure.
- 12. The display of any one of claims 8 to 11, wherein the protrusion material composition comprises a non-conducting material.
- 13. The display of any one of claims 8 to 12, wherein the protrusion material composition comprises an organic polymer material.
- 14. A tape carrier package structure, comprising: a substrate, having an opening; a chip, comprising a plurality of contact points, disposed at the opening of the substrate; a plurality of leads are disposed on the substrate, wherein each lead comprises an inner lead and an outer lead, and the contact points are electrically connected to the inner leads; and a protrusion, disposed on the substrate on a side of the chip.
- 15. The display of claim 14, wherein the protrusion comprises a strip shape.
- 16. The display of claim 14 or 15, wherein the protrusion comprises a plurality of block shapes.
- 17. The display of claim 14, 15 or 16, wherein the protrusion and the substrate are formed as an integral structure.
- 18. The display of any one of claims 14 to 17, wherein the protrusion material composition comprises a non-conducting material.
- 19. The display of any one of claims 14 to 18, wherein the protrusion material composition comprises an organic polymer material.
- 20. The display of any one of claims 14 to 19, wherein the sealant, encapsulating the chip in the Chip on FPC in tape carrier package.
- 21. A display as hereinbefore described with reference to figures 4 to 9 of the accompanying drawings.
- 22. A method of fabricating a display as hereinbefore described with reference to figures 4 to 9 of the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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GB0712713A GB2437665B (en) | 2005-07-12 | 2007-06-29 | Display and carrier package structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW094123505A TWI258032B (en) | 2005-07-12 | 2005-07-12 | Display and tape carrier package structure |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0608759D0 GB0608759D0 (en) | 2006-06-14 |
GB2428327A true GB2428327A (en) | 2007-01-24 |
GB2428327B GB2428327B (en) | 2008-01-23 |
Family
ID=36603861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0608759A Expired - Fee Related GB2428327B (en) | 2005-07-12 | 2006-05-03 | Display And Tape Carrier Package Structure |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP4252568B2 (en) |
DE (1) | DE102006020853A1 (en) |
FR (1) | FR2888666B1 (en) |
GB (1) | GB2428327B (en) |
TW (1) | TWI258032B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9978674B2 (en) | 2016-04-05 | 2018-05-22 | Samsung Electronics Co., Ltd. | Chip-on-film semiconductor packages and display apparatus including the same |
CN108447396B (en) * | 2018-02-26 | 2020-11-03 | 上海天马微电子有限公司 | Display device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5767571A (en) * | 1995-06-16 | 1998-06-16 | Hitachi, Ltd | Semiconductor device and display unit using the semiconductor device and notebook-size personal computer |
EP0940709A1 (en) * | 1998-03-06 | 1999-09-08 | Nec Corporation | Liquid crystal display apparatus having stepped section in glass substrate |
JP2000183470A (en) * | 1998-12-16 | 2000-06-30 | Sony Corp | Wiring where migration is prevented and its prevention method |
-
2005
- 2005-07-12 TW TW094123505A patent/TWI258032B/en not_active IP Right Cessation
- 2005-10-11 JP JP2005296805A patent/JP4252568B2/en not_active Expired - Fee Related
-
2006
- 2006-05-03 GB GB0608759A patent/GB2428327B/en not_active Expired - Fee Related
- 2006-05-04 DE DE102006020853A patent/DE102006020853A1/en not_active Ceased
- 2006-05-24 FR FR0604708A patent/FR2888666B1/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5767571A (en) * | 1995-06-16 | 1998-06-16 | Hitachi, Ltd | Semiconductor device and display unit using the semiconductor device and notebook-size personal computer |
EP0940709A1 (en) * | 1998-03-06 | 1999-09-08 | Nec Corporation | Liquid crystal display apparatus having stepped section in glass substrate |
JP2000183470A (en) * | 1998-12-16 | 2000-06-30 | Sony Corp | Wiring where migration is prevented and its prevention method |
Also Published As
Publication number | Publication date |
---|---|
JP4252568B2 (en) | 2009-04-08 |
TW200702785A (en) | 2007-01-16 |
TWI258032B (en) | 2006-07-11 |
DE102006020853A1 (en) | 2007-02-15 |
GB2428327B (en) | 2008-01-23 |
GB0608759D0 (en) | 2006-06-14 |
FR2888666B1 (en) | 2010-06-11 |
FR2888666A1 (en) | 2007-01-19 |
JP2007027672A (en) | 2007-02-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20200503 |