GB2412194A

GB2412194A - Reprogramming a non-volatile memory system

Info

Publication number: GB2412194A
Application number: GB0406238A
Authority: GB
Inventors: David Gordon
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2004-03-19
Filing date: 2004-03-19
Publication date: 2005-09-21
Also published as: WO2005091302A1; GB0406238D0

Abstract

A non-volatile memory system is provided. The system comprises non-volatile memory divided into a plurality of segments each segment having an address in an address space and wherein at least one of the segments is unused. The system further comprises means for copying any one segment to be reprogrammed into a RAM, the RAM having a size at least equal to the segment size, means for reprogramming the contents of the RAM, means for erasing the unused segment, writing means for writing the reprogrammed code into the at least one unused memory segment, and control means arranged to amend the address space to show the same address of the reprogrammed segment.

Description

REPROGRAMMING A NON-VOLATILE SOLID STATE MEMORY SYSTEM

The present invention relates to the reprogramming of a part of a memory system that uses non-volatile memory and, particularly, to reprogramming a segmented memory system within an embedded processor system, for example Flash memory.

In the past non-volatile Flash memory has been treated as contiguous and, possibly continuous, area of storage. Larger systems are known that comprise several Flash memory chips which may not be adjoining in the memory space. When a change is required, therefore, the entire memory is reprogrammed. This is undesirable for a number of reasons. Firstly, as the amount of data to be transferred to an electronic device increases so the time taken for reprogramming also increases. During this, increasingly lengthy, reprogramming process the electronic device is not in a usable state.

One approach that has been used to attempt to overcome these problems is that of segmenting the memory. US-A-6295603 discloses a system incorporating a segmented control memory. This invention seeks to overcome the problem of overwriting programme code vital to the system boot-up process.

The segmentation of the memory, along with the provision of segment pointers, results in the memory area containing the programme to be executed not being mapped onto a specific location within the memory. Manipulation of the address pointers is then used to minimise the chance of an inadvertent overwriting of the boot up code.

It is evident from this document that the segmentation of a solid state memory is a powerful tool. However, the system disclosed in US-A-6295603 makes only passive, rather than active use of segmentation to prevent unwanted overwriting of certain sections of a memory.

There are existing techniques that provide multiple "banks" of program memory. The concept behind such systems is as follows: there are two banks of memory A and B. Whilst bank A is executing the current version of the software software A, bank B can be reprogrammed with new software, software B. When the reprogramming is complete, the system is instructed using a soft reset to use the new software. Although this does facilitate reverting to software A in the event of a problem with software B. there is a requirement for double the memory required for bank A alone. Furthermore, the redirection of the system to read from the other memory bank requires a soft reset and this causes an interruption in service.

In other systems known in the art the new version of the programme directly overwrites the old version. It is therefore not possible to regress to the earlier version of the programme if, for some reason, the reprogramming is unsuccessful and the new version of the programme fails to operate correctly.

This is a very unsatisfactory state of affairs as it renders functional, if out of date, data and programmed, entirely unusable.

The present invention has been developed to overcome these problems.

According to the present invention there is provided a non-volatile memory system comprising: non-volatile memory divided into a plurality of segments each segment having an address in an address space and wherein at least one of the segments is unused, means for copying any one segment to be reprogrammed into a RAM, the RAM having a size at least equal to the segment size, means for modifying the contents of the RAM, means for erasing the unused segment, writing means for writing the reprogrammed code into the at least one unused memory segment, and control means arranged to amend the address space to show the same address of the reprogrammed segment.

The segments are all of equal size so that any segment of non-volatile memory can occupy any segment in the address space. The RAM is at least equal in size to a single memory segment and therefore any segment of the non-volatile memory can be reprogrammed using the RAM and can subsequently be copied to any available segment of non-volatile memory.

At least one segment of the non-volatile memory is unused. This means that there is always an available segment to write the reprogrammed segment to, other than the segment from which it was originally copied. This enables the regression discussed above.

Preferably each segment contains some unused space. This space is preferably a small proportion of the segment. This space allows for the reprogrammed version being of a larger size than the original version.

The control means may comprise either a custom logic design or appropriate internal logic components.

The area of RAM to be used in this technique is equal in size to a single memory segment. This facilitates a 1:1 transfer between any non-volatile memory segment and the RAM and then subsequent 1:1 transfer of the modified segment in the RAM to any available memory segment.

Furthermore, according to the present invention there is provided a method of reprogramming a non-volatile solid state memory system comprising a plurality of equal size segments each segment having an address in an address space, a RAM at least equal in size to a single memory segment, and control means capable of altering the address of any one of the address corresponding to the individual segments in the address space, whilst the system is active, the method comprising the steps of: copying at least one segment to be reprogrammed into RAM, modifying the contents of the RAM, erasing the contents of the at least one unused memory segment, writing the reprogrammed code into the at least one unused memory segment, and amending the address space to show the same address of the reprogrammed segment.

Preferably, the segment containing the earlier version is designated as unused. This "unused" segment can subsequently be written to during a later upgrade. However, the fact that the contents of the unused segment are not automatically deleted allows the regression to an earlier version if, for some reason, the reprogramming is unsuccessful and the amended version is not fully functional.

Preferably the amendment to the address space is synchronized with the S processor execution so that no code is executed from the segment to be modified while the non-volatile segment and the RAM segment are being exchanged. This avoids any interruption to the use of the device of which the embedded processor forms a part.

Preferably there is furthermore provided a user interface for managing the method of reprogramming according to the present invention. The user interface is designed to guide the user through the reprogramming a non volatile solid state memory system comprising a plurality of segments each segment having an address in an address space, a RAM at least equal in size to a single memory segment, and control means capable of altering the address of any one of the address corresponding to the individual segments in the address space, whilst the system is active, the user interface comprising: a graphical representation of the embedded processor showing the contents of each segment, means for selecting the segment to be reprogrammed, and means of initiating the method of reprogramming described above.

An example of the present invention will now be described with reference to the following figures in which: Figures 1, 2 and 3 show affected parts of a processor system according to the present invention undergoing reprogramming.

Figure 4 is a schematic showing the connectivity of the embedded system of which the processor system of the present invention forms a part; Figures 5a, b and c show the graphical user interface of the present invention during the reprogramming.

Each of Figures 1 to 3 shows affected parts of a processor system 10 according to the present invention. The processor system 10 comprises a non volatile memory 1 1 which, in this example, is divided into a number of segments S' to Sg. In this example Segment SO is empty. It will be appreciated that the invention can be applied to a memory with other numbers of segments. Each of these segments S' to SO has a corresponding address in address space A1- A9. The processor system 10 also contains an area of RAM that is the same size as one of the segments 11 and a memory management unit (MMU) or other logic to control the switching of segments within the address space.

The process of reprogramming one segment, in this case segment S4, is shown in Figures 1, 2 and 3. Figure 1 represents the initial situation with each segment residing at an address having the same subscript as the segment number. The segment S4 is to be modified. It is therefore copied into the RAM and the version residing in the RAM is modified with the required changes. The reprogrammed version is called S'4, and is shown in Figure 2. The amended segment S'4 is reprogrammed into the empty segment previously called SO and the memory management unit MMU amends the address information so that the amended segment S'4 is at address A4 and the address Ag is applied to the segment containing the original version of segment S4, as shown in Figure 3.

This segment, containing the original version of S4 is now construed to be available as a target for further reprogramming steps.

Figure 4 shows the processor system 10 within the context of a computer system 1. The volatile memory 11 and RAM communicate with the processor via a system bus15 and address control logic 14 that processes the change of address information required during the reprogramming. The graphical user interface appears on a display 16 to enable the user to instruct the reprogramming operation. This is convenient as the user must be able to control the process despite the fact that it is embedded deep within the computer system 1. Information from the processor 10 and address control logic 14 is supplied to the display 16 via the system bus 15 and display control logic 17. The user can use a mouse, touch screen or other suitable pointer to input commands which are subsequently fed back to the processor 10 via screen control logic 18. Alternatively the user can input commands through a keypad 19 that is connected, via keypad control logic 20, to the system bus 15.

Figures 5a, b and c show the graphical user interface at various stages during the reprogramming process. The first step is to download the package to the system. This will result in the window shown in Figure 5a asking "Which Flash segment to update?" The user must then select a segment number "n" and proceed by either clicking the "OK" icon within the window, or giving a suitable command via the keyboard. The processor 10 then begins the reprogramming process and the user is informed of the progress of the reprogramming by a window that progresses from that shown in Figure 5b to that shown in Figure 5c as the process proceeds. This window is for information only as the user cannot interrupt the process once it has been initiated.

Claims

1. A non-volatile memory system comprising: non-volatile memory divided into a plurality of segments each segment having an address in an address space and wherein at least one of the segments is unused, means for copying any one segment to be reprogrammed into a RAM, the RAM having a size at least equal to the segment size, means for modifying the contents of the RAM, means for erasing the unused segment, writing means for writing the reprogrammed code into the at least one unused memory segment, and control means arranged to amend the address space to show the same address of the reprogrammed segment.

2. The system according to claim 1, wherein the segments are substantially equal In size.

3. The system according to claim 1 or claim 2, wherein each segment contains some unused space.

4. The system according to any of claims 1 to 3, wherein the control means comprises internal logic components.

5. A method of reprogramming a non-volatile solid state memory system comprising a plurality of equal size segments each segment having an address in an address space, a RAM at least equal in size to a single memory segment, and control means capable of altering the address of any one of the address corresponding to the individual segments in the address space, whilst the system is active, the method comprising the steps of: copying at least one segment to be reprogrammed into RAM, modifying the contents of the RAM, erasing the contents of the at least one unused memory segment, writing the reprogrammed code into the at least one unused memory segment, and amending the address space to show the name address of the reprogrammed segment.

6. The method according to claim 5, wherein the segment containing the earlier version is designated as unused.

7. The method according to claim S or claim 6, wherein the amendment to the address space is synchronized with the processor execution.

8. A user interface for guiding a user through a reprogramming a non volatile solid state memory system comprising a plurality of equal size segments each segment having an address in an address space, a RAM at least equal in size to a single memory segment, and control means capable of altering the address of any one of the address corresponding to the individual segments in the address space, whilst the system is active,, the user interface comprising: a graphical representation of the embedded processor showing the contents of each segment, means for selecting the segment to be reprogrammed, and means of initiating the method of reprogramming according to any of the claims 5 to 7.