GB2410373A - DRAM storage electrode having curved fins - Google Patents
DRAM storage electrode having curved fins Download PDFInfo
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- GB2410373A GB2410373A GB0500291A GB0500291A GB2410373A GB 2410373 A GB2410373 A GB 2410373A GB 0500291 A GB0500291 A GB 0500291A GB 0500291 A GB0500291 A GB 0500291A GB 2410373 A GB2410373 A GB 2410373A
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- 238000003860 storage Methods 0.000 title claims abstract description 170
- 125000006850 spacer group Chemical group 0.000 claims description 89
- 239000004065 semiconductor Substances 0.000 claims description 79
- 238000000034 method Methods 0.000 claims description 55
- 239000000758 substrate Substances 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 3
- 235000020639 clam Nutrition 0.000 claims 2
- JCYWCSGERIELPG-UHFFFAOYSA-N imes Chemical compound CC1=CC(C)=CC(C)=C1N1C=CN(C=2C(=CC(C)=CC=2C)C)[C]1 JCYWCSGERIELPG-UHFFFAOYSA-N 0.000 claims 2
- 241000237519 Bivalvia Species 0.000 claims 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- 210000000078 claw Anatomy 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005452 bending Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 208000031481 Pathologic Constriction Diseases 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- 239000000454 talc Substances 0.000 description 1
- 229910052623 talc Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 210000002268 wool Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H01L27/10808—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
Abstract
The storage electrodes comprise upright curved fins 425 which are supported by an insulating structure 440. The curved fins are formed by patterning a series of conductive lines formed into a wave-shape when viewed from above.
Description
24 1 0373
SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR
MANUFACTURING THE SAME USING SIDEWAL1. SPACERS
Field of the invention
The present nventon relates to semiconductor memory devices and methods for manutacturng the same, and more particularly to storage nodes for semiconductor memory devices and methods for manut'acturng the same. s
Background of the Invention
As scmconductor memory devices have become highly integrated, the areas of unit cells and the distances between cells may be reduced. However, capacitors leaving a large capacitance within small areas are desired, to provide predetermined l 0 capacitances. As is well known to those having skill in the art, semiconductor nenory device capacitors ncluLle a lower electrode, also referred to as a storage node electrode, an upper electrode, also ret'erred to as a plate electrode, and a dielectric layer therebetween. Conventional methods for securing large capacitances of the capacitors Include using a high dielectric material as the dielectric layer, reducing the l 5 thickness of a dielectric layer, andlor increasing the surface area of storage node electrodes of the capacitors.
A method for increasing the surface area of the storage node electrodes includes forming three-dinensional storage node electrodes, for example, cylindrical or concave electrodes.
2() FIG. l is a sectional view illustrating conventional concave storage node elec bodes Refen-nlg to FIG. 1, an nterlevel insulating layer 12 Is formed on a semiconductor substrate 10 having circuit devices (not shown), such as MOS transistors The interlevel insulating layer 12 includes storage node contact plugs 14 that are widely known to connect a source region (not shown) of a selected MOS transistor with storage node electrodes 16, which will be formed in a subsequent process Thereat'ter, the cup-shaped concave storage node electrodes 16 are formed on the predetermined portions of the storage node contact plugs 14 and the nterlevel insulating layer 12. A method for torrnng the concave storage node electrodes 16 is as follows. First, a mold oxide layer (not shown) having a predetermined thickness Is deposited on the nterlcvel msulatng layer 12 including the storage node contact plu;,s 14. The mold oxide layer Is etched into hole shapes until exposing the storage node contact plugs 14, thereby defining a region for forming the storage node electrodes Thereafter, a conductive layer (not shown) and a node isolation insulating layer (riot shown) are subseclcently formed on the mold oxide layer so as to contact the exposed storage node contact plugs 14 The condtctve layer and the node isolation nstlatmg layer are chemical mechamcaI polished to expose the surface of the wool oxide layer. Thereafter, the node Isolation msulatng layer and the mold oxide layer are removed by a conventional method so that the concave storage node electrodes 16 are formed tlowever, the concave storage node electrodes formed by the above-descrbed method may have tle following problems.
In order to manufacture tile storage node electrodes having large capacitance, tile light of the storage node electrodes may need to bc increased within a limited area. In addition, in order to increase the height of the storage node electrodes, the Slickness ol'the mold oxide layer may need to be increased. In this case, when the mold oxide layer is etched to define the region for forming the storage node electrodes, a large slope may occur on the sidewalls of the holes, and the cntcal dimension of the exposed storage node contact holes may be reduced. Accordingly, the lower portions of the thin and high storage node electrodes may become narrower so that tile storage node electrodes may become unstable. In addition, the distance between adjacent storage node electrodes nnay be reduced so that it may be dit'ficult to provide insulation between the storage node electrodes.
Furtllelllore, due to thermal stress generated In subsequent processes, some of tile weak storage node electrodes may fall or break and generate bridges between unit storage node electrodes, thereby causing defects m the device.
Summary of the Invention
An aspect of the present invention provides a semiconductor memory device 3() comprsng a semiconductor substrate, an interlevel insulating layer on the semcondtctor substrate, storage node contact plugs in the mterlevel insulating layer, and storage node electrodes, which comprise a plurality of conductive line patterns separated m predetermined intervals while having a predetermined height, contacting tile storage node contact plugs, wherein, the storage node electrodes are separated by mslllatmg brie patterns between selected storage node electrodes m units of a unit cell ofthe memory device.
Another aspect of the present invention provides a semiconductor memory device conpusmg an mterlevel rnsulatmg layer on a semiconductor substrate mcludng a plurality of active regrows, a plurahty of word line structures passing over the active regions, source and drain regions on the active regions at respective sides of the word line structures, and a plurality of bit lme structures crossing the word Lee structures, electrically connecting to the dram regions, and passing between the active regions; etch stoppers on the intcrlevel insulating layer; storage node contact plugs I () fonned n1 the nterlevel insulating layer and the etch stoppers; storage node electrodes, which comprise a plurality of conductive brie patterns separated in piedetermmecl intervals while having a predetermined height, contacting to the storage node contact plugs; and supporters between the storage node electrodes and extending perpcndcular to an extending direction of the One patterns of the storage node electrodes In these embodiments, the plurality of brie patterns are formed into straight hoes.
Another aspect of the present invention provides a semiconductor memory device comprising an mterlevel rnsulatmg layer on a semiconductor substrate mcludmg a plurality of active regions, a plurality of word line structures passing over the active regions, source and dram regions on the active regions at respective sides of the word One structures, and a plurahty of bit line structures crossing the word line strrctcrres, electrically connecting to the drain regions, and passing between the active regions; etch stoppers on the interlevel insulating layer; storage node contact plugs in the nterlevel msulatng layer and the etch stoppers; storage node electrodes, which comprise a plurality of conductive hne patterns separated in the same intervals while havmg a specrtic height, contacting the storage node contact plugs; and supporters between the storage node electrodes while being perpendicular to an extending direction of the brie patterns of the storage node electrodes. In these embodiments, the plurality ol lme patterns are formed in the shape of waves in a plan view.
In another aspect of the present mventron, there are provided methods of rnancfacttrrng a semiconductor memory device In these methods, an rnterlevel insulating layer- is deposited on a semiconductor substrate, and a plurahty of storage node contact plugs are tonned m the mterlevel insulating layer- m specific intervals.
T hereafter, mold oxrcle layer patterns are formed on the interlevel msulatmg layer in specs tic intervals to expose the storage node contact plugs, and the spaces between the Hold oxide layer patterns are filled by alternately forming conductive lme patterns and insulating brie patterns, repeatedly, on the sidewalls of the mold oxide layer patterns (Jrooves are formed perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the nlsulatmg hne patterns. Storage node electrodes are Conned by selectively rermovng the mold oxide layer patterns and the insulating brie patterns.
In a yet f;rtl-ier aspect of the present invention, there are provided methods t'or manut'acturing a semiconductor memory device. In these methods, a semiconductor substrate, which includes a plurality of active regions, a plurahty of word line structures passmg over the active regions, source and dram regions fonmed on the active regions at respective sides of the word line structures, and a plurahty of bit brie structures crossing the word brie structures, electrically connecting to the drain regions, and passing between the active regions, is prepared An mterlevel insulating layer is Conned on the semiconductor substrate, etch stoppers are formed on the mterlevel msulatng layer, and storage node contact plugs are formed in the mterlevel insulating layer and the etch stoppers at specific intervals. Thereafter, a plurality of mold oxide layer patterns are fonmcd on the etch stoppers at specific intervals to expose the storage node contact plugs. The spaces between the mold oxide layer patterns are tilled by alternately forming at least one conductive line pattern and msulatmg line pattern on the sidewalls of the mold oxide layer patterns in order to follow the shape of the mold oxide layer patterns. Grooves are formed perpendicular to the mold oxide layer patterns by etchmg portions of the mold oxide layer patterns, the conductive line patterns, and the insulating line patterns. Thereafter, supporters ?5 are formed in the grooves, and storage node electrodes are Conned by selectively removing the mold oxide layer patterns and the insulating One patterns. In these embodiments, the mold oxide layer patterns extend into straight hnes and the mold oxide layer patterns and the supporters separate the storage node electrodes m units of each cell.
In a still other aspect of the present mventon, there are provided methods for manuL'actunng, a semiconductor memory device. in these methods, a semiconductor substrate, which includes a plurality of active regions, a plurality of word line structures passing over the active regions, source and drain regions formed on the active regions at respective sides of the word line structures, and a plurality orbit hne structures crossing the word hne structures, electrically connecting to the drain regions, and passing between the active regions, Is prepared An mterlevel Insulating layer Is fowled on the semiconductor substrate, and etch stoppers are formed on the mterlevel nsulatng layer- Thereafter, storage node contact plugs are l'ormed in the mterlevel insulating layer and the etch stoppers at specific intervals, and a plurality of mold oxide layer patterns, which are formed In the shape of waves on a plan view, are fonned on the etch stoppers to expose the storage node contact plugs. The spaces between the mold oxide layer patterns are filled by alternately forming at least one conductive lme pattern and insulating line pattern on the sidewalls of the mold oxide I () layer patterns n1 order to follow the shape of the mold oxide layer patterns Thereal'ter, grooves are funned perpendicular to the mold oxide layer patterns by etching portions ol' the mold oxide layer patterns, the conductive line patterns, and the insulating line patterns. Supporters are formed m the grooves, and storage node electrodes are fonned by selectively removing the mold oxide layer patterns and the msulaling, One patterns. In these embodiments, the mold oxide layer patterns and the supporters separate the storage node electrodes m units of each cell.
Another aspect of the present invention provides a storage node for a semiconductor memory device which includes a pair of spaced apart mold oxide layer patterns on a semiconductor memory device substrate that defines facing mold oxide layer pattern sidewalls. A pair of first conductive spacers are provided, a respective one of which Is on a respective one of the facing mold oxide layer pattern sidewalls and face one anotller. A pair of first insulating spacer is provided, a respective one of which is on a respective one of the pair of first conductive spacers, opposite the respective one of the facing mold oxide layer pattern sidewalls. A pair of second conductive spacers Is provided, a respective one of which Is on a respective one of the pair of first insulating spacers, opposite the respective one of the pair of first conductive spacers At least one second insulating spacer is provided between the pair of second conductive spacers. In some ermbodrments, a single nsclatmg spacer extends between the pair of second conductive spacers.
Storage nodes may be t'abricated according to some embodiments of the present invention by fonnng spaced apart mold oxide layer patterns on a semiconductor memory device substrate that define facmg mold oxide layer pattern sidewalls A first conductive spacer is formed on each of the facing mold oxide layer pattern sidewalls. A first nsulatmg spacer Is Donned on each of the first conductive spacers A second conductive spacer Is formed on each of the first insulating spacers i.
and at feast a second insulating spacer is formed on the second conductive spacers. In some embodiments, the lost conductive spacers, the first insulating spacers and the | second conductive spacers are formed by conformally tormmg a conductive or i insulating layer on the tacmg mold oxide layer pattern sidewalls and on the semiconductor memory device substrate therebetween, and then ansotropically etching the conductive or Insulating layer lo remove at least some the layer that is on the semiconductor memory device substrate therebetween.
In other embodnnents of the invention, a storage node for a semiconductor memory device includes a plurality of freestanding storage node electrodes that project away from a semiconductor memory device substrate by a first distance. A supporter is configured to support at least one of the freestanding storage node electrodes and projects away from the semiconductor memory substrate by a second distance that is less than the first distance. In other embodiments, the plurality of teestanding storage nodes extend along two spaced apart rows, and the supporter extends between the two spaced apart rows. Storage nodes may be fabricated by forming the freestanding storage node electrodes and then forming the supporter to support at least one of the freestanding storage node electrodes
Brief Description of the Drawines
FIG I is a sectional view Illustrating a conventional semiconductor memory device having concave storage node electrodes; FIGS 2A throtgh 2D are plan views of stages m the manufacture of a semiconductor memory device according to first embodiments of the present j uvento, it. FIGS. 3A through 3C are sectional views of stages in the manufacture of a semiconductor memory device according to the first embodiments of the present I' mventon, FIG 4 is a perspective view Illustrating a semiconductor memory device according to the first embodiments of the present invention; FIG 5 Is a plan view illustrating a modified semiconductor memory device according, to the first embodiments of the present invention; FIGS 6A through 6D are plan views of stages m the manufacture of a semiconductor memory device according to second embodiments of the present mventron, FIGS 7A and 7B are sectional views of stages in the mantrfacture of a semiconductor memory device according to the second embodiments of the present l invention, I FIG 8 Is a perspective view illustrating a semiconductor memory device according to the second embodiments of the present invention, FIG. 9 Is a plan view illustrating a modified semiconductor memory device according to the second embodiments of the present invention; FIGS. IOA through IOC are sectional views of stages m the manufacture of a semiconductor memory device according to third embodiments of the present llVeT1tiOll; FIGS. 1 1 A through I I D are plan views ot stages in the manufacture of a I 5 semiconductor memory device according to fourth embodiments of the present invention; FIGS. 12A and 12B are sectional views of stages in the manufacture of a sermconductor memory device according to the fourth embodiments of the present invention; FIGS. 13 and 14 are perspective views illustrating a semiconductor memory device according to the fourth embodirrlents of the present invention; FIG. 15 is a plan view Illustrating a modified semiconductor memory device according to the fourth embodiments of the present invention; FIG 16 is a plan view illustrating another modified semiconductor memory device according to the fourth embodiments of the present invention; FIGS. 17\ and 173 are plan views of stages m the manufacture of a semiconductor memory device according to fifth embodiments of the present mventron, and ; FIG 18 Is a plan view illustrating a modified semiconductor memory device ,Y-, 30 according to the fifth embodiments of the present invention.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, m which embodiments of the invention are shown. However, this Invention should not be construed as hunted to the ig embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the | nvcnton to those Allied in the art. In the drawings, the thickness of layers and regions are exag;,erated for clarity I,rke numbers refer to lice elements throughout It Will be understood that when an element such as a layer, region or substrate is referred to as bemg "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or ntervenmg elements may also be present.
In contrast, when an element is referred to as being "directly on" or extending lO "directly onto" another element, there are no intervening elements present.
First Embodiments Reterung to FIGS. 2A and 3A, an isolation layer 110 is formed in a selected region of a semiconductor substrate 100 by a conventional STI method, thereby lS defining active regions 115 on which devices will be formed. Here, the semiconductor substrate 100 may be a silicon substrate Including P-type or N-type hnpurties and may include wells m a predetermined region to form a device. The active regions 115, formed in, for example, a bar shape, are spaced apart by a | predetermined distance in rows and columns. Here, the active regions 115 are arranged to alternate by each row In other words, the spaces between the adjacent active regions 115 correspond to the central portions of the active regions of the subsequent row in the direction of the longer axis of the active regions 115. FIere, the central portions ot the active regions will be drain regions.
Thereafter, word line structures 120 are formed on the semiconductor I 25 substrate 100 Here, the word hne structures 120 are extended to be parallel with one i: another while being perpendicular to the longer axis of the active regions 115. In addition, a pair of word line structures 120 may be arranged for each of the active regions 115. Source and drain regions (not shown) are fonned in the active regions - 115 at both sides of the word brie structures 120 by a conventional method.
i, 30 A first n1terlevel msulatng layer 130 is formed on the semiconductor substrate havmg the word hue strtctures 120 and on the source and dram regions. First and second contact pads 140a and 140b, which contact the source and dram regions while havmg the same height as the first nterlevel insulating layer 130, are formed in the first nterlevel insulating layer 130. A method for formmg the first and second contact pads 140a and 140b will now be described. After the first nterlevel insulate, layer 130 Is donned, the first interlevel Insulating layer 130 is etched to expose the source and dram regions. A conductive layer, for example, a doped polysrlicon layer, Is deposited to contact the exposed source and drain regions, and the conductive layer is etched back or chemical mechanical polished so as to expose the surface of the first interlevel msulatulg layer 130 Accordingly, the first and second contact pads 140a and 140b are formed. Here, the t'irst and second contact pads 140a and 14()b contact the drain region and the source regions, respectively.
A second mterlevel instating layer 150 is fonned on the first nterlevel 1() msclatm,, layer 130 and bit line structures 165 are t'onned on the second interlevel Latin,, layer 150 Here, the bit One structure 165 Includes a bit line 160, a mask layer 162 formed on the bit lme 160, and spacers 164 formed on both walls ofthe bit line] 60 anct the mask layer 162 The mask layers 162 and the spacers 164, t'onned of, for example, silicon mtnde layers, are formed to surround the bit lines 160 In order to t'onn self-algned contact holes when forming storage node contact holes In addition, In some embodiments, the bit brie structures 165 are formed to be perpendicular to the word line structures 120 and that the bit line structures 165 are arranged on the isolation layer 110 between the active regions 115 while being parallel to the longer axis of the active regions. Here, though not shown in the drawings, bit line contact plugs for connecting the first contact pads 140a and the bit line structures 165 are formed in the second nterlevel Insulating layer 150 by a conventional metllod, before t'onning the bit One structures 165.
A third mterlevel msulatmg layer 170 and etch stoppers 175 are sequentially l'onned on the second interlevel msulatng layer 150 having the bit line structures 165.
?5 Here, the first throcgl1 third mterlevel insulating layers 130, 150, and 170 may be tombed of; for example, Insulating layers of the silicon oxide layer group. The etch stoppers 175 are formed ol'msulating layers, for example, silicon nitride layers, having an etchmg selectivity dt'fercnt t'rom the etching selectvites of the second and third mterlevel ins Latin, layers 150 and 170. The etch stoppers 175, the third 3() mterlevel nsulatmg layer 170, and the second interlevel Insulating layer 150 are etched to expose the second contact pads 140b, which contact the source regions, so that storage node contact holes 180 are t'orrned. Here, the storage node contact holes are fonned by a selt'- ahgnm:, method Smog the bit line structures 165. Thereafter, a conductive layer, for example, a doped polysrlcon layer, Is deposited to sut'ficently fill the storage node contact holes 180, and the doped polyslcon layer is chemical rnechamcal pohshed to expose the etch stoppers 175. Accordingly, storage node contact pings 185 are formed Other conventional techniques tor forming a semiconductor memory device substrate may be used.
A mold oxide layer is Conned on the storage node contact plugs 185 and the etch stoppers 175 to a predetermined thclo1ess. [n some embodiments, the mold oxide layer for detennmmg the height of the storage node electrodes is formed to a height higher than the desired hell of the storage node electrodes by a predetermined height, considering that the mold oxide layer will be chemical 1() inechamcal pohshed to the predetermined height in the present embodiments. The mold oxide layer is etched to overlap the bit hne structures 165 so that mold oxide layer patterns 190 are fonned. Here, the mold oxide layer patterns 190 can be formed nil predetermined intervals, for example, one-ptch or two-pitch. The mold oxide layer patterns 190 of FIG 2A are arranged m two-ptch intervals and the mold oxide layer patterns 190 of FIG 5 are arranged in one-ptch intervals. In this respect, the mold oxide layer patterns 190 m the two-pitch intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patterns 190. In addition, the hne width of the mold oxide layer patterns 190 may be equal to or less than the brie width of the bit line structures 165.
Referring to FIG. 3B, a conductive layer for the storage node electrodes, for example, a polyshcon layer, Is deposited on the etch stoppers 175 on which the mold oxide layer patterns 190 are formed. Next, the polysilicon layer is anisotropically etched to form conductive spacers 200 of polyslicon on both walls of the mold oxide layer patterns 190. An insulating layer Is deposited on the resultant structure and anisotropically etched to form insulating spacers 220 on the sidewalls of the conductive spacers 200. By repeatedly forming the conductive spacers 200 and the msulatmg spacers 220, the spaces between the mold oxide layer patterns 190 are tilled l-lere, m order to separate unit cells, the last spacers formed between the mold oxide layer patterns 19(), net, the spacers formed at the center points between the mold oxide layer patterns 190, are the nsulatmg spacers 220. In addition, the conductive spacers 200 are formed to contact the node contact plugs 185 In the present embodiments, the spaces between the mold oxide layer patterns 190 are filled by forming the conductive spacers 200 twice and forming the insulating spacers 220 twice, however, the widths and the numbers of the conductive spacers 200 and the iislatmg spacers 220 can be varied.
Ret'errmg to FIGS. 2B and 3C, the upper surfaces of the mold oxide layer patterns 19O, the conductive spacers 200, and the insulating spacers 220 are chemical mechanical polished to planarze the tipper surfaces so that conductive One patterns 201 and mstlating line patterns 221 and 225 are t'orrned between mold oxide layer patterns 1')1. Here, reference numeral 191 denotes the mold oxide layer patterns having placarded upper surt'aces And, the conductive brie patterns 201 are the conductive spacers 220 having planarzed upper surfaces, and the msulatng brie 1 () patterns 221 and 225 are the insulating spacers 220 having planarized upper surfaces.
The conductive One patterns 201 respectively contact the storage node contact plays and the insulating line patterns 221 and 225 insulate the conductive line patterns 201 In particular, the mstlatrng line patterns 225 formed on the etch stoppers 175 separate the conductive brie patterns 201 by one pitch, i.e., the size of trnit cells, in a direction parallel to the bit brie structures 165 while msulatng the conductive hne patterns 201 In the present embodiments, each of the storage node contact plugs 185 includes, t'or exarrlple, two conductive line patterns 201 and one insulating line pattern 221 therebetween.
Referrmg to FIG. 2C, m order to define the storage node electrodes, grooves 230 are f'onned by pattermng portions of the mold oxide layer patterns 191, the conductive brie patterns 201, and the insulating brie patterns 221 and 225. Here, the grooves 230 extend to be perpendicular to the extending direction of the mold oxide layer patterns 191, net, to be parallel to the word line structures 120. The grooves 230 are formed between the word line structures 120 on which the dram regions are t'ormed in order to secure maximum storage node electrode regions. In other words, a couple of word hnes 120 are arranged between a couple of adjacent grooves 230 such that the grooves 230 open the etch stoppers 175.
Referring to FIGS. 2D and 4, an insulating layer for supporters is deposited to sut'ficently bury the grooves 230, and the insulating layer is etched to a height smaller 3() than the height of the conductive line patterns 201 so as to form supporters 240. Here, the insulating layer for supporters is formed of an insulating layer having an etching selectivity do t'ferent from the etching selectvites of the mold oxide layer patterns 191 and the insulating brie patterns 221 and 225. Accordmgly, the instigating layer is wet etched to t'onn the supporters 240.
Since the supporters 240 are formed in the grooves 230, the supporters 240 cross through the conductive Ime patterns 201 so that the supporters 240 separate the conductive lme patterns 201 according to cell. Furthermore, the supporters 240 support the conductive line patterns 21)1, thereby reducing or preventing the S conductive One patterns 201 from tolling or bending toward the adjacent conductive lme patterns 201. In addition, the supporters 240 have a height smaller than the height of' the conductive brie patterns 201 m order to secure storage node electrode capacitance.
Thereafter, the mold oxide layer patterns 191 and the msulatmg linepatterns 221 and 225 are removed by a conventional wet etchmg method. Mere, smce the mold oxide layer patterns 191 and the insulating lme patterns 221 and 225 have the etching selectivity dft'erent from the etchmg selectvtres ofthe etch stoppers 175 and the supporters 240, the mold oxide layer patterns 191 and the insulating line patterns 221 and 225 are selectively removed Thus, the storage node electrodes 250 formed of the plurality o l'conductve line patterns 201 are completely formed.
The storage node electrodes 250 according to the present embodiment are formed of a plurality of conductive line patterns 201 having a fine hoe wrath so as to increase the surface area of the storage node electrodes 250. In addition, the supporters 240 separate and support the storage node electrodes 250 according to cell so as to reduce or prevent the storage node electrodes 250 from t'alling or bending toward the adjacent storage node electrodes 250. Furthermore, as shown in FIG. 2D, the storage node electrodes 250 are extended to the regions corresponding to the drain regions (not shown) as well as the regions having the bit line structures 165 so as to increase the surface area of the storage node electrodes 250.
Second Embodiments Ret'errmg to FIGS. GA and 7A, an isolation layer 110 is t'orrned on a semiconductor substrate 100 as shown in the first embodiment to define active regions 115. Word hne structures 120 are formed on the semiconductor substrate 100 as follows At'ter 2,! subseclucntly dcpostrng a gate msulatrng layer 121, word hrles 123, and a hard mask layer 125, the layers are patterned to be perpendicular to the longer axis of the active regions 115 Word line spacers 127 are formed on the sidewalls of the patterned hard mask layers 125 and word hoes 123 by a conventional method to form the word line strtctcjres 120. } lore, the hard mask layers 125 and the word line spacers 127 are tonged of silicon mtnde layers having an etching selectivity dt'ferent trom the eichmg selectivity of an mterlevel insulating layer of a silicon oxide layer group, which Will be formed to t'orrn selt:aLgning contact holes in a subsequent process In addition, the word brie structures 120 extend so as to be parallel with one another and a couple of word brie structures 120 are arranged on each active region 115. Source and drain regions (not shown), a first ntcrlevel Insulating layer 13(), contact pads 140a and 140b, a second mterlevel insulating layer 170, etch stoppers 175, and storage node contact pads 185 are formed in the active regions 115 at both sides of the 1() word line structures 120 by the method illustrated in the first embodiment.
A mold oxide layer is formed on the storage node contact plugs 185 and the etch stoppers 175 to a predetermined thickness. As described above, the mold oxide layer t'or detennmng the height of the storage node electrodes is formed to a height higher than the desired height of the storage node electrodes by a predetermined height. The portion of the mold oxide layer Its etched to expose the storage node contact plugs 185, thereby t'ormng mold oxide layer patterns 195. In the present embodiments, the mold oxide layer patterns 195 are arranged to be parallel to the word line structures 120 while overlapping the drain regions of the active regions 115.
In addition, the mold oxide layer patterns 195 can be formed in predetermined 2() intervals, for example, one-ptch or two-pitch. The mold oxide layer patterns 195 of FIG 6A are arranged in two-pitch intervals, and the mold oxide layer patterns 195 of FIG ') are arranged in one-pitch intervals. Here, the mold oxide layer patterns 195 in the two-ptch Intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patterns 195, and the mold oxide layer patterns 195 m the one-ptch intervals mean that one storage node contact plug 185 is located between two adjacent mold oxide layer patterns 195.
Rcterrmg to FIGS. bB and 7B, a conductive layer for the storage node electrodes, t'or example, a doped polysilicon layer, is deposited on the etch stoppers on which the mold oxide layer patterns 195 are formed as shown in the first embodiment. The polys,hcon layer is anisotropcally etched to t'on-n conductive spacers (not shown) of polyshcon on the both walls of the mold oxide layer patterns 195. An nsclatng layer is deposited on the resultant strct'rre and ansotropcally etched to forth msulatng spacers (not shown) on the sidewalls of the conductive spacers By repeatedly t'onnng the conductive spacers and the insulating spacers, the spaces between the mold oxide layer patterns 195 are filled. Here, the conductive spacers contact the storage node contact plugs 185 and the last spacers are the insrlatrrlg spacers. The last spacers are formed on the etch stoppers 175 between the storage node contact plLgs 185 and the last spacers may have relatively larger hne width than the other msulatrng spacers. In the present embodiments, each of the spaces between the mold oxide layer patterns 195 Is [died by forming the conductive spacers polar times and t'or-rmng the msulatmg spacers four times; however, the widths and the numbers of the conductive spacers and the Insulating spacers can be controlled.
I () The upper surfaces of the mold oxide layer patterns 195, the conductive spacers, and the rnsulatmg spacers are chemical mechanical polished to t'orrn conductive hne patterns 261 and insulating line patterns 271 and 275 between mold Exile layer patterns 1')6. Here, reference numeral 196 denotes the mold oxide layer patterns with plananzed upper surfaces. The conductive hne patterns 261, which are the conductive spacers having plananzed upper surfaces, contact the storage node contact plugs 185. The insulating hne patterns 271 on the storage node contact plugs 185, which are the insulating spacers 220 having planarized upper surfaces, insulate the condLctve line patterns 261 In addition, the insulating line patterns 275 formed on the etch stoppers 175 Insulate the conductive line patterns 261 and separate the conductive brie patterns 261 m a direction parallel to the word line structures 120 by one pitch, i.e., cell unit. In the present Invention, t'our conductive One patterns 261 contact each of the storage node contact plugs 185.
Referring to FIG. 6C, in order to define the storage node electrodes in each cell, grooves 235 are formed by pattcrnmg portions of the mold oxide layer patterns 196, the conductive line patterns 261, and the moating brie patterns 271 and 275.
I{ere, the grooves 235 are formed to overlap the bit line structures 165. Accordingly, grooves 235 and the Insulating spacers 275 separate the conductive line patterns 261 hi units of umt cell.
Referring to FIGS 6D and 8, an insLrIatmg layer for supporters Is deposited to sul'ficrently fill the grooves 235, and the insulating layer Is etched to a height smaller than the height of the conductive lme patterns 261 so as to form supporters 245. In some embodments, the msLrIating layer filled In the grooves 235 is formed of an msulatmg layer having an etchmg selectivity different from the etching selectrvites of the mold oxide layer patterns 196 and the rnsulatmg line patterns 271 and 275. Since the supporters 245 cross through the conductive One patterns 261, the supporters 245 separate the concirctve tine patterns 261 according to cell. Furthermore, the supporters 245 prevent the conductive One patterns 261 from tolling or beading toward the adjacent conductive line patterns 261. In addition, the supporters 245 are formed to a hegl1t smaller than the height of the conductive line patterns 261 in order to secure storage node electrode capacitance Thereat'ter, the mold oxide layer patterns 196 and the insulating lme patterns 271 and 275 are removed by a conventional wet etching method. Here, since the mold oxide layer patterns l 96 and tile msulatmg line patterns 271 and 275 have an 1 () etching selectivity different from the etching selectivitics of the etch stoppers 175 and the supporters 245, the mold oxide layer patterns 196 and the insulating line patterns 271 and 275 are selectively removed. Thus, storage node electrodes 280 are completed The effects of the second embodiments can be the same as those of the first l 5 embodiments.
Third Embodiments FIGS. l OA through 10C are sectional views of stages in the manufacture of a semiconductor memory device according to third embodiments of the present invention. The descriptions of the elements that are the same as the first and second embodiments will not be repeated, and the same reference numerals are allotted for the same elements ot'the first and second embodiments. In addition, the present embodiments Include a method for forrnng storage node electrodes where the processes performed up until f'orrmng mold oxide layer patterns are the same as the processes of the first embodiments, thus the description will begin with the srbseclcient processes Ret'errm to FIG IOA, a first conductive layer 310 for storage node electrodes Is formed on etch stoppers 175 on which mold oxide layer patterns 190 are formed.
I'hereafter, an insulating layer 320 Is deposited on the first conductive layer 310.
The t'irst conductive layer 310 and the Insulating layer 320 are anisotropically etched to term first conductive spacers 311 and insulating spacers 321 as shown m FlC 1013 A second conductive layer 330 for storage node electrodes is deposited on the resultant structure Here, the first conductive spacers 311 contact storage node contact plugs 18S Next, by ansotropcally etching the second conductive layer 330, second conductive spacers (not shown) are formed on the sidewalls of the insulating spacers 321 Here, the second conductive spacers contact the storage node contact plugs 185 while contacting the. sidewalls ol' the first conductive spacers 311. As shown in FIG 1OC, the srr-tace of' the resultant structure is chemical mechanical polished to form t'irst conductive line patterns 312 formed ofthe first conductive spacers 311 and second conductive line patterns 332 l'ormecl of the second conductive spacers Here, the first contlrctrve lme patterns 312 are termed mto an L-shape and portions ofthe second conductive One patterns 332 contact the lower portions of the first conductive 1() line patterns 312. 'l'hereal'ter, the insulating spacers 321 and the mold oxide layer patterns 1')0 are renoveci by a conventional wet etching method. Accordingly, storage Lode electrodes 300 formed of the first and second conductive line patterns 312 and 332 are i'on-ned.
Here, tle storage node electrodes 300 are t'on-ned of two conductive line patterns; however, the widths and the numbers of the conductive hne patterns can be vaned.
In addition, the mold oxide layer is formed to be parallel to the bit One structures he the present embodiments; however, the mold oxide layer can be Donned to be parallel to the word One strretrres as shown in the second embodiments Fourths Embodiment_ FIG. 12A and 12B are the sectional views cut along lmes C-C' of FIGS. I IA and I IB, respectively.
The descriptions ot' the elements that are the same as the first through third embodiments will not be repeated, and the same reference numerals are allotted for the same elements of the first through third embodiments. In addition, m the present enbodunents, the processes performed up until forming storage node contact plugs are tlie saline as the processes ofthe first through third embodiments, thus the clescriptron will begin with the subsequent processes.
Referring to FIGS. I IA and 12A, a mold oxide layer is formed on storage node contact plugs 185 and etch stoppers 175 to a predetermined thickness. IIere, the mold oxide layer for detennnmg the height of storage node electrodes can be formed to the desired height of the storage node electrodes Thereafter, portions ot'the mold oxide layer are dry etched to fond a plurality of mold oxide layer patterns 400. Here, the mold oxide layer patterns 400 are formed m, for example, one-pltch intervals.
while being formed In the shape of waves on a plan view In other words, ridge portions X of the mold oxide layer patterns 400 located between the storage node contact plugs 185 and valley portions X2 of the mold oxide layer patterns 400 are located on dram regions, which correspond to first contact pads 140a, or on an isolation layer 110 corresponding to the drain regions. When connecting tile ridge ports.Y of the wave-shaped mokl oxide layer patterns 400, straight lines are fonned In addition, m some embodiments, the straight lines are parallel to bit Ihnes structures 165 As shown m Fl(JS I IB and 12B, a conductive layer 410 for storage node electrodes, t'or example, a doped polyslicon layer, is deposited on etch stoppers 175 on which the wave-shaped mold ox de layer patterns 400 are formed, and a buffer insrlatm;, layer 420 is deposited on the conductive layer 410 for storage node electrodes Tlereat'ter, a chemical mechanical polishing Is performed to expose the mold oxide layer patterns 400. Accordingly, the conductive layer 410 for storage node electrodes remams m a region deemed by the mold oxide layer patterns 400 Here, the sidewalls of'the remaining conductive layer 410 for storage node electrodes have the same wave shape as the mold oxide layer patterns 400.
Next, as shown in FIGS 11 C and 13, grooves 430 are formed by dry etching 2() portions of the mold oxide layer patterns 400, the conductive layer 410 for storage node electrodes, and the Insulating layer 420 in order to separate the storage node electrodes by cell. Here, the grooves 430 are formed between word Ime structures 120, on which dram regions (not shown) are t'orrmed, while being perpendicular to the extending direction of the mold oxide layer patterns 400, net, the direction of bit line structures It is preferable that the grooves 430 pass through the valley portions X2 of the mold oxide layer patterns 400.
Thereafter, as shown in FIGS 11 D and 14, an insulating layer t'or supporters is deposited to sul'f'icrently fill the grooves 430 Here, the msulatmg layer for supporters can be t'ormed of the same material as the etch stoppers 175, for example, a silicon 3() Betide layer The msuiatilg layer is wet or dry etched to a predetermined thickness so that the isolating layer Is remained m the grooves 430 to a height smaller than the height of'the conductive layer 410 for storage node electrodes or the mold oxide layer patterns 400 Accordingly, supporters 440 are formed.
The mold oxide layer patterns 400 and the mstlatmg layer 420 are removed by a convcntonal wet etching method to long storage node electrodes 425 Here, smce the etch stoppers 175 are formed on the resultant structure on the semcondtctor substrate 100 and the etching selectivity of the supporters 440 is ditterent from the etching selectvtes of the mold oxide layer patterns 400 and the instlating layer 42O, only the snow oxide layer patterns 400 and the msulatmg layer 420 are selectively removed. Thtis, the storage node electrodes 425 are defined in tenets of each cell. In other words, the storage node electrodes 425 are separated in units of each cell by the stpporters 440 m a direction parallel to the word lines. In addition, the supporters 1 () 440 tombed In specific intervals support the storage node electrodes 425, which are Coroner Into wave-shaped line patterns. Therefore, the narrow and high storage node electrodes 425 are prevented from tailing toward the adjacent storage node electrodes Accordmg to the present embodiments, since the storage node electrodes 425 l S are formed In the wave shape, the surface area ot the storage node electrodes 425 increases In addition, since the storage node electrodes 425 are extended to the drain regions or the regions corresponding to the drain regions, the surface area of the storage node electrodes 425 ftrther increases.
hrthemore, since the supporters 440 are formed to separate the storage node electrodes 425 in tenets of each cell, the storage node electrodes 425 are reduced or prevented from falhng or bending toward the adjacent storage node electrodes 425 Here, the mold oxide layer patterns can be formed by changing the Intervals of the wave as shown m FIG l S. Referring to FIG. 15, mold oxide layer patterns 450 are formed m the shape of 7: waves m a plan view Here, nd,,e portions X3 and valley portions X are foamed to be located between storage node contact plugs 185. In this case, lines formed by connecting the ridge portions X3 and lines Formed by connecting the valley portions Y are parallel with one another by a predetermined distance, which Is wider than the width of the active regions.
It the wave shape of the mold oxide layer patterns 450 Is changed, the same effect Is attained.
In addition, as shown m FIG. 16, mold oxide layer patterns 500 may be formed In two-ptch intervals. In other words, the mold oxide layer patterns 500 are arranged m two-ptch intervals as shown m the first embodiment while being formed m the shape of waves on a plan view For example, m the mold oxide layer patterns 500, ridge portions X may be located between storage node contact plugs 185, and valley portions X, may he located on drain regions, i e, first contact regions, or on an Isolation layer l 10 corresponding to the drain regions. If the mold oxide layer patterns 500 in two-ptch intervals are formed, the same effect Is attained.
In adchton, storage node electrodes 425 can be formed by the method perfonned m talc the-d embodrments.
Flfth Embodiments I () FIGS. 17A and 17B are plan views of stages in the manufacture of a semiconductor memory device according to filth embodiments of the present mventorl. The processes pert'onned up until forming etch stoppers 175 are the same as the processes of tile first and second embodiments, thus the description will begin with the subsecluent processes.
Refenrulg to FIGS. 17A, mold oxide layer patterns 600 are foamed in the shape of waves m a plan view, on etch stoppers 175. Here, the mold oxide layer patterns 600 can be t'onned m, for example, one-pitch intervals. In other words, lines Conned by connecting ridge portions Xs or valley portions X of the mold oxide layer patterns 600 are substantially parallel to word line structures 120. In addition, the mold oxide layer patterns 600 are formed to expose each of the storage node contact plugs 185 between the adjacent mold oxide layer patterns 600 on the same lines. The mold oxide layer patterns 600 are Donned on regions without storage node contact plugs, i e., on drain regions and on an isolation layer 110 corresponding to the drain regions.
A plurality of conductive line patterns 610 and msulatmg line patterns 620 are alternately formed between the mold oxide layer patterns 600. Here, the plurahty of conductive line patterns 610 and insulating line patterns 620 are fonmed mto waves according to the wave-shaped mold oxide layer patterns 600. In this case, the conductive line patterns 610 and the insulating line patterns 620 are formed by the above-descnbed methods.
3() As shown in Fl(. 17B, portions ot'the mold oxide layer patterns 600, the concluctic brie patterns file, and the insulating lme patterns 620 are etched to foam grooves 630. The grooves 630 arc loomed on regions, which overlap bit line structures 165, in order to separate the conductive line patterns 610 in units of each cell. Here, the conductive line patterns 610 are defined in units of each cell by the groom es 630 and the mold oxide layer pattern 600, and the conductive line patterns 610 are Donned mto waves while contacting the storage node contact plugs 185.
Thereat'ter, supporters (not shown) are formed in the grooves 630 by the above-dcscrbed method. The mold oxide layer patterns 600 and the insulating line patten1s 620 are etched to form storage node electrodes 625.
If the mold oxide layer patterns 600 are formed to be parallel to the word line strictures It0, the same ef't'ect may be attained.
As shown m FI(J 1 8, the same effect may be attained by t'onming the mold oxide layer patterns 700 into waves n1 two-ptch intervals.
As described above, according to embodiments of the present mventon, storage node electrodes are formed in a plurality of line pattern types havmg a fine hne width Thins, the surface area of the storage node electrodes can increase. In addition, the supporters formed of an insulating layer are formed to be perpendicular to the extending direction of the hne patterns of the storage node electrodes.
Therefore, the supporters separate the storage node electrodes in units of each cell, and the supporters support the storage node electrodes, thereby reducing or preventing the storage node electrodes from falling or bending toward the adjacent storage node electrodes.
Furthennore, the regions for formmg the storage node electrodes may be increased so that the strf'ace area of the storage node electrodes may be increased.
While this nvento'1 has been particularly shown and described with reference to preferred embodiments thereof; it will be understood by those skilled in the art that var-ios changes in Corm and details may be made therein without departing from the spiral and scope of'thc mventon as defined by the appended claims.
In the drawings and specification, there have been disclosed typical preferred emboclments of the invention and, although specific terms are employed, they are Vised in a,,enenc and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the t'ollowing clauns.
Claims (1)
- CLAMS: I A semiconductor memory device comprising: a semiconductorsubstrate including a plurality of active regions, a plurality of word One structures passmg over the active regions, source and drain regions on the active re;,ons at rcspeclve sides of the word line structures, and a plurality of bit One structures crossing the word brie structures, electrically connecting to the dram regions, and passe;, between the active regions; an nterlevel insulating layer on the semiconductor substrate, etch stoppers on the nterlevel msulatmg layer; ] () storage node contact plugs n1 the mterlevel insulating layer and the etch stoppers; storage node electrodes, which comprise a plurality of conductive line patterns separated nil the same intervals while having a specific height, contacting the storage node contact plugs; and ] 5 supporters between the storage node electrodes and extending perpendicular to an extending direction of the brie patterns of the storage node electrodes; wherein, the plurality of Ime patterns comprise waves in a plan view.2. The semiconductor memory device of claim 1, wherein the conductive brie patterns are extended to be substantially parallel to the bit brie stnctrres; and the supporters are substantially parallel to the word One structures and pass over the drain regions between the word line structures and an isolation layer corresponding to the dram regions.3 The senicondcctor memory device of claim I or 2, wherein the condrictvc hne patterns are extended to be substantially parallel to the word line structures; and the supporters are substantially parallel to the bit line structures and overlap each of the bit Ime structures 4 The semiconductor memory device of claim 1, 2 or 3, wherem the supporters have a height smaller than the height of the brie patterns The semiconductor memory device of any of claims l to 4, wherein the supporters comprise msuiatng layers.6 A method Lor manctactiring a semiconductor memory device, the metho:l compr rsmg prepaying a semiconductor substrate including a plurality of active regions, a plurahty of word one structures passmg over the active regions, source and dram regions tom1ed on the active regions at respective sides of the word brie structures, and a plurality of bit One structures crossing the word line structures, electrically I () connecting to the drain regions, and passing between the active regions; Conning an mterlevel insulating layer on the semiconductor substrate; forming etch stoppers on the nterlevel insulating layer; forming storage node contact plugs m the rnterlevel insulating layer and the etch stoppers at specific intervals; forming a plurality of mold oxide layer patterns, which are fonmed in the shape of waves m a plan view, on the etch stoppers to expose the storage node contact pltigS; f l king spaces between the mold oxide layer patterns by alternately forming at least one conductive hne pattern and insulating hne pattern on the sidewalls of the mold oxide layer patterns m order to follow the shape of the mold oxide layer patterns; fonnmg grooves substantially perpendicular to the mold oxide layer patterns by etchmg portions of the mold oxide layer patterns, the conductive hne patterns, and the insulating line patterns, forming supporters in the grooves; and formm;, storage node electrodes by selectively removing the mold oxide layer patterns and the u1sulatmg In1e pattems; wherem the mold oxide layer patterns and the supporters separate the storage Diode electrodes m units ol each cell.7 The method for manufacturing a semiconductor memory device of claim 6, wherem the mokl oxide layer pattcnns are formed to expose each of the storage node plugs between the adjacent mold oxide layer patterns on the same lines.8. The method for manufacturing a semiconductor memory device of claim 6 or 7, wherem the mold oxide layer patterns are foamed to expose two storage node plugs between the adjacent mold oxide layer patterns on the same lines.9. The method for manufacturing a semiconductor memory device of claim 6, 7 or 8, wherein the mold oxide layer patterns are Donned along an extending direction ol' the bit brie structures.The method for manufacturing a semiconductor memory device of I () clause to, wherem r edge portions of the mold oxide layer patterns are located between the storage node contact plugs, and valley portions of the mold oxide layer patterns are located on the drain regions between the word hne structures or an isolation layer corresponding to the drain regions.11. The mctl1od for manufacturing a semiconductor memory device of claim I O. wherein Ones formed by connecting the ridge portions of the mold oxide layer patterns are straight Imes parallel to the bit One structures.12. The method for manufacturing a semiconductor memory device of claim I () or I 1, wherein r idge portions and valley portions of the mold oxide layer patterns are located between the storage node contact plugs, respectively.13 The method t'or manul'actunng a semiconductor memory device of claw 6, 7 or 8, wherein the mold oxide layer patterns are formed along an extending 2j direction of'tlle word One structures.14 The method for manufacturing a semiconductor memory device of clang 6, 7 or 8, wherein the mold oxide layer patterns are formed on the dram regions between the word line structures and an isolation layer region corresponding to the 3 () drain regal ons.The method for manufacturing a semiconductor memory device of claim 14, wherem Imes formed by connecting ridge portions of the mold oxide layer patterns are straight Ones parallel to the word line structures.16 The method for manufacturing a semiconductor memory device of any of claims 6 to 15, wherem the filling spaces between the mold oxide layer pasterns Sum, the conductive brie patterns and the insulating dine patterns comprises: depositing a conductive layer for storage node electrodes on the mterlevel msrlatmg layer; clepostmg an instlatmg layer on the conductive layer for storage node electrodes; and chemical mechamcal poLshmg the conductive layer for storage node I () electrodes and the msulatng layer.17 The method for rmantfactrring a semiconductor memory device of any of clanns 6 to 15, wheren1 the filling spaces between the mold oxide layer patterns rising the conductive brie patterns and the insulating One patterns comprises: longing conductive spacers on the sidewalls of the mold oxide layer patterns; forming msulatrlg spacers on the sidewalls of the conductive spacers; repeating the Donning of the conductive spacers and the forming of the msulatng spacers at least once; and chemical mechanical polishing the mold oxide layer, the conductive spacers, and the inslatmg spacers to focal the conductive line patterns and the msulatmg line patterns.18 The method tor manufacturing a semiconductor memory device of claim 57, wherem the condtictve spacers are fonned to contact the storage node ?5 contact plugs 19. The method for manufacturing a semiconductor memory device of clang 17 or 18, wherem the insulating spacers are finally Donned when repeatedly tomnng the conductive spacers and the insulating spacers.Tile method for manufacturing a semiconductor memory device of any of claims 6 to 15, wherein the Filing spaces between the mold oxide layer patterns usmg the conductive line patterns and the msulatmg brie patterns comprises: depositing a first conductive layer on the mterlevel insulating layer and the mold oxide layer patterns, t'onnmg an nsulatmg layer on the first conductive layer; formm;, first conductive spacers and msulatmg spacers by amsotropically S etching the nsulatmg layer and the first conductive layer; t'onmug second conductive spacers on the sidewalls of the insulating spacers; and chemical mechanical polishing the mold oxide layer patterns, the first conductive spacers, the msulatmg spacers, and the second conductive spacers. 1()21 The method For manuf'actunng a semiconductor memory device o f clam 6, wherein the t'orming of the supporters comprises: depositing an insulating layer that tills the grooves; and etclnng the Isolating layer so the insulating layer remains in the grooves.22 The method t'or manufacturing a semiconductor memory device of clarn1 21, the insulating layer is etched by a wet etching method.23. The method for manufacturing a semiconductor memory device of 2() claim 21 or 22, wherein the msulatmg layer is etched to have a height smaller than the height of the conductive Ime patterns.24. The method for manufacturing a semiconductor memory device of claim 21, 22 or 23, wherem the insulating layer cormposmg the supporters has an etching selectivity different from the etching selectvrtes of the mold oxide layer patterns and the insulating One patterns.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0036414A KR100434506B1 (en) | 2002-06-27 | 2002-06-27 | Semiconductor memory device and method for manufacturing the same |
| KR10-2002-0037059A KR100480602B1 (en) | 2002-06-28 | 2002-06-28 | Semiconductor memory device and method for manufacturing the same |
| GB0314707A GB2392311B (en) | 2002-06-27 | 2003-06-24 | Semiconductor memory devices and methods for manufacturing the same using sidewall spacers |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0500291D0 GB0500291D0 (en) | 2005-02-16 |
| GB2410373A true GB2410373A (en) | 2005-07-27 |
| GB2410373B GB2410373B (en) | 2006-03-22 |
Family
ID=34743278
Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0500290A Expired - Fee Related GB2410372B (en) | 2002-06-27 | 2003-06-24 | Semiconductor memory devices and methods for manufacturing the same using sidewall spacers |
| GB0500294A Expired - Fee Related GB2410375B (en) | 2002-06-27 | 2003-06-24 | Semiconductor memory devices and methods for manufacturing the same using sidewall spacers |
| GB0500293A Expired - Fee Related GB2410374B (en) | 2002-06-27 | 2003-06-24 | Methods for manufacturing semiconductor memory using sidewall spacers |
| GB0500295A Expired - Fee Related GB2410376B (en) | 2002-06-27 | 2003-06-24 | Semiconductor memory devices and methods for manufacturing the same using sidewall spacers |
| GB0500291A Expired - Fee Related GB2410373B (en) | 2002-06-27 | 2003-06-24 | Semi conductor memory devices and methods for manufacturing the same using sidewall spacers |
Family Applications Before (4)
| Application Number | Title | Priority Date | Filing Date |
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| GB0500290A Expired - Fee Related GB2410372B (en) | 2002-06-27 | 2003-06-24 | Semiconductor memory devices and methods for manufacturing the same using sidewall spacers |
| GB0500294A Expired - Fee Related GB2410375B (en) | 2002-06-27 | 2003-06-24 | Semiconductor memory devices and methods for manufacturing the same using sidewall spacers |
| GB0500293A Expired - Fee Related GB2410374B (en) | 2002-06-27 | 2003-06-24 | Methods for manufacturing semiconductor memory using sidewall spacers |
| GB0500295A Expired - Fee Related GB2410376B (en) | 2002-06-27 | 2003-06-24 | Semiconductor memory devices and methods for manufacturing the same using sidewall spacers |
Country Status (1)
| Country | Link |
|---|---|
| GB (5) | GB2410372B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6063656A (en) * | 1997-04-18 | 2000-05-16 | Micron Technology, Inc. | Cell capacitors, memory cells, memory arrays, and method of fabrication |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550076A (en) * | 1995-09-11 | 1996-08-27 | Vanguard International Semiconductor Corp. | Method of manufacture of coaxial capacitor for dram memory cell and cell manufactured thereby |
| US5856220A (en) * | 1996-02-08 | 1999-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a double wall tub shaped capacitor |
| US5721154A (en) * | 1996-06-18 | 1998-02-24 | Vanguard International Semiconductor | Method for fabricating a four fin capacitor structure |
| GB2321771A (en) * | 1996-08-16 | 1998-08-05 | United Microelectronics Corp | Stacked capacitor |
| US5854105A (en) * | 1997-11-05 | 1998-12-29 | Vanguard International Semiconductor Corporation | Method for making dynamic random access memory cells having double-crown stacked capacitors with center posts |
| US6025624A (en) * | 1998-06-19 | 2000-02-15 | Micron Technology, Inc. | Shared length cell for improved capacitance |
| US5913119A (en) * | 1998-06-26 | 1999-06-15 | Vanguard Int Semiconduct Corp | Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure |
-
2003
- 2003-06-24 GB GB0500290A patent/GB2410372B/en not_active Expired - Fee Related
- 2003-06-24 GB GB0500294A patent/GB2410375B/en not_active Expired - Fee Related
- 2003-06-24 GB GB0500293A patent/GB2410374B/en not_active Expired - Fee Related
- 2003-06-24 GB GB0500295A patent/GB2410376B/en not_active Expired - Fee Related
- 2003-06-24 GB GB0500291A patent/GB2410373B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6063656A (en) * | 1997-04-18 | 2000-05-16 | Micron Technology, Inc. | Cell capacitors, memory cells, memory arrays, and method of fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2410375A (en) | 2005-07-27 |
| GB2410376A (en) | 2005-07-27 |
| GB2410372A (en) | 2005-07-27 |
| GB2410374A (en) | 2005-07-27 |
| GB2410376B (en) | 2005-11-30 |
| GB0500291D0 (en) | 2005-02-16 |
| GB0500293D0 (en) | 2005-02-16 |
| GB0500290D0 (en) | 2005-02-16 |
| GB2410372B (en) | 2005-11-30 |
| GB0500294D0 (en) | 2005-02-16 |
| GB2410373B (en) | 2006-03-22 |
| GB2410374B (en) | 2005-11-30 |
| GB0500295D0 (en) | 2005-02-16 |
| GB2410375B (en) | 2005-11-30 |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20090624 |