GB2407434A

GB2407434A - Vcsel

Info

Publication number: GB2407434A
Application number: GB0324940A
Authority: GB
Inventors: Victoria Broadley; Jennifer Mary Barnes
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2003-10-24
Filing date: 2003-10-24
Publication date: 2005-04-27
Also published as: GB0324940D0

Abstract

A first wet chemical etch process using a sulphuric acid/hydrogen peroxide/ water solution is used to etch a GaAs capping layer 5 and an AlGaAs cladding layer 4, an AlGaInP active layer acts as an etch stopping layer to control the etch depth. A second wet chemical etch process using an ammonia/hydrogen peroxide/water solution is used to selectively etch the sidewall of the GaAs capping layer. The two-stage etching process allows the width of the capping layer to be controlled to be the same as or less than the underlying cladding layer, and where the vertical angle r 2 of the capping layer is less than the vertical angle r 1 of the cladding layer. VCSELs with continuous sidewalls between the cladding and capping layers can thereby be manufactured.

Description

A semiconductor layer structure and a method of manufacture thereof The

present invention relates to a method of fabricating a semiconductor layer structure.

The invention may be applied in the manufacture of, for example, a vertical cavity surface-emittng laser device (VCSF,I,).

Figure 1 Is a schematic cross-sectonal view of a conventional vertical cavity semiconductor laser device. The laser device 6 comprises a substrate l, a first cladding region 2, an active region 3 disposed over the first cladding region, and a second cladding region 4 disposed over the active region 3. A cap layer 5 is disposed over the second cladding region. In use, an electrical current is passed through the laser device 6 by means of electrical contacts (not shown) provided on the top face of the cap layer 5 and on the underside of the substrate 1, and photons are generated in the active region 3.

A VCSEL is a cylindrically symmetric structure, as shown in Figure 1, being cylindrically symmetric about an axis that is perpendicular to the layers 1-5 of the laser structure. In Figure 1, the axis of symmetry Is the z-axis.

Current will pass through the laser device generally along the z-axis shown In figure 1.

In order to provide lateral confinement (that is, confinement in the radial direction) of the current, and thus provide lateral confinement of the generated light, the second cladding region 4 and the cap layer 5 have, as shown in figure 1, a diameter d' that is smaller than the diameter d2 of the active region 3, the first cladding layer 2 and the substrate 1.

A laser device 6 having the structure shown in figure 1 is generally manufactured by initially growing all the semiconductor layers 1-5 with the same diameter. Portions of the second cladding region 4 and the cap layer 5 are then removed to produce the shape shown in figure 1. The portions of the second cladding region 4 and cap layer 5 are conventionally removed using an etching technique.

The second cladding region 4 and the cap layer 5 together constitute a mesa structure 7.

The diameter do of the second cladding region 4 and the cap layer 5 in the laser of figure 1 should, in order to provide good optical confinement, be made small. This has the disadvantage, however, that the area of a contact dsposcd on the upper surface ol the cap layer 5 is also small, and this can result m a laser that has a high electrical resistance and so has poor characteristics. The diameter d' of the second cladding layer 4 and the cap layer 5 is therefore a compromise between the desire to provide good optical conlincmcnt and the need to have a contact of sufficient area to provide a low electrical resistance.

In f pure 1, the side walls of the second cladding layer 4 and the cap layer 5 are shown as being vertical and continuous with one another. This is an idealised representation, and the etching process used to reduce the diameter of the cap layer 5 and the second cladding layer 4 is unlikely to leave the cap layer 5 and the second cladding layer 4 with vertical side walls. It Is more likely that the side walls 4', 5' of the second cladding region 4 and the cap layer 5 will be inclined with respect to the z-directon, as shown in figure 2.

It has been proposed to planarise the upper surface of the laser device 6 of figure 1, by depositing a thin layer (such as the layer 13 in Figure 8) of a material such as insulating silica over the mesa structure 7 so as to cover the side walls of the second cladding region 4 and cap layer 5, the top face of the cap layer, and the portions of the active region 3 that are not covered by the second cladding region 4. It can be difficult to do this in practice, however, and reasons for this are described in relation to figure 2.

The cap layer 5 and the second cladding region 4 of the laser 6 will in general be made of different semiconductor materials. It is likely that one of these materials will be more susceptible to the etchant used in the etching process than the other material. Where the second cladding region is more susceptible to the etchant than the cap layer 5, the etching process may well lead to the etched second cladding region 4 undercutting the cap layer 5, as shown in figure 2. The side wall 4' of the second cladding region 4 is not continuous with the side wall 5' of the cap layer, and this leads to difficulties in depostmg a planansaton layer over the mesa 7 - the discontinuity in the side wall profile of the mesa 7 can lead to nten-uptons In the deposited silica layer.

A method of manufacturing a semconduclor laser device having a stripe ridge structure Is disclosed in US-A-6 1()3 542. A stripe ridge laser has a cross-section that Is generally similar to the cross-section of the VCSEL of figure 1, although the laser extends In a stripe form and Is not cyhndncally symmetric. In this document, a mask Is deposited over the cap layer, and the cap layer and second cladding region are then etched using a suitable etchant. This etching process is stopped while the width of the second cladding region is greater than the desired width. A second etching step is then used to further reduce the width of the second cladding region, and to make the side walls of the second cladding region more nearly vertical.

Side walls that are close to the vertical can be obtained relatively easily using a dry etching technique such as reactive Ion etching. However, dry etching techniques are relatively expensive. The method of US-A-6 103 542 Is intended to enable near-vertcal side walls to be obtained using a wet etching process. However, it can be difficult to deposit a thm planansation layer over layers having vertical or nearvertcal side walls.

The method of US-A-6 103 542 leads to a structure of the general type shown in figure 2, m which the second cladding region 4 undercuts the cap layer 5. This undercutting Is a further reason why it is difficult to deposit a planarisation layer over the mesa structure obtained by the method of US- A-6 103 542.

A first aspect of the present invention provides a method of fabricating a semiconductor layer structure comprising a first semiconductor region and a second semiconductor region disposed over the first semiconductor region, the method comprising; a first etching step of etching the layer structure using a first etchant thereby to etch the first semiconductor region to a desired side wall profile; and a second etching step of etching the structure using a second etchant different from the first etchant thereby to etch the second semiconductor region to a desired side wall profile while not substantially alfectng the side wall profile of the first semiconductor region; wherein the second : it etching step produces a second semiconductor region that has a side wall profile that is substantially continuous with the side wall profile of the first semiconductor region or that has, at the interface between the lost semiconductor region and the second semiconductor region, a width smaller than the width of the first semiconductor region.

Where the first etching step produces a structure similar to that shown m figure 2, the second etching step may be used to reduce the width of the cap layer (which corresponds to the second semiconductor region) to produce a side wall profile for the cap layer that is substantially continuous with the side wall profile of the second eladdmg region (which corresponds to the first semiconductor region). This makes it easier to deposit a thin planarsaton layer over a mesa structure that includes the cap layer and the second cladding region.

The invention may alternatively be effected by etehmg the second semiconductor region so that it has a width that Is smaller than the width of the first semiconductor region (with both widths being measured at the interface between the first semiconductor region and the second semiconductor region). For example, where the first etching step produces a structure similar to that shown in figure 2, the second etching step may be used to reduce the width of the cap layer to produce a cap layer that, at the interface between the cap layer and the second cladding region, has a smaller width than the second cladding region. This agam makes it easier to deposit a thin planarisation layer over a mesa structure that includes the cap layer and the second cladding region.

The method of the invention may be used to ensure that amount of overhang of the second semiconductor region is sufficiently small to allow a planarisation layer to be deposited without containing interruptions or diseontinuities. In order to deposit a planarisation layer that does not contain any interruptions or discontinuities over a mesa structure in which the second semiconductor region overhangs the first semiconductor region, the second semiconductor region must overhang the first semiconductor region by preferably no more than approximately 15-20% of the thickness of the planarisation layer. As an example, if the overhang of the cap layer after the first etching step were 35nm, a planarsaton layer deposited over the mesa would need a minimum thickness of 130-170nm (depending on the angle of slope of the sidewall of the mesa) in order to s be reasonably certain of depositing a planarisaton layer that did not contain interruptions or dscontinutes. A planarisation layer typically has a thickness of approximately 200nm.

Although it might appear that simply increasing the thickness of the planansaton layer would allows mesa structure having greater overhang to be planarised, In practice it Is not possible to increase the thickness of the planarsaton layer sgnicantly. The thickness of the planarisation layer is preferably less than the thickness of the metal contact deposited over the planarisation layer to ensure that the metal contact makes good electrical contact to the upper surface of the cap layer inside the window defined in the planarisation layer, and a metal contact layer typically has a thickness of approximately 250nm. Thus, a planarisation layer will generally have a thickness of approximately 200nm, and it is difficult to use a planarsation layer having a thickness of more than approximately 400nm.

The second etching step may produce a side wall profile for the second semiconductor region that is inclined relative to an axis normal to the semiconductor layer structure.

This facilitates subsequent deposition of a planarisaton layer, since a planarsation layer may be deposited more reliably over an inclined surface than over a vertical surface.

The second etching step may produce a side wall profile for the second semiconductor region that makes a lower angle with an axis normal to the semiconductor layer structure than does the side wall profile of the first semiconductor region.

The second etching step may produce a side wall profile for the second semiconductor region that makes an angle of less than 10 with an axis normal to the semiconductor layer structure.

The first etching step may produce a side wall profile for the first semiconductor region that Is inclined WIttl respect to an axis normal to the semiconductor layer structure. rl his again fachtates subsequent deposition of a planarsation layer.

The first etching step may produce a side wall profile for the first semiconductor region that makes an angle of less than 57 with an axis normal to the semiconductor layer structure.

The first etching step may produce a side wall profile for the first semiconductor region that makes an angle of more than 29 with an axis normal to the semiconductor layer structure.

The first semiconductor region may comprise a stack of semiconductor layers.

The first semiconductor region may comprises a stack of AlGaAs layers. The first etchant may be H2SO4: H2O2: H2O.

The second semiconductor region may be a GaAs layer. The second etchant may be NH4OH: H2O2: H2O.

A second aspect of the present Invention provides a semiconductor layer structure manufactured by a method of the first aspect.

A third aspect of the present Invention provides a semiconductor layer structure comprising: a first semiconductor region and a second semiconductor region disposed over the first semeonduetor region; wherein a side wall of the semiconductor layer structure is inelmed with respect to a normal axis of the layer structure and is substantially continuous over the first semiconductor region and the second semiconductor region.

The angle of mchnat''on, to the normal axis, ol the side wall of the second semiconductor region may he Ic.ss than the angle of mchnaton, to the normal axis, ol the side wall of the first scmconclctor region.

The angle of inclination, to the normal axis, of the side wall of the second semiconductor region may he less than 1() .

The angle of mclinaton, to the normal axis, of the side wall of the first semiconductor region may be less than less than 57 .

The angle of mcl'naton, to the normal axis, of the side wall of the first semiconductor region may be more than 29 .

The first semiconductor region may comprise a stack of semiconductor layers.

The first semiconductor region may comprise a stack of AlGaAs layers.

The second semiconductor region may be a GaAs layer.

A fourth aspect of the present invention provides a semiconductor laser device comprising a semiconductor layer structure as defined in the third aspect. The first semiconductor region may be a cladding region. The second semiconductor region may be a cap layer.

Preferred embodiments of the present invention will now be described by way of illustrative example with reference to the accompanying figures in which: Figure I is a schematic perspective view of a vertical cavity surface-emitting laser device; Figure 2 Is a schematic cross-sectonal view Illustrating results of a conventional fabrication process for the laser device of figure 1; Figures 3 to 7 Illustrate manufacture of a semiconductor laser according to a method of the present invention; Figure 8 is a schematic cross-sectonal view of a semiconductor laser manufactured by method ol the present invention; and figure 9 Illustrates manufacture of a semiconductor laser according to another method of the present invention.

Like references denote like-components throughout the drawings.

The Invention will be described with reference to the manufacture of a vertical cavity surfaee-emttng laser device. The Invention is not, however, limited to use in the manufacture of such a device.

Figures 3 to 7 illustrate the manufacture of a VCSEL using a method according to the present invention. Imtally, the basic laser structure 12 is grown by any suitable semiconductor growth technique such as, for example, molecular beam epitaxy (MBE).

The basic laser structure 12 is shown in Figure 3. In this embodiment, the laser structure 12 has, as its lowest layer, a substrate 1. In this embodiment this Is a semi- insulating e-doped GaAs substrate.

A first eladdmg region 2 is grown over the substrate. In this embodiment the first cladding region 2 is an e-type cladding region formed by an etype AlGaAs region that consists of layers 8 of low aluminium mole fraction alternating with layers 9 of high aluminum mole fraction. For example, the layers 8 may be layers of e-type Ale 5Ga'5As, and the layers of high aluminium content may be layers of e-type Ale 'sGao 05AS An active region is grown over the first cladding region 2. In this embodiment the active region is a GaAllnP active region which is not intentionally d sped.

A second cladding region 4 is grown over the active region 3. The second cladding region 4 has opposite conductivity type to the first cladding region - and, in this emboclmlent, the second cladding region 4 is a ptype chddmg region since the first cladding region 2 is an e-type cladding region. The p-type cladding region 4 again consists ol layers X of low aluminum content alternating with layers 9 of high aluminum content. The layers 8 of low aluminum content may be layers of p-type Al05Ga5As, and the layers 9 of high alumnium content may he layers of p- type Ale ssGao 05As.

Finally, a cap layer 5 is grown over the second cladding region 4. In this embodiment the cap layer 5 is a highly p-doped GaAs layer.

Once the laser structure 12 has been grown, it Is etched to give the profile generally similar to that shown in Figure 1. In order to carry out the etching, a mask 20 is deposited over part of the upper surface of the laser structure 12 as shown m figure 4.

The mask 20 may be, for example, a mask of photo-resst, and may be deposited and patterned to the desired size using any suitable technique.

The layer structure 12 is then etched using a first etchant that etches the cap layer 5 and the second cladding layer 4. Figure 5 shows the results of the first etching step.

The first etchant removes the portions of the cap layer 5 and the second cladding region 4 that are not covered by the mask 20. Furthermore, the etchant also undercuts the mask 20. If the etchant etches the second cladding region more readily than it etches the cap layer 5, preferential etching of the AlGaAs second cladding region 4 results in the formation of an side wall 4' of the second cladding region 4 that Is inclined and that undercuts the cap layer 5. The side wall 4' ol the second cladding region Is inclined with respect to the symmetry axis of the structure (m figure 5, the symmetry axis of the structure 12 is along the z-axs). The angle between the symmetry axis and the side wall 4' of the second cladding region 4 is denoted by (it.

The depth ot'ctch in the z-dh-ccto,.1 can he controlled by providing a layer that Is highly resistant to the l''rst etchant In the layer structure. L)cpcndng on the material system in which the laser Is being fabrcat.ed, and on the first etchant used, the active region 3 Itself' may act as such an "etch stop layer". Alternatively, a specific etch stop layer can be provided in the layer structure 12, for example within the second cladding region 4.

In the specific example given, a suitable t'irst etchant is a solution of sulphuric acid and hydrogen peroxide in water (I'I2SO4: H2O2: LEO). In this example, the AlGalnP active region 3 will act as an etch stop layer for the first etchant, and it is not necessary to provide a specific etch stop layer In the laser structure.

The structure obtained by the first etching step Is shown m figure 5, and corresponds generally to the structure of figure 2.

According to the present Invention, a second etching step Is linen carried out. This step uses a second etchant that etches the cap layer 5 In preference to the second cladding region 4. The second etchant preferentially etches the cap layer 5, underneath the mask 20, to remove the portions of the cap layer 5 that overhang the second cladding layer 4.

Figure 6 shows the results of the second etching step. As can be seen, the resultant mesa 7 has a continuous side wall profile - the side wa]] 5' of the cap layer 5 is continuous with the side wall 4' of the second cladding region 4. The continuous side wall profile Is obtained by suitably controlling the duration of the second etching step so as to remove the portions of the cap layer 5 that overhang the second cladding region 4, and stopping the second etching step when the diameter of the cap layer 5 has been reduced lo be substant ally equal to the diameter of the second cladding region 4. The active region 3 acts as an etch stop layer In the z-drecton for the second etching step.

Next, the mask 20 is removed to produce the structure 12 shown In figure 7.

Since the side wall S' of the cap layer S obtained in the second etching step Is continuous with the side wall 4' of the second cladding region 4, it is straightforward to deposit a thin planansation layer, for example a silica layer over the mesa structure 7 to cover part of the upper surface of the cap layer 5 (part ol the upper surface of the cap layer S Is left uncovered by the planarisation layer to allow emission of light), the side walls of the cap layer and the second cladding region, and the exposed upper surface of the active region 3. This layer Is shown In figure 8 as the layer 13. A metallic contact 14 may then be deposited over the planarisation layer 13 (again leaving part of the upper surface of the cap layer S uncovered to allow emission of hght). The metallic contact 14 may extend over the side lace of the cap layer 5, so that the area of the contact 14 can be much larger than the area of the mesa structure 7. This enables a large area, low- resstance contact to be used, while still making the mesa structure narrow in order to provide good lateral confinement of injected current.

The method of the present Invention will generally produce a side wall 5' for the cap layer 5 that is steeper (that is, more nearly vertical) than the side wall 4' of the second cladding region 4 - the angle 02 between the side wall 5' of the cap layer and the normal axis of the laser structure (the z-axs in figure 7) Is less than the angle 8r between the side wall 4' of the second cladding region 4 and the normal axis. This is because the angle of slope 02 of the sidewall of the cap layer 5 is determined by the duration of the second etching step whereas the angle of slope 0 of the sidewall of the second cladding layer 4 is determined by the duration of the first etching step, and the second etching step will generally be shorter than the duration of the first etching step.

In a preferred embodiment, the angle 0 is preferably greater than 29 and is preferably less than 57 . The angle 02 preferably satisfies -10 < H2 < 10 (an angle of -10 indicates that the cap layer Is wider at its top surface than at its Interface with the second cladding region). Depending on the thickness and composition of the cap layer 5, the second etching step may produce a cap layer having a side wall 5' that is substantially vertical.

For the specific material system described In the above example, a suitable etchant for the second etching step Is a mixture of' ammonia and hydrogen peroxide In water (NH4OH: [12O2: H2O). This etchant prel'erentully etches the GaAs cap layer 5 without significantly etching the AlClaAs second cladding region 4.

The Invention has been described with reference to the manufacture of a VCSET, structure. The invention Is not lrnted to this, however, and may be applied to the manufacture of other structures. As an example, the Invention may also be applied to the manut'acture of resonant cavity hghtemttng diodes, smce these require a similar mesa profile to that shown In t'gure 7.

In the present invention, the diameter of the mesa structure 7 at the interface between the second cladding region and the cap layer Is determined m the first etching step. The diameter of the mesa structure at the interface with the active region is determined by the diameter of the mask 20. The second etching step acts to alter the side wall profile of the cap layer 5, but does not sgnf'icantly affect the diameter of the second cladding region 4.

The use of two etching steps makes it possible to obtain a profile such as that shown in figure 7, in which the angle of inclination of the side wall 10 of the second cladding region is not the same as the angle of nelnation of the side wall 11 of the cap layer 5.

The method of the present invention may be carried out using "wet etching" steps only.

The invention does not require the use of dry etching steps, and this is advantageous since dry etching steps are more expensive to carry out than wet etching steps. A further advantage of using wet etching techniques Is that dry etching techniques tend to be Isotropic and provide near-verteal side wall profiles. Near-vertieal side wall profiles are disadvantageous in the fabrication of a VCSEL, since they would prevent reliable deposition of the planarisation layer 13. Tn contrast, the method of the present Invention can provide a mesa structure in which the second cladding layer and the cap layer have side walls that are continuous or substantially continuous with one another, but in which the side wall of the cap layer and the side wall of the second cladding layer are not vertical - so that a thin planarsaton layer can reliably be deposited over the mesa structure.

Figure 9 illustrates manufacture ol a laser- device according to another method of the invention. Figure 9 corresponds generally to Figure 7, and shows the laser structure after the thrst and second etching steps have been carried out and after removal ol the mask. In this method, the second etching step is carried out for long enough to ensure that the cap layer 5 has been etched so that its diameter, at the interface between the cap layer 5 and the second cladding region 4, is less than the diameter of the second cladding region 4. A planarisation layer without interruptions or diseontinuities can readily be deposited over the mesa structure 7. In this embodiment, care must be taken that the final diameter of the cap layer Is large enough to allow a window region of the desired size - as a rule, the diameter of cap layer 5 must be at least 20nm greater than the desired diameter ol the window region of the laser.

Claims

CLAIMS: 1. A method of etching a semiconductor layer structure composing a

first semiconductor region and a second semiconductor region disposed over the first semiconductor region, the method comprising: a first etching step ol etching the structure using a first etch.ant thereby to etch the lost semiconductor region to a desired side wall profile; and a second etching step o, etching the structure using a second etchant different from the first etchant thereby to etch the second semiconductor region to a desired side wall profile while not substantially affecting the side wall profile of the first semiconductorregion; wherem the second etching step produces a second semiconductor region that has a side wall profile that is substantially continuous with the side wall profile of the first semiconductor region or that has, at the interface between the first semiconductor region and the second semiconductor region, a width smaller than the width of the first sernconductor region.
2. A method as claimed In claim l wherem the second etching step produces a side wall profile for the second semiconductor region that is inclined relative to an axis normal to the semiconductor layer structure.
3. A method as claimed In claim 1 or 2wherein the second etching step produces a side wall profile for the second semiconductor region that makes a lower angle with an axis normal to the semiconductor layer structure than does the side wall profile of the first semiconductor region.
4. A method as claimed in claim 2 or 3 wherein the second etching step produces a side wall profile for the second semiconductor region that makes an angle of less than 10 with an axis normal to the semiconductor layer structure.
5. A method as claimed In any preceding claim wherein the first etching step produces a side wall profile for the first semiconductor region that is mchned with respect to an axis normal to the semiconductor layer structure. l S
6. A method as claimed In claim 5 wherein the first ctchrng step produces a side wall profile Or the Idlest semiconductor region that makes an angle of less than 57 with an axis normal to the semiconductor layer structure.
7. A method as claimed in claim 5 or 6 wherein the first etching step produces a side wall profile for the fast semrco,nductor- region that makes an angle of more than 29 with an axis norin,ll to the semiconductor layer structure.
8. A method as claimed in any preceding claim wherein the first semiconductor region comprises a stack of semiconductor layers.
9. A method as claimed in claim 8 wherein the first semiconductor region comprises a stack of AlGaAs layers.
10. A method as claimed in any preceding claim wherein the first etchant is H2SO4: H202: H2O.
11. A method as claimed In any preceding claim wherein the second semiconductor regc,n Is a GaAs layer.
12. A method as claimed m any preceding claim wherein the second etchant is NH4OH: H2O2: H2O.
13. A method of etching a semiconductor layer structure substantially as described herein with reference to Figures 2, 3 and 4 of the accompanying drawings.
14. A semiconductor layer structure manufactured by a method defined in any of claims 1 to 13.
15. A scrnrconductor layer structure composing: a first semiconductor region; and a second semiconductor region disposed over the first semiconductor region; wherein a side wall of the semiconductor layer structure Is inclined with respect to a nor-real axis of the layer structure and Is substantially continuous over the fir-et semiconductor region and the second semiconductor region.
16. A semiconductor layer structure as claimed m clams 15 wherein the angle of nchnatorl, to the normal axis, of the side wall ot the second serilconductor region Is less than the angle of Inclination, to the normal axis, ot the side wall of the first semiconductor region.
17. A semiconductor layer structure as claimed m claim 15 or 16 wherein the angle of inchnaton, to the normal axis, of the side wall ot the second semiconductor region Is less than 10 .
18. A semiconductor layer structure as claimed m claim 15, 16 or 17 wherein the angle of inclination, to the normal axis, of the side wall of the first semiconductor region Is less than less than 57 .
19. A semiconductor layer structure as claimed m claim 15, 16, 17 or 18 wherein the angle of Inclination, to the normal axis, of the side wall of the first semieonduetor region is more than 29 .
20. A semieonduetor layer structure as claimed in any of claims 15 to 19 wherein the first semieonduetor region comprises a stack of semieonduetor layers.
21. A semieonduetor layer structure as Maimed in claim 20 wherein the first semieonduetor region comprises a stack of AlGaAs layers.
22. A semieonduetor layer structure as claimed in any of claims 15 to 21 wherein the second semiconductor region is a GaAs layer.
23. A semiconductor laser device comprising a semiconductor layer structure as defined in any of claims 15 to 22. 1 17
24. A semiconductor laser device as claimed in claim 23 wherein the first semiconductor region Is a cladding region.
25. A semiconductor laser device as clamcd In claim 23 or 24 wherein the second semiconductor region Is a cap layer.