GB2402275B - Delay locked loop for use in semiconductor memory device - Google Patents

Delay locked loop for use in semiconductor memory device

Info

Publication number
GB2402275B
GB2402275B GB0418670A GB0418670A GB2402275B GB 2402275 B GB2402275 B GB 2402275B GB 0418670 A GB0418670 A GB 0418670A GB 0418670 A GB0418670 A GB 0418670A GB 2402275 B GB2402275 B GB 2402275B
Authority
GB
United Kingdom
Prior art keywords
memory device
semiconductor memory
locked loop
delay locked
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0418670A
Other versions
GB0418670D0 (en
GB2402275A (en
Inventor
Seong-Hoon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR10-2000-0036762A external-priority patent/KR100527397B1/en
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of GB0418670D0 publication Critical patent/GB0418670D0/en
Publication of GB2402275A publication Critical patent/GB2402275A/en
Application granted granted Critical
Publication of GB2402275B publication Critical patent/GB2402275B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
GB0418670A 2000-06-30 2001-06-29 Delay locked loop for use in semiconductor memory device Expired - Fee Related GB2402275B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2000-0036762A KR100527397B1 (en) 2000-06-30 2000-06-30 Delay Locked Loop having small jitter in semiconductor memory device
GB0116028A GB2367435B (en) 2000-06-30 2001-06-29 Delay locked loop for use in semiconductor memory device

Publications (3)

Publication Number Publication Date
GB0418670D0 GB0418670D0 (en) 2004-09-22
GB2402275A GB2402275A (en) 2004-12-01
GB2402275B true GB2402275B (en) 2005-02-23

Family

ID=33436266

Family Applications (2)

Application Number Title Priority Date Filing Date
GB0418670A Expired - Fee Related GB2402275B (en) 2000-06-30 2001-06-29 Delay locked loop for use in semiconductor memory device
GB0418667A Expired - Fee Related GB2402274B (en) 2000-06-30 2001-06-29 Delay locked loop for use in semiconductor memory device

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB0418667A Expired - Fee Related GB2402274B (en) 2000-06-30 2001-06-29 Delay locked loop for use in semiconductor memory device

Country Status (1)

Country Link
GB (2) GB2402275B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0704975A1 (en) * 1994-09-29 1996-04-03 Nec Corporation Digital phase locked loop having coarse and fine stepsize variable delay lines
US5969553A (en) * 1997-06-20 1999-10-19 Mitsubishi Denki Kabushiki Kaisha Digital delay circuit and digital PLL circuit with first and second delay units
US6049239A (en) * 1996-12-27 2000-04-11 Fujitsu Limited Variable delay circuit and semiconductor integrated circuit device
US20010005337A1 (en) * 1999-12-24 2001-06-28 Hea-Suk Jung Delay locked loop having fast locking time

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100197563B1 (en) * 1995-12-27 1999-06-15 윤종용 Digital delay synchronous loop circuit using synchronous delay line
US6008680A (en) * 1997-08-27 1999-12-28 Lsi Logic Corporation Continuously adjustable delay-locked loop

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0704975A1 (en) * 1994-09-29 1996-04-03 Nec Corporation Digital phase locked loop having coarse and fine stepsize variable delay lines
US6049239A (en) * 1996-12-27 2000-04-11 Fujitsu Limited Variable delay circuit and semiconductor integrated circuit device
US5969553A (en) * 1997-06-20 1999-10-19 Mitsubishi Denki Kabushiki Kaisha Digital delay circuit and digital PLL circuit with first and second delay units
US20010005337A1 (en) * 1999-12-24 2001-06-28 Hea-Suk Jung Delay locked loop having fast locking time

Also Published As

Publication number Publication date
GB0418670D0 (en) 2004-09-22
GB2402274A (en) 2004-12-01
GB2402275A (en) 2004-12-01
GB2402274B (en) 2005-02-23
GB0418667D0 (en) 2004-09-22

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20180629