GB2401227B - Cache line flush micro-architectural implementation method and system - Google Patents

Cache line flush micro-architectural implementation method and system

Info

Publication number
GB2401227B
GB2401227B GB0415931A GB0415931A GB2401227B GB 2401227 B GB2401227 B GB 2401227B GB 0415931 A GB0415931 A GB 0415931A GB 0415931 A GB0415931 A GB 0415931A GB 2401227 B GB2401227 B GB 2401227B
Authority
GB
United Kingdom
Prior art keywords
implementation method
cache line
line flush
architectural implementation
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0415931A
Other versions
GB0415931D0 (en
GB2401227A (en
Inventor
Salvador Palanca
Stephen A Fischer
Subramaniam Maiyuran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/475,759 external-priority patent/US6546462B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0415931D0 publication Critical patent/GB0415931D0/en
Publication of GB2401227A publication Critical patent/GB2401227A/en
Application granted granted Critical
Publication of GB2401227B publication Critical patent/GB2401227B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0415931A 1999-12-30 2000-12-28 Cache line flush micro-architectural implementation method and system Expired - Fee Related GB2401227B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/475,759 US6546462B1 (en) 1999-12-30 1999-12-30 CLFLUSH micro-architectural implementation method and system
GB0217123A GB2374962B (en) 1999-12-30 2000-12-28 A cache line flush instruction and method, apparatus, and system for implementing the same
PCT/US2000/035481 WO2001050274A1 (en) 1999-12-30 2000-12-28 Cache line flush micro-architectural implementation method and system

Publications (3)

Publication Number Publication Date
GB0415931D0 GB0415931D0 (en) 2004-08-18
GB2401227A GB2401227A (en) 2004-11-03
GB2401227B true GB2401227B (en) 2005-03-16

Family

ID=34219610

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0415931A Expired - Fee Related GB2401227B (en) 1999-12-30 2000-12-28 Cache line flush micro-architectural implementation method and system

Country Status (1)

Country Link
GB (1) GB2401227B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0210384A1 (en) * 1985-06-28 1987-02-04 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
GB2178205A (en) * 1985-06-27 1987-02-04 Encore Computer Corp Hierarchical cache memory system and method
GB2200481A (en) * 1987-01-22 1988-08-03 Nat Semiconductor Corp Maintaining coherence between a microprocessor's integrated cache and external memory
US4924379A (en) * 1986-10-03 1990-05-08 Bbc Brown Boveri Ag Multiprocessor system with several processors equipped with cache memories and with a common memory
EP0750262A2 (en) * 1995-06-19 1996-12-27 Kabushiki Kaisha Toshiba Apparatus for flushing the contents of a cache memory
WO1999035578A1 (en) * 1998-01-08 1999-07-15 International Business Machines Corporation Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2178205A (en) * 1985-06-27 1987-02-04 Encore Computer Corp Hierarchical cache memory system and method
EP0210384A1 (en) * 1985-06-28 1987-02-04 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
US4924379A (en) * 1986-10-03 1990-05-08 Bbc Brown Boveri Ag Multiprocessor system with several processors equipped with cache memories and with a common memory
GB2200481A (en) * 1987-01-22 1988-08-03 Nat Semiconductor Corp Maintaining coherence between a microprocessor's integrated cache and external memory
EP0750262A2 (en) * 1995-06-19 1996-12-27 Kabushiki Kaisha Toshiba Apparatus for flushing the contents of a cache memory
WO1999035578A1 (en) * 1998-01-08 1999-07-15 International Business Machines Corporation Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency

Also Published As

Publication number Publication date
GB0415931D0 (en) 2004-08-18
GB2401227A (en) 2004-11-03

Similar Documents

Publication Publication Date Title
GB0217123D0 (en) Cache line flush micro-architectural implementation method and system
HK1045777A1 (en) System and method for miniguide implementation
EP1287449A4 (en) Application caching system and method
GB0208759D0 (en) Transaction system and method therefor
GB9906037D0 (en) Tagging system and method
GB9911956D0 (en) Electrosurgery system and method
GB0028079D0 (en) System and method
GB9918348D0 (en) Location finding system and method
GB0022444D0 (en) Positioning system and method
SG112894A1 (en) System and method for dimensioning objects
GB0024354D0 (en) Wellbore antennae system and method
GB2352851B (en) Search system and method based on search condition combinations
IL135821A0 (en) Manufacturing system and method
AU2578301A (en) Mounting system and method
DE60016291D1 (en) Connection system and method
SG108816A1 (en) Electronic settling system and electronic settling method
AU7379900A (en) Units system and method
IL150263A0 (en) System and method for multiprocessor management
GB2352523B (en) Fluid-gauging systems and methods
HK1044395A1 (en) Component management system and method
IL130791A0 (en) Irrigation method and system
GB9906386D0 (en) Bit encoding system and method
SG92765A1 (en) Dubbing system and dubbing method
AU2001275087A1 (en) Deicing system and related method
GB0023952D0 (en) Project management system and method

Legal Events

Date Code Title Description
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1066991

Country of ref document: HK

REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1066991

Country of ref document: HK

S28 Restoration of ceased patents (sect. 28/pat. act 1977)

Free format text: APPLICATION FILED

S28 Restoration of ceased patents (sect. 28/pat. act 1977)

Free format text: RESTORATION ALLOWED

Effective date: 20100122

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20191228