GB2387268A - Silicon stamped circuits - Google Patents

Silicon stamped circuits Download PDF

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Publication number
GB2387268A
GB2387268A GB0201569A GB0201569A GB2387268A GB 2387268 A GB2387268 A GB 2387268A GB 0201569 A GB0201569 A GB 0201569A GB 0201569 A GB0201569 A GB 0201569A GB 2387268 A GB2387268 A GB 2387268A
Authority
GB
United Kingdom
Prior art keywords
silicon
wafer
stamp
layer
ink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0201569A
Other versions
GB0201569D0 (en
Inventor
Darren Edward Robertson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to GB0201569A priority Critical patent/GB2387268A/en
Publication of GB0201569D0 publication Critical patent/GB0201569D0/en
Publication of GB2387268A publication Critical patent/GB2387268A/en
Withdrawn legal-status Critical Current

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Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1275Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by other printing techniques, e.g. letterpress printing, intaglio printing, lithographic printing, offset printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108Male die used for patterning, punching or transferring

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

A silicon stamp suitable for manufacturing integrated circuits is formed from a silicon wafer having a base 3 and a layer 2 on a surface thereof, which may be silicon dioxide grown on the surface, which is etched to form stamp recesses 4. Sub-nanometre scale powder is applied to the wafer in the form of an ink 5. The wafer is pressed onto a substrate 6, and the ink on areas of the stamp surface not in the recesses is transferred onto the substrate 6. The ink may contain sub-nanoparticles of silicon suspended in a non-reactive liquid vehicle.

Description

Silicon Stamped Circuits This invention relates to the manufacture process
of integrated circuits using a silicon stamp and nanoparticle ink solution.
Current methods of creating integrated circuits requires large wafer's of silicon to be patterned many times by applying a photoresist layer which is then exposed to ultra violet light though a mask to create bare region's The i wafer is then placed into an oven for several hours where either layer's are grown on or elements are diffused though the exposed regions of the wafer to create features. The total process can take week's to create a fully tunctionai circuit. MIT Media Labs are currently working on way's to print - integrated circuits using nanoparticle silicon ink and high resolution inlet printer's though the size of the current [eature's are extremely large compared to current methods.
According to the present invention there is a stamp created from a silicon wafer using current photolythic methods. This entails growing a layer onto the silicon water, silicon dioxide is preferable but other type's of layer's could À be use, using thermal oxidation or C.V.D. (chemical vapor disposition) andiis then polished to create a flat surface. A layer of photoresist is applied and exposed to ultraviolet light, either though a mask or using a beam which is optically narrowed or widened, so exposed section's of the photoresist can be easily removed. These exposed region's can then allow the layer below be etched creating pit's. The remaining photoresist can then be removed. This stamp then has a layer of (sub)nanoparticle ink, which is a (sub)nanoparticle À powder of the substance you want in the layer suspended in a non-reactive liquid, applied to it, for example by a fine mist sprayed onto it or being rolled onto it, which is then pressed onto a substrate, for example plastic or glass, to create a print where the photoresist was not exposed to the ultraviolet light. A specific embodiment of the invention will now be described by way of À example with reference to the accompanying drawing in which: Figure shows the silicon wafer with a layer grown on top and a layer of photoresist applied Figure 2 shows the etched wafer of silicon which is the stamp used Figure 3 shows the stamp with (subnanoparticle ink applied to it Figure 4 show's the substrate being printed using the made stamp
Referring to the drawing the silicon stamp comprises a silicon base 3 and a grown layer on top 2 which is etched to create pits 4 using a photoresist layer to pattern the etching area. A layer of (sub) nanoparticle ink 5 is applied to a substrate 6.
In order to create a stamp the silicon wafer 3 first has a layer grown onto the top 2 using thermal oxidation or C.V.D (chemical vapor disposition). This top layer is then polished to create an extremely flat surface and a layer of photoresist 1 is applied to the surface as shown in figure 1. The photoresist is then exposed to ultra violet light, creating areas on the photoresist which can be easily removed. The exposed regions are then etched to create pit's 4 as shown is figure 2. The non exposed regions of photoresist are removed and a layer of (sub) nanoparticle ink 5 is applied to the wafer as shown in figure 3.
The wafer is then pressed onto a substrate 6 which leaves (subnanoparticle ink 5 on the non-exposed regions on top of the substrate 6 and the ink in the let's 4 remain on the water creating a pattern on the substrate as shown in figure 4.

Claims (1)

  1. I A silicon wafer patteren and used as a stamp to print (sub)nanoparticle powder in a solution onto a substrate 2 A stamp as claimed in (Jaim 1' wherein the wafer is made of another material
GB0201569A 2002-01-22 2002-01-22 Silicon stamped circuits Withdrawn GB2387268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0201569A GB2387268A (en) 2002-01-22 2002-01-22 Silicon stamped circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0201569A GB2387268A (en) 2002-01-22 2002-01-22 Silicon stamped circuits

Publications (2)

Publication Number Publication Date
GB0201569D0 GB0201569D0 (en) 2002-03-13
GB2387268A true GB2387268A (en) 2003-10-08

Family

ID=9929637

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0201569A Withdrawn GB2387268A (en) 2002-01-22 2002-01-22 Silicon stamped circuits

Country Status (1)

Country Link
GB (1) GB2387268A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005046299A1 (en) * 2003-10-07 2005-05-19 Darren Edward Robertson An apparatus and method for manufacturing integrated circuits, microelectromechanical system (mems) devices and nanofilters
US20110244116A1 (en) * 2010-04-02 2011-10-06 Centre Nationale De La Recherche Scientifique Selective nanoparticle assembly systems and methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512131A (en) * 1993-10-04 1996-04-30 President And Fellows Of Harvard College Formation of microstamped patterns on surfaces and derivative articles
JP2000106033A (en) * 1998-09-28 2000-04-11 Mitsuboshi Belting Ltd Copper conductor paste
WO2000070406A1 (en) * 1999-05-12 2000-11-23 Thin Film Electronics Asa Methods for patterning polymer films, and use of the methods
WO2001020402A1 (en) * 1999-09-14 2001-03-22 Massachusetts Institute Of Technology Fabrication of finely featured devices by liquid embossing
US6309798B1 (en) * 1996-05-08 2001-10-30 Studiengesellschaft Kohle Mbh Lithographical process for production of nanostructures on surfaces
EP1283541A2 (en) * 2001-08-06 2003-02-12 Samsung SDI Co., Ltd. Method of fabricating field emission display employing carbon nanotubes

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512131A (en) * 1993-10-04 1996-04-30 President And Fellows Of Harvard College Formation of microstamped patterns on surfaces and derivative articles
US6309798B1 (en) * 1996-05-08 2001-10-30 Studiengesellschaft Kohle Mbh Lithographical process for production of nanostructures on surfaces
JP2000106033A (en) * 1998-09-28 2000-04-11 Mitsuboshi Belting Ltd Copper conductor paste
WO2000070406A1 (en) * 1999-05-12 2000-11-23 Thin Film Electronics Asa Methods for patterning polymer films, and use of the methods
WO2001020402A1 (en) * 1999-09-14 2001-03-22 Massachusetts Institute Of Technology Fabrication of finely featured devices by liquid embossing
EP1283541A2 (en) * 2001-08-06 2003-02-12 Samsung SDI Co., Ltd. Method of fabricating field emission display employing carbon nanotubes

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005046299A1 (en) * 2003-10-07 2005-05-19 Darren Edward Robertson An apparatus and method for manufacturing integrated circuits, microelectromechanical system (mems) devices and nanofilters
US20110244116A1 (en) * 2010-04-02 2011-10-06 Centre Nationale De La Recherche Scientifique Selective nanoparticle assembly systems and methods
US8475869B2 (en) * 2010-04-02 2013-07-02 Rhodia Operations Selective nanoparticle assembly systems and methods

Also Published As

Publication number Publication date
GB0201569D0 (en) 2002-03-13

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