GB2380029A - Active address content addresable memory - Google Patents
Active address content addresable memoryInfo
- Publication number
- GB2380029A GB2380029A GB0226599A GB0226599A GB2380029A GB 2380029 A GB2380029 A GB 2380029A GB 0226599 A GB0226599 A GB 0226599A GB 0226599 A GB0226599 A GB 0226599A GB 2380029 A GB2380029 A GB 2380029A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory
- addresable
- aacam
- cpu
- active address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A present invention provides a system and method for avoiding memory hazards in a multi-threaded CPU which shares an L-1 data cache. The system includes a CPU and an AACAM. The AACAM is capable of copying memory addresses from the two or more threads being processed by the CPU. The method provides for comparing the AACAM memory address with the active threads to avoid memory hazards by thread switching before the memory hazard occurs.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/564,202 US6915395B1 (en) | 2000-05-03 | 2000-05-03 | Active address content addressable memory |
PCT/US2001/013270 WO2001084304A2 (en) | 2000-05-03 | 2001-04-24 | Active address content addressable memory |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0226599D0 GB0226599D0 (en) | 2002-12-24 |
GB2380029A true GB2380029A (en) | 2003-03-26 |
GB2380029B GB2380029B (en) | 2005-04-06 |
Family
ID=24253548
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0226599A Expired - Lifetime GB2380029B (en) | 2000-05-03 | 2001-04-24 | Active address content addresable memory |
Country Status (4)
Country | Link |
---|---|
US (1) | US6915395B1 (en) |
AU (1) | AU2001259144A1 (en) |
GB (1) | GB2380029B (en) |
WO (1) | WO2001084304A2 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003167737A (en) * | 2001-11-30 | 2003-06-13 | Nec Corp | Stack use method |
US7711934B2 (en) * | 2005-10-31 | 2010-05-04 | Mips Technologies, Inc. | Processor core and method for managing branch misprediction in an out-of-order processor pipeline |
US7734901B2 (en) * | 2005-10-31 | 2010-06-08 | Mips Technologies, Inc. | Processor core and method for managing program counter redirection in an out-of-order processor pipeline |
US20070204139A1 (en) | 2006-02-28 | 2007-08-30 | Mips Technologies, Inc. | Compact linked-list-based multi-threaded instruction graduation buffer |
US7721071B2 (en) * | 2006-02-28 | 2010-05-18 | Mips Technologies, Inc. | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor |
US7370178B1 (en) | 2006-07-14 | 2008-05-06 | Mips Technologies, Inc. | Method for latest producer tracking in an out-of-order processor, and applications thereof |
US7650465B2 (en) | 2006-08-18 | 2010-01-19 | Mips Technologies, Inc. | Micro tag array having way selection bits for reducing data cache access power |
US7657708B2 (en) | 2006-08-18 | 2010-02-02 | Mips Technologies, Inc. | Methods for reducing data cache access power in a processor using way selection bits |
US8032734B2 (en) * | 2006-09-06 | 2011-10-04 | Mips Technologies, Inc. | Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor |
US7647475B2 (en) * | 2006-09-06 | 2010-01-12 | Mips Technologies, Inc. | System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue |
US20080082793A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Detection and prevention of write-after-write hazards, and applications thereof |
US7594079B2 (en) * | 2006-09-29 | 2009-09-22 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
US8078846B2 (en) | 2006-09-29 | 2011-12-13 | Mips Technologies, Inc. | Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated |
US9946547B2 (en) * | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
US8468306B2 (en) * | 2008-02-15 | 2013-06-18 | International Business Machines Corporation | Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions |
GB2469299B (en) | 2009-04-07 | 2011-02-16 | Imagination Tech Ltd | Ensuring consistency between a data cache and a main memory |
JP5850774B2 (en) * | 2012-03-22 | 2016-02-03 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device and system using the same |
GB2519108A (en) * | 2013-10-09 | 2015-04-15 | Advanced Risc Mach Ltd | A data processing apparatus and method for controlling performance of speculative vector operations |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2321544A (en) * | 1996-12-16 | 1998-07-29 | Ibm | Concurrently executing multiple threads containing data dependent instructions |
WO1999031594A1 (en) * | 1997-12-16 | 1999-06-24 | Intel Corporation | System for ordering load and store instructions that performs out-of-order multithread execution |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761476A (en) * | 1993-12-30 | 1998-06-02 | Intel Corporation | Non-clocked early read for back-to-back scheduling of instructions |
US6170051B1 (en) * | 1997-08-01 | 2001-01-02 | Micron Technology, Inc. | Apparatus and method for program level parallelism in a VLIW processor |
US6298431B1 (en) * | 1997-12-31 | 2001-10-02 | Intel Corporation | Banked shadowed register file |
US6341341B1 (en) * | 1999-12-16 | 2002-01-22 | Adaptec, Inc. | System and method for disk control with snapshot feature including read-write snapshot half |
-
2000
- 2000-05-03 US US09/564,202 patent/US6915395B1/en not_active Expired - Lifetime
-
2001
- 2001-04-24 AU AU2001259144A patent/AU2001259144A1/en not_active Abandoned
- 2001-04-24 WO PCT/US2001/013270 patent/WO2001084304A2/en active Application Filing
- 2001-04-24 GB GB0226599A patent/GB2380029B/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2321544A (en) * | 1996-12-16 | 1998-07-29 | Ibm | Concurrently executing multiple threads containing data dependent instructions |
WO1999031594A1 (en) * | 1997-12-16 | 1999-06-24 | Intel Corporation | System for ordering load and store instructions that performs out-of-order multithread execution |
Non-Patent Citations (1)
Title |
---|
WALLACE ET AL: "Threaded multiple path execution" COMPUTER ARCHITECTURE, 1998. PROCEEDINGS. THE 25TH ANNUAL INTERNATIONAL SYMPOSIUM ON. BARCELONA, SPAIN 27 JUNE-1 JULY 1998, LOS ALAMITOS, CA, USA, IEEECOMPUT. SOC, US, 27 June 1998, pages 238-249, XP010291395, ISBN: 0-8186-8491-7 * |
Also Published As
Publication number | Publication date |
---|---|
WO2001084304A2 (en) | 2001-11-08 |
US6915395B1 (en) | 2005-07-05 |
GB0226599D0 (en) | 2002-12-24 |
AU2001259144A1 (en) | 2001-11-12 |
WO2001084304A3 (en) | 2002-08-08 |
GB2380029B (en) | 2005-04-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Expiry date: 20210423 |