GB2379524A

GB2379524A - Multiplexing pins on an ASIC

Info

Publication number: GB2379524A
Application number: GB0121585A
Authority: GB
Inventors: Anthony Paul Banks
Original assignee: NEC Technologies UK Ltd
Current assignee: NEC Technologies UK Ltd
Priority date: 2001-09-06
Filing date: 2001-09-06
Publication date: 2003-03-12
Also published as: GB0121585D0

Abstract

An ASIC device 60 is provided with a number of test input pins 62, 64, 66, 68, 70 and a selection input pin 72. A multiplexor 74 is used to select between a first set of internal connections 86, 90, 94, 98, 102 associated with a JTAG test and a second set of internal connections 88, 92, 96, 100, 104 associated with a scan test based on the signal input 72. This reduces the number of pins needed for the ASIC.

Description

Multiplexing test pins on an ASIC The present invention relates to an apparatus for multiplexing test pins on an ASIC, in particular on an ASIC containing two serial chains for test purposes.

Modern systems often incorporate one or more ASIC devices which include a processor core. These devices typically contain two serial chains for test purposes.

The first chain is the scan test chain. This is added by the manufacturer of the module and used to test whether the chip is operating correctly. Scan tests are typically executed before any devices are connected to the chip.

The scan test may require 5 pins during interfacing which access the internal nodes of the chip.

Once the chip has been successfully tested devices may then be connected to the chip. At this stage JTAG (Joint Test Access Group) tests are executed. JTAG tests are used to test the connectivity of devices within the system during manufacture. Typically the tests are used to check for open circuits or short circuits. JTAG tests are also likely to be executed when locating a fault within a system. JTAG tests require 5 test pins during interfacing.

Since each of the tests require 5 pins during interfacing, a typical device must dedicate a total of 10 pins to scan and JTAG testing.

Both scan and JTAG tests are typically only executed during production of a system or when a fault is to be located. In everyday use of the system the pins used for interfacing during scan or JTAG testing are redundant.

One design constraint on ASIC devices as commonly used in modern systems is the number of pins available on the package.

The present invention provides a means for multiplexing the 5 pins required to interface during scan or JTAG testing such that they can carry control signals to operate both JTAG and scan tests. One further pin is introduced and the input of this pin determines whether the JTAG or scan test interface is initiated. The effect of the multiplexing is to reduce the number of signal pins from 10 to 6.

This reduction in the number of pins may allow the design to fit into smaller packages and allow a cost saving to be made. Furthermore, the smaller device is more suitable to systems in which space is constrained and the reduction in number of pins reduces the number of pins required to be routed to the package on the PCB.

According to the present invention there is provided an apparatus for reducing the pin count on an ASIC device comprising at least one external operation pin, at least two internal connections wherein the number of internal connections is greater than the number of operation pins, a selection pin, a switch connected to each operation pin wherein said switch is operable to connect said operation pin to one of the internal connections in dependence on a signal applied to the selection pin.

A preferred embodiment of the present invention will now be described with reference to the accompanying drawings in which;

Figure 1 shows the arrangement of testing pins on a typical ASIC device; Figure 2a shows a preferred embodiment of the present invention during a JTAG test; Figure 2b shows a preferred embodiment of the present invention during a scan test Figure 3 is a flow diagram showing the initiation and execution of a test.

Figure 1 shows an embodiment of a typical ASIC device 10 capable of performing both JTAG and scan tests. The ASIC device dedicates 5 pins to scan interfacing and 5 pins to JTAG interfacing. During JTAG interfacing the JTAG interface is executed through the JTAG reset pin 12 which carries the TRSTN (Asynchronous reset input for the JTAG controller state machine) signal 14, the JTAG clock 16 which carries the TCK (Clock input for the JTAG controller state machine) signal 18, the JTAG mode pin 20 which carries the TMS (Mode select input for the JTAG controller state machine) signal 22, the JTAG data-in pin 24 which carries the TDI (Data input for the serial JTAG chain) signal 26 and the JTAG data-out pin 28 which carries the TDO (Data output from the serial JTAG chain) signal 30.

During scan interfacing the scan reset pin 32 carries the SRST (Asynchronous reset input for the scan controller state machine) signal 34, the scan clock 36 carries the SCK (Clock input for the scan controller state machine) signal 38, the scan mode pin 40 carries the SMS (Mode select input for the scan controller state machine) signal 42, the scan data-in pin 44 carries the SDI (Data input for the serial scan chain) signal 46 and the scan data-out pin 48 carries the SDO (Data output from the serial scan chain) signal 50.

A preferred embodiment of the present invention is shown in Figure 2a. The ASIC device 60 provides a total of 6 pins for use in interfacing both JTAG and scan tests namely a reset pin 62, clock pin 64, mode pin 66, data-in pin 68, data-out pin and testmux pin 72. Each of the pins is able to carry the appropriate signal for executing either a JTAG or scan test.

The state of the testmux pin determines whether a scan or JTAG test is initiated. The signal from the testmux pin 72 is forwarded to the multiplexor 74. The multiplexor controls the circuit path from the pins within the ASIC device depending on the signal received by the testmux pin. Each of the 5 test pins are connected to a separate switch within the multiplexor. The switches complete the circuit appropriately to interface either a JTAG test or a scan test. In Figure 2a the testmux input = 0, in this case the multiplexor sets each of the switches to JTAG interface.

The reset switch 76 is set for a JTAG interface allowing the TRSTN signal 86 to be sent. The clock switch 78 is set for a JTAG interface allowing the TCK signal 90 to be sent. The mode switch 80 is set for a JTAG interface allowing the TMS signal 94 to be sent. The data-in switch 82 is set for a JTAG interface allowing the TDI signal 98 to be sent. The data-out switch 84 is set for a JTAG interface allowing the TDO 102 signal to be received.

In Figure 2b the testmux input is set to 1. In this case each of the switches within the multiplexor are set for scan test interface. The reset switch 76 is set for a scan interface allowing a SRST signal 88 to be sent. The clock switch 78 is set for a scan interface allowing the SCK signal 92 to be sent. The mode switch 80 is set for a scan interface allowing the SMS signal 96 to be sent. The data-in switch 82 is set for a scan interface allowing the

SDI signal 100 to be sent. The data-out switch 84 is set for a scan interface allowing the SDO 104 signal to be received.

Figure 3 is a flow diagram showing the initiation and execution of a test. At 120 a decision is made as to whether a test is to be executed. If yes, the user decides what type of test is to be executed at 122. If a JTAG test is to be executed the TESTMUX input is set to 0 at 124. Having set the TESTMUX input, the remaining 5 pins carry appropriate signals to execute a JTAG test at 126. A JTAG test is then executed at 128.

If a scan test is to be executed at 122'the TESTMUX input is set to 1 at 124'. Having set the TESTMUX input, the remaining 5 pins carry appropriate signals to execute a scan test at 126'. A scan test is then executed at 128'.

It is clear from the above description that the present invention facilitates a reduction in the total number of pins on a device which is capable of executing both scan and JTAG tests.

Claims

Claims 1. An apparatus for reducing the pin count on an ASIC device comprising at least one external operation pin, at least two internal connections wherein the number of internal connections is greater than the number of operation pins, a selection pin, a switch connected to each operation pin wherein said switch is operable to connect said operation pin to one of the internal connections in dependence on a signal applied to the selection pin.
2. An apparatus for reducing the pin count on an ASIC device according to claim 1 wherein the signal from said at least one identity pin is forwarded to said multiplexor.
3. An apparatus for reducing the pin count on an ASIC device according to claim 1 or 2 wherein said ASIC device can execute a scan test.
4. An apparatus for reducing the pin count on an ASIC device according to claim 1, 2 or 3 wherein said device can execute a JTAG test.
5. An apparatus for reducing the pin count on an ASIC device substantially as herein described, with reference to the accompanying drawings 2a, 2b and 3.