GB2377548A - TFT fabrication process - Google Patents
TFT fabrication process Download PDFInfo
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- GB2377548A GB2377548A GB0100216A GB0100216A GB2377548A GB 2377548 A GB2377548 A GB 2377548A GB 0100216 A GB0100216 A GB 0100216A GB 0100216 A GB0100216 A GB 0100216A GB 2377548 A GB2377548 A GB 2377548A
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 239000002131 composite material Substances 0.000 claims abstract description 20
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 35
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 229910052786 argon Inorganic materials 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- -1 phosphorous ions Chemical class 0.000 claims description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910000077 silane Inorganic materials 0.000 claims description 2
- 238000005979 thermal decomposition reaction Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000002207 thermal evaporation Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
A first gate oxide layer 22a is formed by oxidizing a thin film polysilicon silicon layer 10a, subsequently the structure is annealed to improve the parametric performance of the device, a second gate oxide layer 24a comprising TEOS is then deposited by CVD and densified using a high temperature anneal. The first and second oxide layers form a composite gate oxide layer of a TFT device. Alternatively, the TEOS layer may be formed directly on the polysilicon active layer and densified using an annealing process.
Description
1 2377548
METHOD OF FABRICATING A GATE DIELECTRIC LAYER
FOR A THIN FILM TRANSISTOR
5 The present invention relates to methods used to fabricate integrated circuits, and more specifically to a method used to form a gate oxide dielectric layer for a thin film transistor.
10 Thin film transistors (TFT) have been used for specific integrated circuit applications. One such application for TFT devices has been in the area of liquid crystal display (LCD) panels. A transmissive-type LCD display panel comprises an array of light valves that 15 selectively transmit incident light, in order to form an image on a display screen when the panel is backlit by a strong incandescent or fluorescent light source. Driving circuitry is provided to operate the light valves.
Typically each light valve is energized by a TFT device, 20 addressed along row and column addressing lines.
The TFT devices are comprised with a dielectric layer, used as the gate insulator layer, formed on a channel portion of an underlying active layer. For conventional 25 metal oxide semiconductor field effect transistor
(MOSFET), used for memory and logic applications, the gate insulator layer is a thin silicon dioxide layer, thermally grown on an underlying single crystalline, silicon substrate. In contrast, the gate dielectric layer used in 30 TFT applications, is formed on an underlying active region comprised of polysilicon. Unlike single crystal silicon, this polysilicon layer is comprised of numerous small grains which creates an uneven surface. The ability to
thermally grow a gate dielectric layer, with the desired integrity is adversely influenced by the unevenness of the underlying polysilicon surface, when compared to counterpart gate dielectric layers formed on underlying 5 single crystalline silicon surfaces. Therefore a conventional gate dielectric layer formed on this uneven polysilicon surface will give inadequate TFT parametric integrity such as low gate oxide breakdown voltage and high gate leakage current.
The present invention will describe fabrication procedures used to improve the integrity of a gate dielectric layer, for a TFT device, formed on an underlying active layer, such as polysilicon. The 5 present invention will feature specific growth and anneal sequences for the TFT gate dielectric layer, which have been demonstrated to improve the parametric performance of the overlying gate insulator layer. The present invention will also describe a novel process sequence, used to 20 improve the integrity of a deposited gate dielectric layer. The deposited gate dielectric layer can either be used as an overlying component of a composite gate dielectric layer, comprised of the deposited layer on the underlying thermally grown gate dielectric layer, or used 2s as the gate dielectric layer, directly on the underlying active layer. Prior art, such as Arghavani et al, in U.S.
Patent No. 6, 124,171, as well as Tai et al, in U.S. Patent No. 6, 121, 035, describe methods of forming silicon dioxide gate dielectric layers on underlying single 30 crystalline silicon substrates, however these prior arts
do not describe the novel process sequence, introduced in this present invention, in which specific growth and anneal procedures are detailed for a composite gate
dielectric layer, or for a thermally deposited gate dielectric layer, on an underlying, non-single crystalline, active layer.
5 It is an object of this invention to fabricate a thin film transistor (TFT), featuring a gate dielectric layer formed on an underlying polysilicon, active layer.
It is another object of this invention to form a gate lo dielectric layer on an underlying polysilicon, active layer, via thermal deposition of a silicon oxide layer, followed by an anneal cycle.
It is still another object of this invention to 5 thermally grow a thin gate dielectric layer, on the underlying polysilicon active layer followed by an anneal prior to the thermal deposition of an overlying gate dielectric layer which has been shown to improve the TFT parametric performance.
In accordance with the present invention a method of forming a gate dielectric layer, for a TFT device, is described. An active layer of polysilicon is provided on an underlying insulator layer. For a first embodiment of 25 this invention a thin, first dielectric layer is thermally formed, in an oxidizing ambient, on the underlying, polysilicon active layer. A first, in situ anneal cycle is then performed at a temperature greater than the temperature used for thermal growth of the thin first gate 30 dielectric layer. An overlying, second gate dielectric layer is next thermally deposited on the underlying thin, first gate dielectric layer, with the second gate dielectric thickness adjusted to meet circuit capacitance
requirements. A second anneal cycle is then performed to density the second gate dielectric layer. Deposition of an overlying polysilicon layer is followed by patterning of the polysilicon layer, and of the composite gate 5 dielectric layer, to form the gate structure for the TFT device. Formation of a source/drain region, in an area of the polysilicon active layer, not covered by the gate structure, complete the process sequence for the TFT device. A second embodiment of this invention entails thermal deposition of the second gate dielectric layer directly on the top surface of the polysilicon active layer. An anneal procedure is then employed for densification 15 purposes. Deposition of an overlying polysilicon layer, and patterning of the polysilicon layer and of the second gate dielectric layer, form the desired gate structure, followed by formation of the source/drain region.
20 The object and other advantages of this invention are best described in the preferred embodiments with reference to the attached drawings that include: Figures 1-5, which schematically, in cross-sectional 25 style, describe key stages of fabrication used to create a TFT device featuring a composite gate dielectric layer comprised of an underlying, thin thermally grown gate dielectric layer, and an overlying, thermally deposited gate dielectric layer; and Figures 6-8, which schematically, in cross-sectional style, describe key stages of fabrication used to create a
TFT device featuring a gate dielectric layer obtained via thermal deposition procedures.
The method of fabricating a gate dielectric layer, or 5 composite gate dielectric layer, for a TFT device will now be described in detail. The TFT will be formed on an underlying insulating substrate 1. Any suitable insulating substrate may be employed, such as silicon oxide, sapphire, or preferably quartz. The first lo embodiment of this invention will describe a composite gate dielectric layer, comprised of an underlying, thin gate dielectric layer, thermally grown, and an overlying, thicker, gate dielectric layer, thermally deposited. The use of an underlying, thermally grown gate dielectric 5 layer enhances the integrity of the composite gate dielectric layer, for example in terms of gate dielectric breakdown and leakage characteristics, when compared to counterparts comprised with only one gate dielectric layer, thermally deposited directly on an underlying 20 active layer. An active layer lea, shown schematically in Fig. 1, is then formed on insulating substrate 1.
Active layer lea, is a semiconductor material, such as a polysilicon layer, and is formed on insulating substrate 1, via a low pressure chemical vapor deposition (LPCVD), 25 procedure between about 500 to 1500Angstroms. A first, gate dielectric layer 22a, shown schematically in Figure 1, is next thermally grown on active layer, or polysilicon layer lea, a temperature between about 800 to 1100 C, preferably about 900 C, in an oxidizing ambient, such as 30 a mixture of oxygen in argon or nitrogen. The thermal oxidation procedure performed for a time between about 15 to 30 min. results in the growth of a silicon dioxide, gate dielectric layer at a thickness between about 50 to
150 Angstroms, preferably 100 Angstroms. However the many small grains, and many grain boundaries contained in polysilicon layer lea cause surface roughness which results in a gate dielectric layer exhibiting lower 5 integrity in terms of dielectric breakdown voltage and leakage, than counterpart gate dielectric layers that were thermally grown on single crystalline silicon substrates, comprised without small grains and numerous grain boundaries.
To improve TFT parametric performance, an anneal procedure is performed in an non-oxidizing ambient, resulting in active layer lob. The anneal procedure is accomplished in situ, by increasing the temperature in the 5 same furnace used for growth of first gate dielectric layer 22a, by an amount between about 10 to 20%. This results in an anneal temperature between about 900 to 1200 C, preferably about 1000 C. An inert ambient comprised of either nitrogen or argon is used for an 20 anneal time of about 3 to 5 furs. The time of anneal, between about 10 to 15 times longer than the oxidation time, results in a TFT with improved device parametric performance to be realized when compared to counterpart dielectric layers, overlying an active layer comprised 25 with smaller grains, thus more grain boundaries.
The second component of the composite dielectric layer, needed to satisfy the thickness requirement for the TFT gate dielectric layer, is next addressed and 30 schematically described using Figures 3-4. A chemically vapor deposited, silicon oxide layer, is used for the thicker, second gate dielectric layer 24a. Second gate dielectric layer 24a, is obtained via thermal deposition
procedures, using tetraethylorthosilicate (TEOS), as a source. Silicon oxide layers, obtained via TEOS thermally deposition procedures, have produced silicon dioxide layers exhibiting greater uniformity when compared to 5 silicon dioxide layers obtained via plasma enhanced chemical vapor deposition (PECVD), TEOS procedures.
Second gate dielectric layer 24a, is deposited to a thickness between about 500 to 700 Angstroms, to bring the total thickness of the composite dielectric layer to lo between about 550 to 850 Angstroms. Second gate dielectric layer 24a, shown schematically in Figure 3, is thermally deposited at a temperature between about 600 to 700 C. To decrease porosity in the as deposited, second gate dielectric layer 24a, an anneal cycle is performed at 15 a temperature between about 900 to 1000 C, in an ambient comprised of a mixture of argon or nitrogen, and oxygen.
The annealing of second gate dielectric layer 24a, results in the creation of second gate dielectric layer 24b, comprised with less porosity, and improved device 20 parametric performance, when compared to unannealed counterparts. The result of this procedure is schematically shown in Figure 4.
The completion of the TFT device is next addressed and 25 schematically shown in Figure 5. A polysilicon layer 30, is deposited via low pressure chemical vapor deposition (LPCVD), procedures, to a thickness between about 3000 to 5000Angstroms. Polysilicon layer 30, is either doped in situ during deposition, via the addition of arsine or 30 phosphine, to a silane ambient, externally doped in a diffusion tube by the use of PH3 or PoCl gas sources or polysilicon layer 30, is deposited intrinsically then doped via implantation of arsenic or phosphorous ions.
Conventional photolithographic and reactive ion etching (RIE), procedures, are then employed to pattern polysilicon layer 30, second gate dielectric layer 24b, and first gate dielectric layer 22b, creating gate 5 structure 40. The RIE procedure used for definition of gate structure 40, employs C12 or SF6 as a selective etchant for polysilicon layer 30, while CHF3 or CF9 is used as an etchant for the gate dielectric layers, selectively terminating at the appearance of active layer 10 lob. After removal of the photoresist shape, used to define gate structure 40, source drain region 12, is formed in a region of active layer lob, not covered by gate structure 40, via implantation of arsenic, or phosphorous ions, at an energy between about 50 to 100KeV, 5 and at a dose between about lE15 to lE16 atoms/cm2.
Subsequent processing steps used to produce a final TFT device, such as the addition of metal interconnect structures, and passivation layers, familiar to those skilled in the art, will not be described in detail here.
A second embodiment of this invention, featuring the use of a single, gate dielectric layer, is now described.
After deposition of active layer, or polysilicon layer 10a, using identical conditions previously described in 25 the first embodiment, is again used. A thermally deposited, gate dielectric layer 24a, obtained using TEOS as a source, is next formed on active layer 10a, at a thickness between about 300 to 900 Angstroms, preferably 600 Angstroms, again using conditions identical to 30 conditions previously used in the first embodiment, for deposition of second gate dielectric layer 24a. This is schematically shown in Figure 6. To improve the density of the as deposited, gate dielectric layer 24a, an anneal
procedure is performed, again using the identical anneal procedures applied to second gate dielectric layer 24a in the first embodiment. The result of this anneal procedure is the creation of second, gate dielectric layer 24b, 5 shown schematically in Fig. 7, on active layer lOa. An anneal procedure, previously applied to active layer lOa, in the first embodiment, could be used if required in the second embodiment even though a thermally grown, first gate dielectric layer is not used. The conditions of this lo anneal are identical to those described in the first embodiment. &ate structure 50, comprised of polysilicon layer 30, and second gate dielectric layer 24b, is next performed, 15 using conventional photolithographic and RIE procedures, again using C12 or SF6 as an etchant for polysilicon, while using CHF3 or CF as an etchant for second gate dielectric layer 24b. Source/drain region 12, is again formed in regions of active layer lea, not covered by 20 gate structure 50. The result of these procedures are schematically shown in Fig. 8. The use of only a single, thick, gate dielectric layer, illustrated in the second embodiment, offers reduced process complexity when compared to the composite, gate dielectric layer, featured 2s in the first embodiment. However the composite gate dielectric layer, featuring the use of the thermally grown, underlying dielectric component, provides improved device parametric performance, when compared to TFT devices comprised with only a single, thermally deposited, 30 gate dielectric layer.
While this invention has been particularly shown and described with reference to, the preferred embodiments
thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.
Claims (1)
- Claims:1. A method of forming a composite gate dielectric layer for a thin film transistor (TFT), device, comprising 5 the steps of: providing an insulating substrate; providing an active semiconductor layer on said lo insulating substrate; thermally growing a first gate dielectric layer, in a furnace, on said active semiconductor layer; 5 performing a first anneal procedure to change said active semiconductor layer; thermally depositing a second gate dielectric layer on said first gate dielectric layer; and performing a second anneal procedure to create a densified second gate dielectric layer, resulting in said composite gate dielectric layer comprised of said densified second gate dielectric on said first gate 2s dielectric layer.2. The method of claim l, wherein said active semiconductor layer is a polysilicon layer, obtained via low pressure chemical vapor deposition (LPCVD), 30 procedures, to a thickness between about 500 to 1000 Angstroms.3. The method of claim 1, wherein said first gate dielectric layer is a silicon dioxide layer, at a thickness between about SO to 150 Angstroms, obtained via thermal oxidation procedures, performed in an ambient 5 comprised of a mixture of oxygen in either argon or nitrogen, at a temperature between about 800 to 1100 C, and performed for a time between about 15 to 30 min. 4. The method of claim 1, wherein said first anneal lo procedure, used to change said active semiconductor layer, is performed at a temperature between about 900 to 1200 C, in a nitrogen or argon ambient, for a time between about 3 to 5 furs.IS 5. The method of claim 1, wherein said second gate dielectric layer is a thermally deposited silicon oxide layer, obtained at a thickness between about 500 to 700 Angstroms, deposited at a temperature between about 600 to 700 C, using tetraethylorthosilicate as a source.6. The method of claim 1, wherein said second anneal procedure, used to create said densified second gate dielectric layer, is performed at a temperature between about 900 to 1000 C, in an ambient comprised of a mixture 25 of oxygen in either nitrogen or argon.7. A method of forming a thin film transistor, featuring a composite gate dielectric layer,on an insulating substrate, comprising the steps of: providing said insulating substrate;forming a first polysilicon layer on said insulating substrate; thermally growing a first silicon oxide layer, in a 5 furnace, on said first polysilicon layer; performing a first anneal procedure, in situ in said furnace, to improve TFT parametric performance; thermally depositing a second silicon oxide gate dielectric layer, 10 on underlying, said first silicon oxide dielectric layer, via thermal decomposition of tetraethylorthosilicate (TEOS); performing a second anneal procedure to density said 15 second silicon oxide gate dielectric layer, resulting in said composite gate dielectric layer, comprised of densified, said second silicon oxide gate dielectric layer on said first silicon oxide gate insulator layer; 20 depositing a second polysilicon layer; patterning of said second polysilicon layer, and of said composite gate dielectric layer to create a polysilicon gate structure on said composite gate 25 dielectric layer; and forming a source/drain region in a portion of said large grain size polysilicon layer, not covered by said polysilicon gate structure.8. The method of claim 7, wherein said first 30 polysilicon layer is obtained via low pressure chemical vapor deposition (LPCVD), procedures, to a thickness between about 500 to 1500 Angstroms.9. The method of claim 7, wherein said first silicon dioxide gate dielectric layer is thermally grown to a 5 thickness between about 50 to 150 Angstroms, via thermal oxidation procedures performed in an ambient comprised of a mixture of oxygen in either argon or nitrogen, at a temperature between about 800 to 1100 C, and for a time between about 15 to 30 min. 1C. The method of claim 7, wherein said first anneal procedure, used to improve TFT parametric performance is performed at a temperature between about 900 to 1200 C, in a nitrogen or argon ambient, for a time between about 3 to 5 furs.11. The method of claim 7, wherein said second silicon oxide gate dielectric layer is a thermally deposited silicon dioxide layer, obtained at a thickness between 20 about 500 to 700 Angstroms, deposited at a temperature between about 600 to 700 C, using tetraethylorthosilicate as a source.12. The method of claim 7, wherein said second anneal 25 procedure, used to density said second silicon oxide gate dielectric layer, is performed at a temperature between about 900 to 1000 C, in an ambient comprised of a mixture of oxygen, in either nitrogen or argon.30 13. The method of claim 7, wherein said second polysilicon layer is obtained via low pressure chemical vapor deposition (LPCVD), procedures, at a thickness between about 3000 to 5000 Angstroms, and either doped insitu, during deposition, via the addition of arsine, or phosphine, to a silane ambient, doped using PH3 or PoCl source in a diffusion tube or deposited intrinsically then doped via implantation of arsenic or phosphorous ions.14. The method of claim 7, wherein said polysilicon gate structure, on said composite gate dielectric layer, is formed via a reactive ion etching procedure, using Cl2 or SF6 as an etchant for said second polysilicon layer, lo while using CF4 or CHF3 as an etchant for said composite gate dielectric layer.15. The method of claim 7, wherein said source/drain region is formed via implantation of arsenic or IS phosphorous ions, at an energy between about 50 to lOOKeV, at a dose between about lel5 to lel6 atoms/cm2.16. A method of forming a thermally deposited, gate dielectric layer, for a thin film transistor device, So comprising the steps of: providing said insulating substrate; forming an active semiconductor layer on said 2s insulating substrate; thermally depositing a silicon oxide gate dielectric layer on said active semiconductor layer, using tetraethylorthosilicate as a source; and performing an 30 anneal procedure to density said silicon oxide gate dielectric layer.17. The method of claim 16, wherein said active semiconductor layer is a polysilicon layer, obtained via low pressure chemical vapor deposition (LPCVD), procedures, to a thickness between about 500 to 1500 5 Angstroms.18. The method of claim 16, wherein said silicon oxide gate dielectric layer is a thermally deposited silicon oxide layer, obtained at a thickness between about 500 to lo 700 Angstroms, deposited at a temperature between about 600 to 700 C, using tetraethylorthosilicate as a source.19. The method of claim 16, wherein said anneal procedure, used to density said silicon oxide gate 5 dielectric layer,:is performed at a temperature between about 900 to 1000 C, in an ambient comprised of a mixture of oxygen in either nitrogen or argon.20. A method as claimed in claim 1 and substantially 20 as hereinbefore described.21. A method as claimed in claim 7 and substantially as hereinbefore described.25 22. A method as claimed in claim 16 and substantially as hereinbefore described.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0100216A GB2377548B (en) | 2001-01-05 | 2001-01-05 | Method of fabricating a gate dielectric layer for a thin film transistor |
| US09/773,872 US6887743B2 (en) | 1999-03-22 | 2001-02-02 | Method of fabricating a gate dielectric layer for a thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0100216A GB2377548B (en) | 2001-01-05 | 2001-01-05 | Method of fabricating a gate dielectric layer for a thin film transistor |
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| Publication Number | Publication Date |
|---|---|
| GB0100216D0 GB0100216D0 (en) | 2001-02-14 |
| GB2377548A true GB2377548A (en) | 2003-01-15 |
| GB2377548B GB2377548B (en) | 2003-06-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0100216A Expired - Fee Related GB2377548B (en) | 1999-03-22 | 2001-01-05 | Method of fabricating a gate dielectric layer for a thin film transistor |
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| CN113451119A (en) * | 2020-03-25 | 2021-09-28 | 和舰芯片制造(苏州)股份有限公司 | Method for improving uniformity of grid oxide layer |
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|---|---|---|---|---|
| US5543635A (en) * | 1994-09-06 | 1996-08-06 | Motorola, Inc. | Thin film transistor and method of formation |
| US5663077A (en) * | 1993-07-27 | 1997-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films |
| US5712208A (en) * | 1994-06-09 | 1998-01-27 | Motorola, Inc. | Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants |
| US5726087A (en) * | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
| US6168980B1 (en) * | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
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2001
- 2001-01-05 GB GB0100216A patent/GB2377548B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5726087A (en) * | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
| US6168980B1 (en) * | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US5663077A (en) * | 1993-07-27 | 1997-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films |
| US5712208A (en) * | 1994-06-09 | 1998-01-27 | Motorola, Inc. | Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants |
| US5543635A (en) * | 1994-09-06 | 1996-08-06 | Motorola, Inc. | Thin film transistor and method of formation |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0100216D0 (en) | 2001-02-14 |
| GB2377548B (en) | 2003-06-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20200105 |