GB2375243A

GB2375243A - Monitoring, storing and indicating the status of supply voltages

Info

Publication number: GB2375243A
Application number: GB0200947A
Authority: GB
Inventors: Stefan Hackl
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 2001-01-17
Filing date: 2002-01-16
Publication date: 2002-11-06
Anticipated expiration: 2022-01-16
Also published as: FR2820219A1; DE10101971A1; GB0200947D0; GB2375243B; FR2820219B1

Abstract

A device 1 for monitoring supply voltages EV1, EV2 of a braking system 2 having a controller 11, comprises memories 14, 15. Each memory 14, 15 is associated with a supply voltage to be monitored and comprises a set input 7, 8, a signaling output 9, 10 and a reset input 12, 13. Upon dectection of a drop or failure of a supply voltage, the mode of operation of the associated memory 14, 15 is changed from standby to signal. The memory 14, 15 remains in its signal mode until it is reset via reset input 12, 13 by the controller 11. In this way, an indication of failure of the corresponding supply voltage is maintained even when the supply voltage is corrected. The device is particularly suitable for monitoring supply voltages for safety systems in vehicles in which a limited quiescent current is required.

Description

1 2375243

A DEVICE FOR MONITORING AND STORING THE STATUS OF

SUPPLY VOLTAGES

The invention relates to a device for monitoring and 5 storing the status of supply voltages of electrical systems, in particular, monitoring and storing drop or failure of a supply voltage in, for example, electrical control system such as safety systems in vehicles.

10 Electrical safety systems in vehicles such as electromechanical braking systems are increasingly used. Naturally, it is desirable that such safety systems do not fail. In this connection, reliability criterion is based on whether a failure and, in 15 particular, a total failure has occurred in the power supply of the system during its inactive state, i.e. when the power supply is not needed. Such failures can be used as an indication that a total failure of the power supply is a threat in the active state of the 20 system.

It is known to monitor the supply voltage of controlled components of a control system within the controller itself. In order to minimize the current consumption in 25 vehicle electrical circuits, it is generally required that a certain quiescent current of approximately 100 WA is not exceeded in any of the vehicle components when they are in their inactive state. However, known types of controllers, which monitor supply voltages, 30 cannot be used in a vehicle system since the quiescent current of the controller would exceed 100 A. Therefore detection and storage of total failure of the supply voltage by a controller in such a vehicle

electrical system in its inactive state would not be feasible. Furthermore, upon power supply failure, the starting-up 5 of the system and the appropriate error detection and processing are no longer possible unless a further power source is available that can supply the power necessary for activation. The supply-voltage failure can not then be detected after the system is started 10 up.

Therefore independent monitoring and storage of the status of the power supply of electrical control systems is not possible in its deactivated quiescent 15 state.

According to an aspect of the present invention there is provided a device for monitoring at least one supply voltage (EVl, EV2) of an electrical system, the 20 electrical system including a control device, wherein the monitoring device comprises: at least one memory device operable within a predetermined quiescent current level and, following failure of the at least one supply voltage (EV1, EV2), the operational mode of 25 the memory device is changed from a standby mode to a signal mode; a set input of the memory device coupled to the at least one supply voltage (EV1, EV2) to be monitored; a signaling output, coupled to the control device of the electrical system, for transmitting a 30 status to the control device; and a reset input coupled to the control device for resetting the memory device from its signal mode to its standby mode.

Accordingly the present invention provides, separately from the actual control device, at least one memory device that can be operated within a limited quiescent current and the status of the memory device is changed 5 following failure of the supply voltage from its standby mode to its signal mode. In this connection, there are provided a set input coupled to the supply voltage to be monitored, a signaling,output coupled to a control device of the system for transmitting the 10 status of the memory device to the control device and a reset input coupled to the control device via which the status of the memory device can be reset from the signal mode to the standby mode by the control device.

In this way, indication that the power supply has 15 failed is then stored in the memory device and is not erased by reactivating the power supply.

Essentially, the information that is relevant for safety systems, for example, and information that a 20 power source is no longer available (has failed) is immediately stored in the memory device. Storage is achieved without the assistance of the system control device (controller) and can consequently be implemented with a very severely limited quiescent current. In 25 order to prevent indication of failure of the supply voltage being erased from the memory device during recovery of the power source, the memory device, according to the present invention, can be reset by the control device to its standby mode from its signal mode 30 via a reset input. Preferably, storage of a failure is made in such a way that the memory associated with a power source is set in the event of failure of the power source to a predefined state that is maintained

if the power source should happen to become available again. In an activated control system, this state can then be scanned and evaluated. Thereafter, the memory device can in turn be set again to its standby mode in s which a further voltage failure can be detected and stored. Preferably, the device of the presen,t invention further provides, at the signaling output of the at least one 10 memory device, a low level signal in the case of a correct supply voltage and a high level signal in the event of a power supply failure. This means that the output does not operate against the corresponding input of the control device (controller) , which would result 15 in a higher quiescent current when the control device is no longer supplied with voltage, i.e. switched-off.

Further features, details and advantages of the present invention can be found in the description below, in

20 which an exemplary embodiment is explained in greater detail by reference to the attached drawings in which: Figure 1 shows a block circuit diagram of a memory device comprising two memory devices 25 according to an embodiment of the present invention; and Figure 2 shows a circuit diagram of one of the status memory devices of Figure 1.

With reference to Figure 1, the device l monitors two supply voltages EV1, EV2 which are applied in parallel.

The supply voltages Evl, EV2 are the power source for

an electromechanical braking system 2. The monitoring device 1 comprises two memory devices 14, 15 associated with each power supply EV1, EV2, respectively. The supply voltages EV1, EV2 are input via protective 5 diodes 3, 4.

In order to be able to track the status of the two supply voltages EV1, EV2 completely even with the braking system 2 deactivated, the supply voltages EV1, 10 EV2 are connected via suitable tapping lines 5, 6 to set inputs 7, 8 of the monitoring device 1. The monitoring device 1 comprises two signaling outputs 9, 10 via which the monitoring device 1 is connected to a central controller 11, the central controller 11 15 controlling the braking system 2. The monitoring device 1 further comprises two reset inputs 12, 13, via which the controller 11 resets the respective memories 14, 15.

20 The two memory devices 14, 15 can be operated with a limited quiescent current of less than 100 MA, and independently of the operation of the controller 11. If the supply voltages EV1, EV2 are properly applied, a low level signal is output at the signaling outputs 9, 25 10. In this case, the memory devices 14,15 are operating in a standby mode. As soon as one or both supply voltages EV1 and/or EV2 fail, at least for a short time, this is logged in one of the respective memories 14, 15 by setting the signal level high. This 30 results in the status of the memory device 14,15 associated with the failed supply changing from its standby mode to a signal mode. The memory device 14,15 remains in its signal mode and cannot be erased even by

reapplying the supply voltage(s) EV1 or EV2. This results in a clear signal detectable by the controller 11 at the signaling output 9, 10. In this respect, therefore, supply voltage failures can also be detected 5 during the inactive state of the controller 11 after it has been started up and appropriately evaluated.

Thereafter, the memory device 14, 15,can be reset again by the controller 11 from its signal mode to its 10 standby mode via the reset inputs 12, 13.

Figure 2 shows the structure of one of the memory devices 14 which is monitoring the supply voltage EV1.

The memory device 14 comprises a bistable flip-flop 15 having two AMOS field-effect transistors FET1, FET2

whose drain-source sections (Dl-Sl, D2-S2) are each connected between the set input 7 and ground via respective drain resistors R1, R2. The gate G1, G2 of the transistors FET1, FET2 are connected to the drain 20 connections D1, D2 of the respective other transistors FET1, FET2 via gate resistors R3, R4. Further, the gate G1 of the transistor FET1 is connected to ground via a capacitor C. 25 The drain D1 of the transistor FET1 forms the signaling output 9 of the memory device 14. The reset input 12 is coupled to the gate G1 of the transistor FET1.

As a result of the circuitry of the memory device 14 of 30 the preferred embodiment, a low level signal is present at the signaling output 9 whilst the correct supply voltage EV1 is present at the set input 7. A soon as the supply voltage drops (fails), the transistors FET1,

FET2 switch, as a result of which the signaling output 9 is set to a high level. The switching state of the transistors FET1, FET2 can be changed again via the reset input 12 and the system can be returned to its 5 standby mode. Similarly the supply voltage EV2 is monitored by the second memory device 15.

Although a preferred embodiment of the present invention has been illustrated in the accompanying 10 drawings and described in the forgoing detailed description, it will be understood that the invention

is not limited to the embodiment disclosed, but is capable of numerous variations, modifications without departing from the scope of the invention as set out in 15 the following claims.

Claims

1. A device for monitoring at least one supply voltage (EV1, EV2) of an electrical system, the 5 electrical system including a control device, wherein the monitoring device comprises: at least one memory device operable within a predetermined quiescent current level and, following failure of the at least one supply voltage (EV1, EV2), lo the operational mode of memory device is changed from a standby mode to a signal mode; a set input of the memory device coupled to the at least one supply voltage (EV1, EV2) to be monitored; a signaling output, coupled to the control device 15 of the electrical system, for transmitting a status to the control device; and a reset input coupled to the control device for resetting the at least one memory device from its signal mode to its standby mode.

2. A device according to Claim 1, wherein the

monitoring device further comprise a plurality of memory devices for monitoring a plurality of supply voltages, each memory device being associated with a 25 respective supply voltage.

3. A device according to Claim 2, wherein the device further comprise two memory devices having respective set inputs, signaling outputs (9, 10) and reset inputs 30 for monitoring two parallel supply voltages.

4. A device according to any one of the preceding claims, wherein the quiescent current level is less than 100 WA.

5 5. A device according to any one of the preceding claims, wherein each memory device comprises a pair of MOSFET transistors, the gate of each transistor is connected to the drain of the other,transistor as a bistable flip-flop.

6. A device according to any one of the preceding claims, wherein a low level signal is present at the at least one signaling output to indicate a correct supply voltage (EV1, EV2).

7. A device substantially as hereinbefore described with reference to the accompanying drawings.