GB2371953A - Viterbi equalizer which compares received data with predicted data based on the channel response estimate to generate path metrics - Google Patents

Abstract

The present invention concerns an equaliser for use in processing received serial data signals (20,21) sent by a transmitter and which may have been distorted during their transmission, the equaliser includes a trellis generator 23 which receives both the serial data signals and the output of a channel estimator 24 so as to generate the most probable bit sequence sent by the transmitter. The trellis generator operating by allocating to each branch of the trellis entering a particular state an individual branch metric which is based on the space distance between the received signal and the predicted signal received from the predictor 25 for that state so that each branch metric is different from any other branch metric, and operates by calculating the two survivors of each Viterbi butterfly in the trellis at the same time.

Description

VITERBI EOUALISER

The present invention concerns equalisers for use in processing received serial data signals sent by a transmitter and which may have been distorted by noise during their transmission. The purposes of the equaliser is to correct as far as possible the distortions to the signal caused by the noise. Equalisers of this kind find particular application in GSM (Global System for Mobile communication) in order to combat noise, channel distortion and Inter-Symbol Interference (ISI) caused by GMSK (Gaussian Minimum Shift Keying) modulation. The present invention is particularly concerned with a Maximum Likelihood Sequence Estimator (MLSE) which utilises the Viterbi algorithm to find a best path through a trellis. The Viterbi algorithm is a very common algorithm implemented in many communication systems and is used in equalisation and convolutional decoding.

Unlike convolutional decoders that operate on probability or Hamming branch metrics, the branch metrics of an MLSE equaliser using the Viterbi algorithm are formed from the signal space distance between the actual received signal and a predicted signal for a particular state.

In a conventional Viterbi decoder and in conventional equalisers using the Viterbi algorithm it will be appreciated that the trellis through which the optimum path is calculated reaches a state in which it consists of what are known as Viterbi butterflies. Each butterfly has two source states leading via branches to two end states so that each end state has as an input a branch from a source state. In calculating survivors the metrics of each path to an end state are compared and the lowest value path selected. In a convolution decoder operating on this principal the two survivors of a Viterbi butterfly are calculated in an extremely efficient manner in two cycles by using two path metrics and two branch metrics and by swapping the branch metrics between cycles. This done by using an ACS (Add, Compare, Select) function. However as will be described this procedure is very inefficient when applied to an MLSE equaliser.

In other known Viterbi equalisers each column of the trellis has associated registers which store the survivors which become the path entries for the next column. However this hardware approach is expensive to implement and also uses a large amount of electrical power.

Another type of equaliser which has been used is the DFE (Decision Feedback Equaliser) which has fewer of the hardware and power penalties set out above but is suboptimal in operation.

Additionally some MSLE equalisers follow the Viterbi decoder practise so that the survivors of a column of the trellis are computed by an ACS instruction in two cycles by swapping branch metrics from the first cycle to the second. However the procedure means that the survivor of the second cycle is erroneous as in the equaliser all the branch metrics are different So that the outcome of the second cycle has to be discarded as it operates on the same metrics.

This procedure also has a significant number of disadvantages. The calculation of each branch metric takes a significant amount of processor time which is greater than the ACS instruction used to calculate the survivor. Additionally because of the switching of the branch metrics means that only one survivor is calculated per ACS instruction. Thus memory is needed to place the non-valid values and whilst this could be non-existent space a bus access is still required. Electrical and processor power are wasted on the invalid calculation and

finally in order to compute the second survivor the pointer to the old path metrics has to be decremented.

It is accordingly a concern of the present invention to provide an equaliser employing the Viterbi algorithm which operates in a computationally efficient manner without the need for extensive hardware.

In accordance with a first aspect of the present invention there is provided an equaliser for use in processing received serial data signals sent by a transmitter and which may have been distorted during their transmission, the equaliser comprising a channel estimator which receives the serial data and generates as an output an estimate of the complex channel impulse response over a sequence of the received serial data bits, a predictor which receives the output of the channel estimator and which produces a predicted received signal based on the output of the channel estimator for 2N combinations of N received bits, a trellis generator which receives both the serial data signals and the output of the channel estimator so as for each of the N data bits output by the channel estimator to generate the most probable bit sequence sent by the transmitter so as to output a data sequence, and wherein

the trellis generator operates by allocating to each branch of the trellis entering a particular state an individual branch metric which is based on the space distance between the received signal and the predicted signal received from the predictor for that state so that each branch metric is different from any other branch metric, and operates by calculating the two survivors of each Viterbi butterfly in the trellis at the same time, and a trace back function for operating on the output of the trellis so as to generate a recovered bit sequence.

In order that the present invention may be more readily understood an embodiment therefore will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a typical transmission and reception channel for speech and data employing an MLSE equaliser.

Figure 2 is a diagram illustrating a typical data packet format used in mobile phone transmission; Figure 3 is a block diagram showing the equaliser of Figure 1 in slightly greater detail;

Figures 4a and 4b show respectively a trellis for a 3-tap channel and a Viterbi butterfly ; Figure 5 is a diagram illustrating the computation of branch metrics; Figure 6 and 7 are flow diagrams, and Figure 8 is a block diagram of a hardware accelerator Referring now to Figure 1 of the drawings this shows the constituents of a transmission channel for speech and data incorporating an MLSE equaliser. The particular transmission channel shown is that of a mobile phone where of course the transmitted data is sent from a transmitter to a receiver by radio. Nevertheless it will be appreciated that the present invention is applicable to MLSE equalisers used in other scenarios and that the transmission path between transmitter and receiver need not necessarily be a radio link.

In Figure 1 the transmitter end of the channel comprises a Source Coding circuit 1 for coding, and in particular compressing, input speech. The output of circuit 1 is supplied for a convolution encoder 2, which is

conventional, to protect and spread the data and the output of the encoder 2 is connected to an interleaving circuit 3 for interleaving the encoded sequential data over multiple transmitted data packets so if a data packet is lost from the channel only individual bits rather than a whole data packet block needs to be reconstructed by the channel decoder. These data packets are known in the GSM as slots. As shown in Figure 3 a typical slot incorporates a tail 4, data packages 5, a training sequence 6 and another tail. Naturally the format of a slot can be varied in accordance with the nature of the main transmission channel. The additional data which is to be interleaved with the speech data to form a slot is input directly into the convolutional encoder 2.

The actual radio transmitter for the data encoded by encoder 2 is shown at 10 and as is common with GSM transmits the encoded slots with phase quadrature with quadrature components I and Q.

At the receiving end the transmitted signal is received by a radio receiver 11 and the quadrature components I and Q of the received signal are supplied to an MLSE equaliser 12 the output of which is taken to a de

interleaver 13 in turn supplying the de-interleaved data to a Viterbi decoder 14. The output of the decoder 14 is supplied to a Source De-coding circuit 15 so that the original speech data can be decompressed and reconstituted.

Convolutional encoder 2, interleave circuit 3 and the Viterbi decoder 14 are entirely conventional and will not be described in detail. Also conventional are the respective Source Coding, Interleave, De-interleave and Source Decoding circuits 1,13 and 15. Also indicated in Figure 1 is a notional Adder circuit 16 where unwanted noise generated at 17 is added to the signal under transmission. As already mentioned such noise in a mobile phone system can be electrical and atmospheric noise, channel distortion and ISI.

Referring now to Figure 3 of the accompanying drawing this Figure illustrates the MLSE equaliser 12 in greater detail. In Figure 3 the I and Q components output by the receiver 11 are input to the equaliser at 20 and 21 respectively. In operation the Equaliser 12 attempts to predict the original transmitted bit sequence by comparing the actual received sequence with a predicted sequence. The predicted sequence is computed by passing

all 2N possible states through an N-tap estimate of the radio channel. Thus if N is 6 there are 64 predicted sequences.

In the Equaliser 12 a Viterbi trellis is implemented to compute the maximum likelihood of the transmitted sequence. This is necessary because the superposition of impulse noise, Gaussian noise and time varying multipath channels will almost inevitably cause the estimated channel impulse response to a burst of data to be different from the actual channel impulse response.

In the equaliser 12 of Figure 3 the input I and Q components are supplied both to a Trellis Generator 23 and to a Channel Estimator 24. The number of coefficients N computed from the channel estimator used in the Trellis Generator 23 and predictor 25 is a matter of engineering design as processing demands increase enormously as N increases. A common compromise between accuracy and processing requirements is to use a 5,6 or 7-tap channel.

The channel estimator 24 receives the input I and Q data and generates as an output an estimate of the complex channel impulse response over the whole burst. The

output of channel estimator 24 is supplied to a predictor circuit 25 which produces 2N predicted received signals based on the output of the channel estimator 24 for all possible 2N combinations passed through the N-tap channel. As a result of the input from the predictor circuit 25 the trellis generator 23 allocates to each branch of the trellis entering a particular state an individual branch metric (BM) based on the space distance between the received I and Q data and the predicted signal received from the predictor circuit 25.

It will be appreciated that in the present embodiment the function of the discrete blocks shown at 23,24, 25,26 in Figure 3 are all carried out in software by a programmable computer.

Figure 4a of the accompanying drawing shows a trellis of the kind found in a Viterbi equaliser or decoder. For reasons of simplicity Figure 4A shows a 3-tap Viterbi channel. In this figure the first bit is input at 30 with subsequent bits in the signal being supplied to successive columns of the trellis. Each node 31 of the trellis indicates a potential state and will be referred to herein after as a state. Also from the Figure 4A it can be seen that the trellis reaches a steady state after

N-1 columns and that in this state there are 2 branches leaving each old state and likewise two branches entering each new state. Each branch, such as branch 32, which enters a state, has a branch metric which, as already discussed, is computed as the space distance between the actual received signal and the predicted signal for that state. In the equaliser trellis the predicted value for a particular state is the value of that state code preceded by a'0'and a'1'as new bits are shifted in from the left thus allowing for all possible transitions from the old state to the new state. Accordingly each branch in the trellis shown in Figure 4A has a different branch metric from the other branches.

In the trellis shown in Figure 4A the branch metric (BM) for an individual branch can be defined as:

BMo/i,tat.= received.word (k)-predictedwo ! : d, . t.-.. (1) Given :the received-word I and Q values of rez and rx Q for a particular word at discrete time k and the predicted-word I and Q values of predicted. I and predicted~Q for a particular state, then

BMo/state = (rx.I (k)-predicted Io/i-state)'+ (rxQ (k)predictedQ,/ita, 2.... (2) Thus again considering the 3-tap channel trellis depicted in Figure 4A for one column as shown in Figure 5 the branch metrics are computed as : BMooo= (rx~I (k) -predicted~Iooo) 2+ (rx~Q (k) -predicted~Qooo) 2 BMIOo= (rx.I (k)-predictedII,,) 2+ (rxQ (k)-predicted~Qi..) 2 BMo, i= (rxI (k)-predictedIIo l) 2+ (rx. Q (k)-predicted~Q. oi) 2 BMI i= (rxI (k)-predictedI) 2+ (rx. Q (k)-predicted-Qlol) 2 BM,O= (rx.I (k)-predictedI,lj) 2+ (rxQ (k)-predictedQonO) 2 BMllO= (rx~I (k) -predicted~IuD) 2+ (rx~Q (k) -predicted~Quo) 2 BM,l= (rx.I (k)-predictedI(,l) 2+ (rx~Q (k)-predicted~Qol) 2 BM= (rx. I (k)-predictedIm) 2+ (rx. Q (k)-predicted~Qm) 2 where predicted. lM ;, = (-l,-l,-l] ahI and predicted.Qaa.=[-l,-l,-l] hQ predicted-Ii, o= [+I,-I,-l) oh-I and predictedi= [+l,-l,-l] g) hQ predicted Iool= [~ +l] @h I and predictedQi= [-l,-l, +l] hQ predictedIj=[+l,-l,+l]hI and predicted Ql0l= [+lr +l] @h-Q predictedII i, = [-l, +l,-l] oh. I and predicted-Qo to= [-l, +l,-l] oh-Q predicted Illo= [+l+l-l] @h I and predicted~Quo= [+1, +1, -1 J 0h~Q predicted. Icn= [-l, +l, +l] hI and predicted, Q,ll= [-l, +l, +lj@hQ predicted. Im= [+l, +l, +l] shI and predicted Qm= [+l, +l, +l] oh. Q In the above hI and h, Q are the estimated impulse response of the I and Q channel, 8 denotes convolution,

and a baseband 0 is transmitted as a'-1'and a baseband 1 is transmitted as a'1'. In the trellis generator 23 at each state 31 a survivor is calculated from the two input branches, the survivor being the lower of the two branch metrics and thus closest to the predicted value. This computation is known as ACS (Add, Compare, Select) and will be described in greater detail hereinafter. Also as will be described hereinafter the different value between the two branches entering the state is stored for subsequent use again as will be described hereinafter.

Figure 4b of the drawings shows what is known as a Viterbi butterfly, which is in effect the branch arrangement between two states in one column of the trellis and two states in the next column.

In the present embodiment the two survivors of a Viterbi butterfly can be calculated simultaneously and as will be described this calculation is done in such a manner that the columns of the trellis do not require individual registers.

Thus a description of the calculation of survivors will now be given with respect to the Viterbi butterfly shown in Figure 4B which of course shows only a part of the trellis shown in Figure 4A and with respect to the flow diagram of Figure 6.

Once a trellis has reached its steady state it will be appreciated that the trellis is then composed entirely of Viterbi butterflies. Accordingly the following description will be directed to the computation involved in determining the two survivors of a Viterbi butterfly on the understanding that whatever the size of N in the complete trellis the computational procedure of the other butterflies will be identical.

Thus the path metric, such as PMoo or PMol as shown in Figure 4B, is the accumulated metric to reach that state, whilst the branch metric BM is the metric required to traverse between states. In Figure 4b only the survivors are shown as these are used as two path metrics for the next column. Relating the values shown in Figure 4b to the three tap trellis shown in Figure 4a and hardware shown in Figure 5 it will be seen that the input branch metrics in the latter figure are defined for the three tap situation. However it will be appreciated that for

values of N other than 3 the hardware arrangement of a Viterbi butterfly shown in Figure 5 will be replicated as often as is required to deal with the number of taps.

Referring now to Figure 5 of the accompanying drawings this shows CPU memory 30 associated with a processor 31. The memory 30 is divided into a number of areas including a buffer area 32 which stores a sequence of received bits normally known as a slot. The memory also includes a buffer area 33 storing the accumulated path metrics of states from which the branches of the butterfly start.

Additionally a buffer area 34 contains the 2N predicted values previously computed by the predictor 25; a buffer area 35 stores path signals generated in a manner to be described hereinafter, and a buffer area 36 storing different values also to be described hereinafter. Under the control of the processor unit 31 the path metrics are accessed and added at adders 37-40 to the respective branch metrics which are the metrics required to traverse from one state to the next state. These metrics are stored in the buffer area 33 of the CPU memory 31. Thus the output of the respective adders are sums the values of which are supplied to comparator selectors 41 and 43 where the value closest to zero is selected as a survivor and becomes the path metric for the next state of the

trellis. Each comparator also computes a signal which indicates by 1 or 0 which branch metric was lowest or highest and the path signal for each column are stacked and stored in the computer memory 30 in buffer area 35.

The output of the adders are also supplied to a pair of subtractors 42,44 which give as outputs the respective differences of their two input. These different values are all stored in buffer area 36. Thus once all the survivors for a column of the trellis have been computed they are returned to the CPU memory 30 and the old path metrics in buffer area 33 are overwritten by the new survivors. The outputs of the address 37-10 are also supplied as shown in Figure 5 to a pair of subtractors 42 and 42 which give difference values as their outputs.

The difference valves are only stored in memory if required for one of two possible modes of output as will be described hereinafter.

As already mentioned the procedure to be followed in the selection of the survivors of a Viterbi butterfly utilising the arrangement illustrated in Figure 5 is, in accordance with the present invention, arranged to be carried out using a single ACS instruction and additionally avoids the use of multiple hard-wired registers for each of the columns of the trellis.

The output of a three tap trellis such as the trellis 23 will be four values for the four states forming the last column of the trellis. For an N tap trellis there will of course be 211-1 values available. The actual output used in the equaliser is the state code of the lowest of the final values available. It is this code which is used by the trace back circuit 26 to indicate where the start of the trace back occurs. To perform the trace back to determine the most likely path through the trellis and thus the most likely transmitted bit sequence the trace back circuit 26 uses this lowest code to select a branch in the trellis from the two branches which entered the selected state. This branch leads to a another state the path signal of which is known from the values of the path states already stored in memory so that the next branch in the trellis can be identified and so on until the complete bit sequence has been recovered for input. In the present embodiment this output is supplied to the de-interleaver 13.

Fundamentally all calculations are carried out by the processor 31 and the two main sets of computations required follow the flow diagrams of Figures 6 and 7.

Turning firstly to the flow diagram 1 Figure 6 this sets out the computational steps required to calculate the survivors and difference values of a Viterbi butterfly.

In step Sl the received slot is stored in buffer 32 and in step S2 a bit is fetched from the buffer for processing in the trellis. In parallel to these steps path metrics stored in step S3 are fetched at step S4 and used with the bit fetched in step S2 to compute at step S5 the branch metrics. In step S6 the path metrics are used by processor 31 to compute the two survivors of the Viterbi butterfly, two path difference signals and two path signals. The two survivors are stored at Step S3 to become the new path metrics and the remaining signals are stored at step S7 in the appropriate buffers in memory 31 for subsequent use in the traceback procedure. In step S3 the survivors are written into memory over the previous survivors for the next computation at step S5.

In the flow diagram of Figure 7 the current state is accessed at step S10, at step Sll the path signal for that state is fetched from the memory and at step S12 the processor computes the index of the current column to select the lowest difference value. For the actual output of the equaliser, namely a sequence of bit values,

two alternative modes can be used. These are respectively a"SOFT"mode in which the difference values for each selected state in the traceback path are output and a"HARD"mode in which the state in output as a 1 or

a 0.

Thus a decision is made as to whether at Step S13"Hard" or"Soft"traceback is to be employed. For"Soft" traceback the difference values from the traced back-back status are fetched from memory at Step S14 and output at step S15 with the actual difference values representing the confidence with which the relevant bit has been identified.

In"Hard"traceback the path select signal is utilised at Step S16 as representing the bit and is output at Step S17.

Many radio communication systems operate on sets of complex (I and Q) data. It is often required as in the

present invention to compute the magnitude of the two I

and Q values,-/+ Q2, for example in power r

measurement. Likewise, in complex computation it is also

often required to compute the distance between 2 complex numbers, for example in computer graphics.

In the equaliser described in this specification, the branch metrics are computed as in equation (2). To actually compute this value, the processor 31 must perform the following pseudo operations :1. Fetch a pre calculated I value from memory, for example predicted~I0/1-state 2. Perform memory register subtraction, computing rx~I(k) - predicted~I0/1-state 3. Perform a multiply to compute (rx~I (k) predicted lOll-state) 2 4. Store this result (I magnitude) 5. Fetch a Q value from memory, for example predicted Q0/1-state 6. Perform memory register subtraction, computing rxQ (k)-predicted. Qo/l-state 7. Perform multiply to compute rx, Q (k)-predicted

QO ! l-state 8. Add this result to the previously computed the I magnitude.

9. Perform shifting and/or scaling.

10. Move the result into a register pair ready for an ACS instruction.

Although these operations are simple, there is a large amount of processor time (approximately 12 cycles depending up shifting or scaling). Also, 4 branch metrics need to be computed per 1 ACS instruction.

Thus a hardware accelerator can be added to the equaliser by a new operation of which is invoked by a sample instruction.

This hardware accelerator is shown in Figure 8 and comprises a pair of multipliers 50,51 the first of which has the value of the first half of equation 2 at each of its two inputs and the other of which has the second half of equation 2 as its input. Then the output of the multipliers 50,51 are supplied to an adder 52 the output of which is the required branch metric.

Claims (10)

1. An equaliser for use in processing received serial data signals sent by a transmitter and which may have been distorted during their transmission, the equaliser comprising a channel estimator which receives the serial data and generates as an output an estimate of the complex channel impulse response over a sequence of the received serial data bits, a predictor which receives the output of the channel estimator and which produces a predicted received signal based on the output of the channel estimator for 2N combinations of N received bits, a trellis generator which receives both the serial data signals and the output of the channel estimator so as for each of the N data bits output by the channel estimator to generate the most probable bit sequence sent by the transmitter so as to output a data sequence, and wherein the trellis generator operates by allocating to each branch of the trellis entering a particular state an individual branch metric which is based on the space distance between the received signal and the predicted signal received from the predictor for that state so that each branch metric is different from any other branch metric, and operates by calculating the two survivors of each Viterbi butterfly in the trellis at the same time,

and a trace back function for operating on the output of the trellis so as to generate a recovered bit sequence.

2. An equaliser according to claim 1, wherein the survivors of a Viterbi butterfly are calculated they are written into memory over the respective path metrics used in their calculation or so as to become path metrics for the next states of the next Viterbi butterfly in the trellis.

3. An equaliser according to claim 1 or claim 2, wherein for each column of the trellis a path signal is calculated in response to the calculation of the survivors and the path signals for each column of the states are stored in memory for subsequent trace back of the input sequence of bits by the trace back function.

4. An equaliser according to claim 3, wherein the trace back function is adapted to calculate the most likely path through the trellis using the lowest state code of the survivors of the last column of the trellis and the stored path signals for the preceding columns of the trellis.

5. An equaliser according to claim 4, wherein when a

survivor is calculated, the difference between the two branch metrics used in the calculation of the survivor is stored in memory, and wherein the difference so stored are output in response to the trace back.

6. An equaliser according to any preceding claim 1, wherein the received data signal is in phase quadrature, and the predictor output for each predicted data bit comprises I and Q values representing the phase quadrature.

7. An equaliser according to any preceding claim,

wherein each branch metric is defined by : BMo/istate- = (rxI (k)-predicted-Io/l-state) 2+ (rx, Q (k)

predicted. Qo/i. ate

8. An equaliser according to claim 7 wherein the calculation of a branch metric is carried out by a hardware circuit comprising a pair of multipliers connected to an adder, one multiplier receiving at its two inputs the value: (rxI (k)-predicted-lo/l-state) and the other multiplier receiving at its two inputs the value:

(rxQ (k)-predicted-Qo/l-state,.

9. An equaliser according to any preceding claim in combination with a convolutional decoder for decoding the equaliser output.

10. A mobile phone including an equaliser and a convolution decoder as claimed in claim 9.