GB2371146A

GB2371146A - Dual damascene interconnect between conducting layers of integrated circuit

Info

Publication number: GB2371146A
Application number: GB0121198A
Authority: GB
Inventors: Richardson O Adebanjo; Yifeng Winston Yan
Original assignee: Agere Systems Guardian Corp
Current assignee: Agere Systems LLC
Priority date: 2000-08-31
Filing date: 2001-08-31
Publication date: 2002-07-17
Also published as: GB0121198D0; JP2002164430A; KR20020018610A

Abstract

An integrated circuit includes a semiconductor layer (14) which may include a MOSFET (18), a conductive metallisation level (62c), and a dielectric layer (64b). An electrical contact (74a) having a wide portion and a narrow portion (such as dual damascene contact) passes through the dielectric layer (64b) between the metallisation level (62c) and the semiconductor layer (14). The integrated circuit may include a further insulating layer (80) and dielectric layer (78) between the electrical contact (74) and the metallisation layer (88) to form a capacitor (70). The electrical contact (74) may connect conductive members (62) of different levels in the structure, and may comprise tungsten, titanium or titanium nitride. The metallisation level (62c) may comprise aluminium. A method of manufacturing the structure is also disclosed where the contact (74a) is formed by forming an opening with narrow and wide portions, and then filling the opening with conductive material.

Description

2371 1 46

Dual Damascene Contact For Integrated Devices Field of the Invention

The present invention relates to semiconductor devices and, more s specifically, to connections between conductive members in circuit structures.

Background

As the level of semiconductor process integration progresses the density of multilevel interconnection schemes continues to increase and the associated feature sizes are becoming smaller. In fact, semiconductor interconnect requirements are lo considered one of the most demanding aspects of ultra large scale integration efforts. Among other concerns, it is becoming more difficult to sustain acceptable levels of device reliability as devices of growing complexity are manufactured at smaller geometries.

Typically, complex semiconductor devices require three or more levels of 5 interconnect in order to effect circuit connections. In these structures connections are made between conductive members on different levels of interconnect by formation of vies or contacts. By way of illustration, in an aluminum metallization scheme the structure is built by alternately forming dielectric layers and patterned metal conductor layers over one another. After each dielectric layer is formed and 20 before the next metallization level is created, the contacts are commonly formed by first etching via openings through the uppermost dielectric layer to expose underlying regions of the previous level of metallization. Barrier metals (e.g., a stack of Ti and TiN) are deposited in the openings, followed by deposition of a refractory metal such as tungsten, although Co and Al may also be deposited. With 25 the width (or diameter) of the openings becoming progressively smaller as device geometries shrink it is common for a void or seam to form in the via opening as the metal is deposited. Often the void extends through the surface of the dielectric layer and becomes exposed as excess metal is removed from the surface, e.g., by chemical mechanical polishing. The resulting structure has been subject of much 30 concern because it leads to reliability problems and frequently requires rework of semiconductor wafers during device fabrication. See B. Kassab et al., "Process

Methodologies to Reduce Rework and Plug Coring in Sub-Quarter Micron Tungsten Chemical Mechanical Planarization Using H2O2 Containing Slurries" June 27-29, Proc. VMIC Conference, pp. 189-194 (2000). See also Y.C. Chang, et al., "Low Temperature CVD TiN Deposition Combined with N2/H2 Plasma Treatment to 5 Prevent Al Extrusion" June 27-29, Proc. VMIC Conference, pp. 297-301 (2000).

One specific problem associated with the formation of voids or seams in metal contacts is known as coring, wherein the polishing process results in enlargement of the void to the point where it affects subsequent fabrication, creating, reliability issues. A second but related problem stems from the conformal nature of 0 materials deposited over the contacts. For example, when a relatively thin dielectric layer is deposited over the exposed void or seam of a contact, the thickness of the layer about this contact seam may further diminish. This may create a short or render the layer so thin in areas that it breaks down under electrical stress. A third problem associated with contact seams, and again magnified by coring, is metal 5 migration, particularly in Al interconnect systems. Electromigration is known to result in movement of Al into contact seams, creating voids in the interconnect layers and leading to device failures.

Overcoming the problems associated with seams in metal contacts would contribute to advancement in the level of integration and device reliability, 20 particularly for devices having metallization schemes fabricated with subtractive metal etch processes.

Summary of the Invention

According to one embodiment of the invention, a semiconductor structure includes spaced-apart metallization levels formed over the semiconductor layer, 25 each level including a conductive member. A contact electrically connects a conductive member in a first of the levels with a conductive member in a second of the levels. The contact includes a narrow portion extending to the conductive member in the first level and a wide portion extending from the narrow portion toward the conductive member in the second level.

30 According to another aspect of the invention, an integrated circuit device is also provided, having a semiconductor layer with a surface formed along a plane. A

metallization level includes a conductive member formed over the surface and a layer of dielectric material, having an upper surface, is formed between the semiconductor surface and the conductive member. An electrical contact extends through the layer of dielectric material along an axis of vertical orientation with 5 respect to the surface. The contact includes a wide portion extending within the dielectric layer from the upper surface and along the axis, and a narrow portion extending along the axis from the wide portion toward the surface of the semiconductor layer.

In still another embodiment, a method of manufacturing a semiconductor 10 structure includes forming over a semiconductor layer a layer of dielectric material having an upper surface. An opening is formed in the dielectric layer. The opening includes a wide portion extending from the upper surface and a narrow portion extending the opening from the wide portion toward the semiconductor layer. Both the narrow portion and the wide portion of the opening are filled with conductor 5 material and a metallization level comprising a conductive member is formed over the opening in electrical contact with the conductor material.

Brief Description of the Drawines

Numerous advantages of the invention will be apparent when the following detailed description of the invention is read in conjunction with the accompanying

20 drawings. in which: Figures 1 illustrates in cross sectional.view an exemplary embodiment of the invention; Figures 2 through 5 illustrate in cross sectional view details relating to fabrication of the Figure 1 embodiment.

25 Like numbers refer to like elements throughout the drawings while it should be noted that various features illustrated in the figures are not to scale with one another. Terminology Illustrated layers and other elements may include two or more sub-layers or 30 sub-elements. When a layer or other element is described as formed or positioned over another feature, that element may be in direct contact with the other feature or

may be spaced apart from the other feature, e.g., by an intervening element.

Further, an element described as over another feature is not necessarily vertically above the feature and may, for example, be formed over a side portion of the other feature. s The terms vertical and horizontal denote an approximately orthogonal orientation of one surface with respect to another surface wherein either surface may be formed in a plane while one or both surfaces may have irregularities or may have curvature such as present along layers and other features of semiconductor devices.

For example, some so-called vertically etched openings are known to have tapered lo profiles. Generally, features resulting from an anisotropic etch, e.g., vies, are characterized as vertical with respect to a crystal plane although the walls may not follow straight lines and the orientation may not be orthogonal with respect to the reference plane.

An interconnect structure is a plurality of conductive members configured to IS support implementation of one or more circuit functions. In complex circuit designs interconnect structures comprise levels, or laminates of sequentially formed layers, which create and electrically isolate the conductive members. A level of metallization or interconnect is a group of conductive members formed during the same sequence of processing, e.g., a stage of photolithography and associated etch 20 steps, to provide a network of conductive members, some of which are isolated from others by dielectric material such as a silicon. oxide or silicon nitride. The conductive members may comprise polysilicon, Al, or Cu. may be an alloy and may include a silicide to reduce sheet resistance.

Detailed Description

2s In the illustrated embodiments the invention enables provision of semiconductor structures with vies having improved reliability. The invention may be applied to a wide variety of semiconductor designs, including complex analog circuitry and so called systems on a chip. In the examples provided, the invention is applied to integrated circuit structures having three or more levels of metallization.

30 For simplicity of presentation, the illustrated embodiments show three such levels of metallization although more or fewer levels may be used. When fabricated with

s exemplary Ultra Large Scale Integration (ULSI) processes, e.g., to create feature sizes of 0.25 micron and less, integrated circuit structures will have circuit densities and electrical performance requirements which may require use of the invention to assure device reliability.

s With reference to the view of Figure 1, the invention is described with respect to formation and connection of a metal oxide metal capacitor structure in a level of interconnect over a semiconductor substrate, and also with respect to formation of a contact between two levels of interconnect. An integrated circuit structure 10, shown in partial cross section, includes a semiconductor layer 14 lo having an upper surface region 12 formed along a horizontal crystal plane. Metal Oxide Semiconductor (MOS) field effect transistors 18 are formed in the region 12.

Other devices, including diodes and other types of transistors (e.g., bipolar devices or MESFETs), may be formed in the surface region 12 but these need not be illustrated for purposes of describing the invention.

is An exemplary one of the transistors 18 is shown to include source/drain regions 20 and a gate structure 22. Although the gate structure 22 is not described in detail the figure illustrates common MOSFET components including a gate dielectric, a gate conductor (typically deposited polysilicon with a silicide formed thereon to reduce sheet resistance) and sidewall filaments formed over the 20 conductive portions to insulate the gate structure from adjoining conductive elements. For simplicity of presentation, other features commonly formed about the upper surface region 12 (e.g., isolation structures) are not shown in the figures.

An initial level 28 of dielectric insulator is deposited over the transistors, and conventionally formed contacts 30, including contacts 30a, provide connection 2s from various transistor regions and other features to overlying levels 40, 50 and 60 of metallization and between levels of metallization. Each level of metallization includes multiple conductive members 62, some of which are illustrated in the figures. The view of Figure 1 is talcen along a plane parallel to the direction in which member 62a in the level 50 of interconnect runs. The figure also illustrates 30 member 62b of level 50, which runs in a direction orthogonal to the direction along which member 62a extends. Multiple members 62 formed in the levels 40 and 60

extend in directions parallel to the member 62b. Generally, the members 69 of each level are formed in an insulative layer 64a or 64b. In this illustration it is assumed the members are formed of Al.

According to the illustrated embodiment, a capacitor 70 is formed in 5 metallization level 60, with connection through a dual Damascene contact 74 to the conductive member 62a of metallization level 50. Most preferably the contact 74 has a plane upper surface 78 providing an interface on which a first metal layer is formed to provide a first capacitor plate 80, with an insulative layer patterned over the plate 80 to provide a capacitor dielectric 84 and a second metal layer formed lo over the dielectric 84 to provide a second capacitor plate 88. A conventional contact 30 provides connection from the second capacitor plate 88 to another level of metallization or to a bond pad (not illustrated). For purposes of illustrating the general usefulness of the invention, another dual Damascene contact 74a is illustrated as connecting conductive member 62b of level 50 to a member 62c in 5 overlying level 60.

Select fabrication details for the integrated circuit structure 10 are described below. However, choice of dielectric and conductor materials may vary depending on application. A brief discussion of methods useful for forming suitable dielectric materials is first provided in relation to the preferred embodiments.

20 Numerous methods are commonly available to form the silicon oxides that electrically isolate conductors from one another in multilevel interconnect structures such as shown in Figure 1. Frequently an interlevel dielectric will comprise sublayers in order to optimize a desired set of attributes such as gap fill and planarity. The first level of interconnect, typically deposited over transistor 2s structures and polysilicon conductors is often a phosphorous and boron-doped deposition. The presence of phosphorous allows reflow at approximately 1000 C while the use of both boron and phosphorous further reduces the flow temperatures.

Dielectric materials providing isolation between metallic conductors in different levels of an interconnect structure (interrnetal dielectrics) may be silicon oxides 30 deposited by chemical vapor deposition (CVD) processes. These include atmospheric CVD, low-pressure CVD (LPCVD) and plasma-enhanced CVD

(PECVD), all of which may be based on decomposition of silane. Addition of phosphorous to the reaction is common, resulting in phosphosilicate glass (PSG) which improves resistance to moisture and Bettering.

Tetraethyl orthosilicate, or TEOS, Si(OC2Hs)4, has been widely used as a 5 precursor in formation of silicon oxide for all interlevel dielectrics. Decomposition of vaporized liquid TEOS to form a silicon oxide film (TEOSdeposited oxide) typically occurs by CVD at 650 C - 750 C in an oxygen environment. Such TEOS depositions are known-to provide good uniformity and step coverage. Generally, the deposited film is understood to be a non-stoichiometric oxide of silicon, 10 although it is often referred to as silicon dioxide. Inclusion of ozone (03), e.g., up to 10 percent of the reacting oxygen, facilitates lower temperature depositions with good conformal properties, low viscosity and improved gap-filling features. A typical reaction environment is at 400C and 300 Torr with 4 standard liters per minute (elm) oxygen, the oxygen comprising 6 percent ozone, 1. 5 slm He and 300 5 standard cubic centimeters per minute (scum) TEOS. The resulting deposit has gap fill properties suitable for regions between individual metal lines on the same level of metallization. The TEOSdeposited film may be doped with phosphorous.

Alternately the silicon oxide layer may be formed by High Density Plasma deposition (HDP). The deposit, referred to as HDP oxide may comprise undoped 20 silicate glass (USG) or floro-doped silicate glass (FSG).

Details regarding the above dielectric materials and other variants are well known. See, for example, Wolf, Silicon Processing for the VLSI Era, Volume 2: Process Integration, Lattice Press 1990.

Select exemplary details for fabrication of the integrated circuit structure 10 25 are illustrated in Figures 2 and 3 for an exemplary subtractive metal etch technology. An initial layer 78 of dielectric insulator is formed over the transistors 18 and exposed portions of the surface region 12. The insulator layer 28 may be formed by first depositing HDP oxide (200 nm + 20 nm) from silane at 350 C to 550 C, followed by plasma enhanced deposition of silicon oxide from TEOS with 30 densification at 700 C for 120 minutes. The resulting thickness of the insulator layer may 28 range up to 9500 nm.

The contacts designated 30a are formed in the insulator layer 28 to provide connection between, for example, various transistor regions and the yet-to-be fonned first level of metallization 40 Contact fonnation in the insulator level 28 begins with patterning of deposited photoresist to define vies, followed by an s anisotropic etch, e.g., CHF3/C2F6. The contacts typically comprise refractory metals.

Matenals of choice include W. Ti and Ta. Preferably all of the contacts are formed with W. After vies are etched the contacts 30a are formed therein by a sequential sputter, first depositing a Ti barrier sublayer (approximately 60 rim at 400C, not 10 illustrated), followed by depositing a TiN sublayer (approximately 75 nm, also at 400C, not illustrated) and then annealing. Next, 400 rim of W is deposited (at 425C) and the structure is then polished to remove metal from the surface of the insulator level 28 and provide sufficient planarity prior to formation of the first level of metallization. The resulting contact is approximately 0.32 micron in width and 5 extends from 650 rim to 950 nm.

After defining the underlying set of contacts 30a the first metallization level 40is formed by a generally well known sequence such as a 400C sequential sputter to form a TilTiN stack (37 nm of Ti' 60 nm of TiN), followed by depositing 400 to 700 rim of Al/Cu alloy and 25 nm of TiN. The conductive members 62 of 20 metallization level 40 are then defined with a standard pattern and etch process.

Over the metallization level 40 (as well as subsequently formed levels 50 and 60) a layer 64 of insulation is deposited, e.g., 600 nm of HOP oxide and 1500 nm of TEOS-deposited silicon oxide. The layer of insulation over level 40 is designated layer 64a in the figures. The structure is planarized with a metal topographic 25 reduction followed by chemical mechanical polishing. A second level of contacts 30 is next formed in the dielectric layer 64a to provide electrical connection between the completed metallization level 40 and the next metallization level 50. As described for the first level of contacts, the second level of conventional contacts 30 are formed by first depositing a Ti barrier followed by deposition of TiN, then an 30 anneal and a W deposition. The exposed surface is then polished back to fully define the contacts 30, remove metal overlying the dielectric layer 64 and provide

sufficient planarity prior to formation of the next level of metallization. The resulting contacts are approximately.36 micron in width.

The foregoing description for forming the first level of interconnect with an

overlying insulator layer 64a with contacts 30 is applicable to each subsequent level 5 of interconnect. Except for features relating to the capacitor 70 (Figure l), the contact 74 and the contact 74a, fabrication of subsequent metallization levels is not described in detail.

With the level 50 of metallization deposited, patterned and etched, another layer 64 of dielectric material (designated 64b in Figure 2) is deposited on the lo structure 10. Formation of the dual Damascene contacts 74 and 74a begins with etching of two via openings 92 in the dielectric layer 64b between the metallization level 50 and the yet to be formed level 60. If conventional contacts 30 are also to be formed between levels 50 and 60, additional openings 92 (not illustrated) are etched at the same time. The openings 92 are lithographically patterned to a width of 5 approximately 0.36 micron and are anisotropically etched (CHF3/C2F6/N2) approximately 600 rim to expose the conductive members 62 of level 50. The openings 92 are cylindrical and vertically oriented with respect to the surface region 12. See again Figure 2.

See next, Figure 3. After a standard clean, the region over the two openings 20 92 is lithographically patterned to a width of approximately 1.2 microns and anisotropically etched (C 3/C2F6/N2) to a depth of approximately 250 nm creating a wide portion 95 over a remaining narrow portion 96 of the original opening 92.

This results in the modified opening 97 illustrated in Figure 3. The wide portion 9S of each modified opening 97 is cylindrical and, within lithographic alignment 25 tolerances, is axially symmetric with the entire opening 92. In the preferred embodiment the narrow portion 96 extends the opening from the wide portion 95 toward the semiconductor layer 14 and through the dielectric layer. However, the narrow portion 96 may widen as the opening extends through the layer 64.

Conductor is formed in the modified opening 97 by first depositing a Ti 30 barrier layer (approximately 60 nm at 400C, not illustrated), followed by depositing approximately 75 nm of TiN (also at 400C, not illustrated) and then annealing.

Next, 400 rim of W is continuously deposited by CVD (at 425C) to fill both the narrow portion 96 and the wide portion 95 of the opening 97. The structure is polished to remove metal from the surface of the insulator level 28 and provide sufficient planarity prior to formation of the next level of metallization. See Figure 5 4. The resulting contact 74 includes an upper wide portion 98 over a lower narrow portion 100. The wide portion 98 has a plane upper surface 102 approximately 1.2 micron in width and the associated depth is approximately 250 nm. The narrow portion 100 is approximately.36 micron in width and 350 nm in depth. The narrow portion 100 may include, as artifact from the deposition of W. a void 104. A feature to of numerous embodiments of the invention is that, to the extent such a void 104 is formed in a contact 74 or 74a, it does not extend to the surface 102. It is believed that such voids may be suppressed from the surface 102 by extending the width of the opening at the surface relative to the narrow portion.

With reference to Figure 5, the capacitor 70 of Figure 1 is formed over the 5 contact surface 102 in conjunction with formation of conductive members 62 in the metallization level 60. A metal layer 110 (which forms the first capacitor plate 80 and a lower layer of the conductive members 62) is deposited overall. This is followed by deposition of an insulative layer 112 (which provides the capacitor dielectric 84) over the metal layer 110.

no The metal layer 110 may be conventionally formed by a sequential sputter to form a TilTiN stack, e.g., 30 nm Ti and 60 rim TiN. The insulative layer may consist of a silicon oxide or tantalum pentoxide deposited over the metal layer 110 by CVD.

Other insulator materials having relatively high dielectric constants are also preferred. 25 Prior to formation of conductor members 62 in metallization level 60, the capacitor dielectric layer 84 is defined by pattern and etch steps to remove the insulative layer 112 from other regions of the structure 10. Preferably, the remaining portion of the layer 112 is rectangular in a plane parallel with the surface region 12 and covers a predefined area consistent with the intended capacitance. In 30 a this embodiment of the invention, the second capacitor plate 88 (Figure 1) is formed as the remaining portion of the metallization level 60 is deposited, patterned

and etched. The metallization level 60 may be completed by depositing 400 to 700 rim of Al/Cu alloy and 25 nm of TiN. When the conductive members 62 of metallization level 60 are defined with a standard pattern and etch process the second capacitor plate 88 is also defined over the layer 84. See Figure 1. A contact s 30 is formed over the second plate 88 to effect connection to an upper level of interconnect or bond pad.

An architecture has been described which is useful for contact regions having a variety of shapes, e.g., cylindrical rectangular, tapered, etc., in circuit structures. Application of this design in accord with the disclosed embodiments 10 assures formation of a plane surface at the interface of electrical contacts and avoiding problems associated with formation of overlying layers which have conformal deposition properties. Specifically, when layers of metal and insulator material are deposited over metal contacts fabricated according to preferred embodiments of the invention, the contacts do not have exposed seams which cause 5 the overlying layers to follow the seam contours. Thus, for example, reliability problems associated with the integrity of the capacitor dielectric about a contact seam are avoided. Also, when interconnect members, e.g., comprising Al, are deposited over contacts formed according to the preferred embodiments of the invention, the Al metal is not exposed to a contact seam which could cause Al 20 metal migration leading to device failure.

While specific applications of the invention have been illustrated, the principles disclosed herein provide a basis for practicing the invention in a variety of ways on a variety of circuit structures including structures formed with III-V compounds and other semiconductor materials. Numerous variations will be 25 apparent. Thus, other constructions, although not expressly described herein, do not depart from the scope of the invention which is only limited by the claims which follow.

Claims

( - We claim:

1. An integrated circuit device comprising: a semiconductor layer having a surface along a plane; a metallization level formed over the surface, the level comprising a 5 conductive member; a layer of dielectric material, having an upper surface, formed between the semiconductor surface and the conductive member; and an electrical contact extending through the layer of dielectric material, the contact including a wide portion extending within the dielectric layer from the upper lo surface and a narrow portion extending along the axis from the wide portion toward the semiconductor layer.

2. The device of claim 1 wherein the narrow portion and the wide portion are each cylindrical in shape and symmetrically oriented along the axis.

3. The device of claim 1 wherein the wide portion of the electrical contact includes 15 a plane surface along the upper surface of the dielectric layer.

4. The device of claim 1 further including: a second insulative layer formed between the electrical contact and the conductive member; and a conductive layer formed between the second insulative layer and the 20 electrical contact, the combination of the conductive member, the second insulative layer and the conductive layer forming a capacitor.

5. The device of claim 1 wherein the conductive member is an interconnect member.

6. The device of claim 1 further including: 25 a second layer of dielectric material, having an upper surface, formed between the semiconductor layer and the electrical contact; and a second level of metallization, including a second conductive member, formed on the upper surface of the second layer of dielectric material, with the electrical contact physically contacting the first conductive member and the second 30 conductive member.

7. The device of claim 6 wherein the electrical contact comprises tungsten, titanium and titanium nitride.

8. The device of claim 1 wherein the electrical contact comprises tungsten.

9. The device of claim 1 wherein the conductive member comprises Al.

5

10. The device of claim 1 wherein the metallization level comprises a plurality of interconnect members for effecting circuit functions.

11. The device of claim 1 wherein the narrow portion extends the opening through the semiconductor layer.

12. A method of manufacturing a semiconductor product comprising: lo providing a layer of semiconductor material; forming over the semiconductor layer a layer of dielectric material having an upper surface; forming in the dielectric layer an opening with a wide portion extending from the upper surface and a narrow portion extending the opening from the wide 5 portion toward the semiconductor layer; and filling both the narrow portion and the wide portion of the opening with conductor material.

13. The method of claim 12 wherein the step of forming the narrow portion includes extending the opening through the layer of dielectric material, the method JO further including forming over the upper surface a metallization level comprising a conductive member in electrical contact with the conductor material.

14. The method of claim 12 further including the step of providing a conductive region over the semiconductor layer and wherein the step of forming the opening includes positioning the opening over the conductive region so that the conductive 2s region is electrically connected to the conductive member of the metallization level.

15. The method of claim 12 wherein the step of forming the conductor in the opening is accomplished by a continuous deposition of metal to fill both the narrow portion and the wide portion.

16. The method of claim 13 further including before formation of the metallization 30 level:

formation of a conductive layer over the wide portion of the opening in electrical communication with the conductor in the opening; and formation of an insulative layer between the conductive layer and the conductive member such that the combination of the conductive layer, the insulative 5 layer and the conductive member form a capacitor.

17. A semiconductor structure comprising: a layer of semiconductor material having an upper surface formed along a crystal plane; a plurality of spaced-apart metallization levels formed over the lo semiconductor layer, each including a conductive member; a contact formed along an axis orthogonal to the plane, the contact electrically connecting a conductive member in a first of the levels with a conductive member in a second of the levels, said contact comprising a narrow portion extending to the conductive member in the first level and a wide portion 5 extending from the narrow portion toward-the conductive member in the second level.

18. The structure of claim 17 wherein the narrow portion extends to the conductive member in the second level.

19. The structure of claim 17 wherein the wide portion is formed over the narrow No portion.

20. The structure of claim 17 wherein the first conductive member is formed over the second conductive member.