GB2369901A

GB2369901A - A circuit for squaring a number using a shifter and selective addition

Info

Publication number: GB2369901A
Application number: GB0029616A
Authority: GB
Inventors: Mel Albert Gerard Long
Original assignee: Ubinetics Ltd
Current assignee: Aeroflex Cambridge Ltd
Priority date: 2000-12-05
Filing date: 2000-12-05
Publication date: 2002-06-12
Also published as: WO2002046911A1; GB2369901A8; AU2002219317A1; GB0029616D0

Abstract

A circuit 10, and method, for squaring a number, Z, comprises a shifter 12 for generating shifted versions of Z. Each shifted version of Z is accumulated into a results register 18 only if a bit of Z corresponding to that particular shifted version of Z is set to one.

Description

236990 1

DATA PROCESSING INVOLVING SOUARIN* A NUMBER

The invention relates to data processing involving the squaring of a number.

Conventional integrated circuits contain multipliers, which are bespoke devices for multiplying together the values held in two operand registers. To calculate the square of number, the same operand is loaded into each of the operand registers for the multiplier.

It is an object of the invention to provide improved apparatus for squaring a number.

According to one aspect, the invention provides apparatus for squaring a binary operand, comprising shifting means and adding means, wherein the shifting means shifts the operand and the adding means selectably adds the shifted operand to a binary total.

According to another, and related, aspect of the invention, there is provided a method of squaring a binary operand, comprising shifting the operand and selectably adding the shifted operand to a binary total.

Multiplication performed in accordance with the invention lends itself to performance by apparatus which consumes a small (relative to conventional multiplier) amount of area in an integrated circuit.

In one embodiment, the addition is performed if a selected bit of the operand is in a predetermined state. Preferably, the predetermined state is "logical 1".

The shifting procedure may produce a plurality of shifted operands, each subjected to a different shift. Each of the shifted operands may have a corresponding operand bit, such that the shift of a shifted operand corresponds to the distance of the corresponding operand bit from the operand's least significant end. The selectable addition of shifted operands may be performed by determining that the shifted operand is to be added to the total if the shifted operand's corresponding bit is in a predetermined state (e.g. "logical 1").

Preferably, the shifted operands are produced sequentially, and a shifted operand is

selectably added to the total before the succeeding shifted operand is produced. This feature allows the multiplication process to be performed recursively, consequentially reducing the amount of data storage that needs to be engaged for the multiplication process.

The invention may be exploited in the processing of digital signals. For example, the invention can be used to condition a digital signal by, for example, producing a signal which is the square or the modulus of an input signal. For example, the invention could be used in the measurement of a quantity such as the power in a digital signal, by calculating the squared amplitude of the digital signal. The invention can be employed to condition signals in communications systems or navigation systems.

The invention also extends to a program causing data processing apparatus to perfonn a method according to the invention. For example, the invention may comprise a program which causes a digital signal processor to condition an input signal by calculating a signal which is the square of the input signal (e.g. for power estimation of the input signal).

By way of example only, an embodiment of the invention will now be described with reference to the accompanying figure which is a block diagram of a squaring device in an integrated circuit.

Referring now to Figure 1, a binary number, Z. to be squared is input to squaring circuit 10.

The number Z is supplied to each of a shifter 12 and a bit selector 14. The shifter 12 outputs an addend to an adder 16. Selector 14 outputs a bit selected from the binary word Z to adder 16 as a control input. The second addend for adder 16 is fed back from a result register 18 which stores the augend output by adder 16. The squaring process is controlled by controller 20 which produces signals So, S2 and So for controlling the operation of the shifter 12, the selector 14 and the register 18, respectively. The operation of the squaring circuit 10 will now be described using as an example the case where Z is a three bit number and, consequently, Z: is a 6 bit number. Let us take the case where Z is 101 (decimal 5).

\ During a first stage of the process, Z is presented to the shifter 12 and the selector 14.

Register 18 is initialised by controller 20. The shifter 12 supplies an unshifted version of Z. l O 1, as an addend to adder 16. The selector 14 transfers the least significant bit of Z as a control input to adder 16. The contents of register 18 (000) are supplied to adder 16 as the other addend. The adder 16 sums the addends if the control signal from the selector 14 is a logical one. Since the least significant bit of Z is one, the adder 16 sums the addends and supplies the resulting augend (101) to register 18, where it is stored.

During the second stage of the calculation, controller 20 directs the shifter to supply to the adder a version of Z that has been shifted by one bit such that a zero is added to its least significant end. The shifted version of Z is supplied as an addend is lOl O. The controller 20 directs selector 14 to select the middle bit of Z as a control input for adder 16. The other addend supplied to adder 16 is the contents of register 18. In this stage, the control signal supplied by selector 14 is zero and so the addition is not performed and the contents of register 18 are not updated. Thus, the contents of register 18 remain as 101.

In the third, and final stage, of the squaring process, the controller 20 directs the shifter 12 to output a version of Z that has been shifted by two bits such that two zeros have been appended to its least significant end. The shifted version of Z now presented to adder 16 is 10100. The controller 20 controls the selector 14 to select the most significant bit of Z as a control input for adder 16. The other addend supplied to adder 16 is the content of register 18, which is 101. In this stage, the control signal from selector 14 is 1 so the adder 16 sums its addends and updates register 18 with its augend, which is 11001, i.e. decimal 25. At the end of this stage, the contents of register 18 represent Z2, there are no more bits of the operand for selector 14 to process, and the squaring operation is complete.

The foregoing example described the use of the squaring circuit lO in relation to 3-bit binary numbers. In that example, it is clear that the shifter 12 needs to be able to output a 5 bit number and that the register 18 must be capable of storing a 6 bit number. In general terms, where Z is a P bit binary number, then the shifter needs to be able to output a number of 2P- 1 bits in length, the register 18 must be capable of storing a number which is 2P bits in length, and the adder 16 does P selectable adding operations.

Staying with the general case where Z is P bits in length, the squaring process performed by the squaring circuit 10 can be described mathematically by the following equation: p-l Z =mI-O Zm Em where: Z is a binary number.

Z2 iS the square of Z. P is the number of bits in Z. Zm iS a version of Z shifted by appending m zeroes to its least significant end.

b,n is the m0' bit of Z. As mentioned earlier, the number of stages in the summation process is equal to the number of bits, P. in the binary word Z.

Claims

1. Apparatus for squaring a binary operand, comprising shifting means and adding means, wherein the shifting means shifts the operand and the adding means selectably adds the shifted operand to a binary total.

2. Apparatus according to claim 1, wherein the adding means performs the addition if a selected bit of the operand is in a predetermined state.

3. Apparatus according to claim 1 or 2, wherein the shifting means is arranged to produce a plurality of shifted operands, each subjected to a different shift.

4. Apparatus according to claim 3, wherein each shifted operand has a corresponding operand bit, such that the shift of a shifted operand corresponds to the distance of the corresponding operand bit from the operand's least significant end.

5. Apparatus according to claim 4, wherein the adding means is arranged to add each shifted operand to the total if the shifted operand's corresponding bit is in a predetermined state.

6. Apparatus according to any one of claims 3 to 5, wherein the shifting means is arranged to produce the shifted operands sequentially, and the adding means is arranged to selectably add a shifted operand to the total before the succeeding shifted operand is produced.

7. Apparatus according to any one of claims 1 to 6, further comprising means for initialising the total before the first addition is made to it.

8. Apparatus according to any one of claims 1 to 7, wherein the adding means is arranged to add the operand to the total if the operand's least significant bit is in a predetermined state.

9. Data processing apparatus comprising the squaring apparatus of any preceding claim.

10. Data processing apparatus according to claim 9, wherein the squaring apparatus is arranged to square values which represent a digitised signal.

11. A method of squaring a binary operand, comprising shifting the operand and selectably adding the shifted operand to a binary total.

12. A method according to claim 11, wherein the addition is performed if a selected bit of the operand is in a predetermined state.

13. A method according to claim 1 1 or 12, wherein the shifting step produces a plurality of shifted operands, each subjected to a different shift.

14. A method according to claim 14, wherein each shifted operand has a corresponding operand bit, such that the shift of a shifted operand corresponds to the distance of the corresponding operand bit from the operand's least significant end.

15. A method according to claim 14, wherein each shifted operand is added to the total if the shifted operand's corresponding bit is in a predetermined state.

16. A method according to any one of claims 13 to 15, wherein the shifted operands are produced sequentially, and a shifted operand is selectably added to the total before the succeeding shifted operand is produced.

17. A method according to any one of claims 11 to 16, further comprising initialising the total before the first addition is made to it.

18. A method according to any one of claims 1 1 to 17, wherein the operand is added to the total if the operand's least significant bit is in a predetermined state.

19. A method of processing data comprising calculating the squares of numbers using the method of any one of claims 11 to 18.

20. The data processing method of claim 19, wherein the numbers for squaring represent values of a digitised signal.

21. A program for causing data processing apparatus to perform the method of any one of claims 11 to 20.

22. Apparatus for squaring a number, substantially as hereinbefore described with reference to the accompanying figure.

23. A method of squaring a number, substantially as hereinbefore described with reference to the accompanying figure.

24. A method of processing a digital signal, substantially as hereinbefore described with reference to the accompanying figure.