GB2366896A - Game machine - Google Patents

Abstract

The invention relates to game machine, for example a game machine to be located in a public place such as a railway station or public house. The game machine has a plurality of resources including payment receiving means 11, a processor 1 for processing gains software, a memory 8 for storing game software and preferably also various input and output devices 12,13. The game machine also has a coordinator unit 3 for controlling data passing between the various resources. In the preferred embodiment the coordinator unit 3, the processor unit 1 and other resources are connected via a data bus and the coordinator unit time slices available memory access time by exploiting the access profile of the processor and accesses the data bus only in a portion of each clock cycle. The coordinator unit carries out various tasks including handling of I/O resources and thus relieves the processor unit of these tasks. The coordinator unit can also be used as a game software development tool and provides for real time emulation of the game machine during game software development. The coordinator unit also takes part in security arrangements (see claims 48 and 49).

Description

2366896 GAME MACHINE The present invention relates to a game machine, for

example to a game machine which can be located in a public place, such as a railway station or a public house- It particularly, but not exclusively, relates to a game machine used for gambling. The present invention further relates to a method of designing or testing game software.

Driven by commercial pressures, the technology of game machines is rapidly advancing, continually attempting to provide the user of the game machines with such a pleasurable experience that he or she is encouraged to use the game machine again.

At this point we should distinguish between game machines which merely entertain the user by sound and visual stimuli (for example video racing games), and those which provide the user with a potential financial return (i.e. gambling machines). The latter type are here referred to as "gaming machines".

A popular and traditional form of gaming machine (often called a "fruit machine") employs spinning reels which are at least partly visible to a user, and generates complex electronic control signals to operate sounders and lights. The processor of a modern fruit machine simultaneously controls the lights and sounders and controls the complex mechanics of the gambling 2 itself. For example, it controls the rotation of the reels and the receiving and dispensing of money. To enhance yet further the visual appeal of such gaming machines, there have been proposals to replace or supplement the reels by a video display.

As game machines become progressively more sophisticated, the computer software required to control them becomes correspondingly longer and more complex.

Moreover, in the case of gaming machines, the technology must have a high level of security to prevent cheating (i.e. fraudulently obtaining money from the machine), and conform to strict legal regulations which govern gambling. At the same time, however, the total computing capacity which is available in a game machine is necessarily limited, since the machine will be too expensive to mass produce if it requires a high-power processor. The level of computing power is particularly limited in the case of a gaming machine. In fact, the maximum computing power (processing speed) which is presently provided in a gaming machine is about 12MHz.

It is imperative that the software of the game machine does not cause the processor to be overloaded at certain moments, and unable to perform what is required of it in real time. In the case of a gaming machine, overloading is particularly liable to occur at moments when the gaming machine is required simultaneously to generate a complex visual output, to pay out money and to 3 generate a complex sound. To generate visual or sound output the gaming machine may include output devices (e.g. lights or sounders) which require periodic refreshing; a conventional gaming machine expends considerable computing power in "housekeeping", such as generating the requisite operating instructions at the refresh rate.

Generally, the designer of game machine software writes the software using apparatus with greater computing capacity than the simple processor of the game machine. For example, the designer may use a powerful PC to write game software for controlling the simple processor of a game machine. To test the game software as and after it is written, the designer is provided with a hard-wired emulator connected to the PC and designed to emulate how the simple processor runs the game software. In the case of a gaming machine, the emulator is a highly sophisticated electronics item, and presently costs about $10,000 per unit. In principle, when the designer tests the game software using the emulator, he or she is able to identify bugs in the game software which cause the simple processor of a real game machine to be overloaded, or to exhibit any other unwanted behaviour.

Once the designer has finished writing the game software, it is downloaded from the PC for storage on a memory chip, which can be installed in a real game machine for use by the processor of the game machine.

Unfortunately, the software is so long (e.g IMbyte) even downloading it from the PC itself takes many minutes. Furthermore, the relatively lowpower processor of the game machine cannot be properly tested until the memory chips carrying the game software have been prepared.

The design of new game machine (i.e. the hardware) and the software of a new game for that machine both require considerable investment, which a supplier of game machines will wish to protect- Consider a situation in which a first game machine manufacturer has supplied a customer with a number of game machines, each including a memory chip which stores a certain game- There is a risk that when the game machine manufacturer produces a new game or an updated version of an old game, the customer will buy one copy of the new game (e.g. one memory chip), copy that chip, and then use the copies to update each its existing machines.

Furthermore, the first game machine manufacturer faces the risk that one of its competitors (a second game manufacturer) will reverse engineer the game machines, and develop a new game which runs on the first game manufacturer's machines. The customer could then install this game by replacing the memory chips in its existing machines by memory chips from the second manufacturer. In this way the first game machine manufacturer will lose the advantage it deserves from having developed and marketed the game machines. The first game manufacturer thus has an incentive to make it hard for a second game manufacturer to reverse engineer its game machines, Furthermore, if game machines are difficult to reverse engineer, then there is less risk that a second game manufacturer will be able to analyse any innovatiori developed by the first game manufacturer and implemented in its game machines. Also, if a game machine is difficult to reverse engineer, then there is less risk that a game supplied by the first manufacturer will be tampered with (modified), for example to evade game machine law.

The present invention seeks to provide a new and useful game machine, and especially (though not exclusively) a game machine which is a gaming machine. The invention further seeks to provide a new and useful method and tool for designing or testing game machine software- In its most general terms, the invention proposes that the memory devices, input devices, output devices and processor of a game machine are mediated through a coordinator unit. From the point of view of the coordinator unit, any or all of the memory devices, input/output devices and processor (and indeed any other hardware which is present) are separate resources, which can operate substantially without knowledge of the others, so that the demands of one resource do not overload the capacities of another. The coordinator unit 6 may provide a useful base from which to organise security operations (e. g. to inhibit reverse engineering). Furthermore, if a writer game software can use the coordinator unit to interact with the resources of the game machine, he or she may be able to design new game software without the need for a separate emulator.

In a first aspect the invention provides a game machine comprising:

a game machine having a plurality of resources including a payment receiving means, a memory for storing game software and a processor unit for processing the game software; and a coordinator unit for interfacing with the resources and for controlling data passing between the resources.

Preferably there is further provided a data bus connecting the processor unit and the coordinator unit, a system clock for determining the operation of the processor unit and controller means for ensuring that the coordinator -unit only accesses the data bus during a portion of each clock cycle. The important point is that the coordinator unit only accesses the data bus at times at which this accessing does not affect the processor unit. This enables the coordinator unit to access the data bus during the same clock cycle as the processor unit without interfering with the operation of the 7 processor unit. It enables efficient handling of data and is discussed in more detail later in the description. Preferably the processor unit only accesses the data bus in a first portion of each cycle and the coordinator unit only accesses the data bus in a second portion of each cycle. The above aspect of the invention and above preferred features may be combined with any of the further aspects of the invention which are discussed below.

In a second aspect the invention provides a game machine comprising: one or more information output devices; a payment receiviag mechanism; a memory for storing game software; a processor unit for processing the game software and generating operating data for operating the output devices; and a coordinator unit for receiving the operating data, and generating, based on the operating data and information about the requirements of the output devices, operating instructions for transmission to the output devices to control the output devices. The information about the requirements of the output devices may include data defining the refresh requirements of the output devices. For example, if the operating data indicates that a particular output device 8 (e,g. light) is to be illuminated during a certain period, the coordinator unit may during this period generate and transmit to the light operating instructions at a rate which is at least the refresh rate of the output device. Thus, the processing unit can be devoted to running the game software, without having also to perform "housekeeping" operations.

Preferably, the processor unit writes the operating data (e.g. via the controller unit) to a memory which the coordinator unit can read to generate the operating instructions, That is, the coordinator receives the operating data first from the processor (on its way to the memory) and then a second time from the memory.

The operating data may include timing data defining the timing according to which the output devices ahould be controlled, e.g- stating that a particular light or set of lights is to be illuminated at a particular moment. The coordinator unit may incorporate this information in the operating instructions which it generates. In this way the time precision with which the lights are illuminated can be maintained, even if at that moment the processor unit is busy processing other portions of the game software.

The coordinator unit may transmit operating instructions to a plurality of output device along a respective channel for each output device. The signals sent along each channel may he in a serial format, but 9 the times at which signals are transmitted along different channels are coordinated, for example to produce a simultaneous illumination of two or 'more lights, Since the processor is separate from the coordinator unit, the invention makes it possible to control the output devices in real time even it the processor unit is unable to generate operating instructions in real time. That is, the invention permits a buffering effect.

The transmission rate of the operating instructions may be selected to be an odd multiple (or even a prime multiple) of the clock frequency, to minimise harmonics. such harmonics could corrupt the operating signals so that precision of the timing of the operation of the output devices is reduced.

Preferably, the coordinator unit is sensitive to the waveform of the electrical power supply to the game machine due, and optionally also to perturbations in the power supply waveform. The coordinator unit may for example he arranged to send the operating instructions to the output devices in dependence on (e.g. in synchrony with a portion of) the waveform of the power supply. For example, the coordinator unit may synchronise the operating instructions to parts of the power waveform to ensure that the output device(s) receive the operating instructions when the power they receive is at a known adequate level.

Preferably, the coordinator transmits output instructions in bursts (referred to here as frames). 8ach frame many contain one or more operating instructions to each of the output devices. The frames are preferably slightly shorter than the period of the power supply, and synchronised with it. The coordinator unit may be arranged to react to any variations in the regularity of the mains supply, by varying the interval of the frames. This may for example be a "flywheel synchronisation" in which a sufficiently great perturbation in the power supply waveform leads to a frame being missed for a given cycle of the power supply.

In the above statement of the first aspect of the invention, and throughout this document, the term "payment receiving device" will be used to include a coin receiving device (e.g. having a coin authenticating function), a banknote receiving device, a token receiving device which receives a token representing money, or a credit card reading device. In fact, in includes any mechanism by which the user can pay to use a game, or by which a signal is transmitted to the game machine to indicate that the user has paid to use the game.

In a third aspect, the present invention provides a game machine comprising.

one or more information input devices; a payment receiving mechanism; a memory for storing game software; a processor unit for processing the game software; and a coordinator unit for receiving signals from the input devices, processing the signals to generate data based on requirements of the processor unit, and making the data available to the processor.

The input device(s) may be one or more push buttons operable by the user. The information input devices preferably transmit the signals to the coordinator, which processes it into data, and stores the data in memory. At an appropriate moment, for example when the coordinator determines that the processor unit is not occupied, or in response to a signal from the processor unit, the data is transferred from the memory to the processor unit (e.g. via the coordinator unit). Thus, the coordinator unit permits a buffering of input information, so that when data is input the processing of game software by the processor is not interrupted.

The coordinator data preferably pre-processes the information to make it easier for the processor to handle. For example, the processing may include generating vector arrays in a predefined format, for storage in volatile memory.

In a fourth aspect, the invention provides a game machine comprising:

payment receiving means (a "resource"); a memory for storing game software (another "resource,,); a processor unit for processing the game software (another "resource"); and a coordinator unit capable of interfacing with the processor unit, and mediating between the resources, the coordinator being arranged to vary the mediation between the resources.

For example, the coordinator unit might be used (e.g. when the games machine is booted) to test the integrity of the resources, by for example connecting the processor (or another resource) to a certain section of memory and controlling the processor to process the data in that section of memory, the coordinator verifying that the processor processes it correctly.

The coordinator unit is particularly useful when game software is being developed. In this case, the writer of the game software is preferably able to transmit instructions to the coordinator to control how the coordinator mediates between the resources.

For example, the writer may initially control the coordinator to ignore the processor (e.g. turn it off) and divert all signals which would normally he sent to the processor out of the game machine to the writer's PC (or other computer). The coordinator is similarly configured to treat signals received from the PC as if they had come from the processor. The processor of the PC 13 can thus play the role of the processor of the game machine. The writer can test game software by causing the PC to run game software (e.g, stored in the memory of the game machine and made available to the processor of the PC via the coordinator unit, or alternatively stored in the memory of the PC), and checking whether it interacts correctly with other resources of the game machine, Any bugs can be identified, and since the processing by the processor of the PC can be analysed in detail, the reason for the bugs can be easily identified, and the bug corrected.

If the writer arranges for the memory of the game machine to be a writable memory, the writer may write the software directly into the memory of the game machine (i.e. arranging for the coordinator unit to receive program data from the PC and transfer it to the internal memory of the game machine), Thus, the necessity for a separate download is avoided. The game software stored in the memory of the game machine can then be tested as described above using the writer's PC to play the role of the processor of the game machine.

When the program has been completed, the writer can instruct the coordinator unit to turn on the processor, and cause the processor to process the program data (i.e. taking over f rom the processor of the PC). Even while the game machine is processing the software, the writer may still be able to influence the processing by transmitting 14 signals to the coordinator unit; for example the writer may indicate starting conditions, or instruct the game machine to function as if a payment had been made, e.g. by writing data into a location of the memory which indicates that payment has been made.

If the processing of the game software is successful, the writer can control the coordinator unit to transmit the program data in the memory out of the computer, so that the program data can then be stored in a read-only memory.

The writable memory chip(s) in the game machine can then be at least partially he replaced by the read-only chip (s) If necessary the writer can control the coordinator unit to convert it from handling the replaced writable memory to handling the read-only memory, so that the processor receives substantially identical input from the coordinator unit irrespective of whether the memory is read-only or writable.

In other words, from the point of view of the coordinator unit, the processor of the PC is a resource (like the processor inside the game machine itself), and the two sets of memory are also each a resource, one of which replaces the other. The coordinator unit mediates between all the resources, and the mediation can be varied so that one resource substitutes for a second resource without the other resources being affected.

This method of testing software constitutes a fifth aspect of the invention, which may be expressed as a method of testing game software comprising:

providing two or more first resources, including a processor unit for processing game software (e.g. a processor of a PC) and a memory for storing game software (a writable memory), and a coordinator for mediating between the first resources; causing the game software to be processed by the first resources mediated by the coordinator, and investigating the processing; controlling the coordinator to treat one additional resource (e.g. an additional processor unit, such as a processor suitable for installation in a game machine, or a read-only memory) in place of one of the first resources; and causing the game software to be processed again.

Preferably, the method is carried out when the processor is connected to at least one output device via the coordinator- In a sixth aspect, the invention provides a tool for writing game software, the tool comprising in combination:

a processor for processing game software and suitable for installation in a game machine (a first resource), a memory for storing game software (another first resource), and a coordinator unit capable of mediating between the first resources; the coordinator being arranged in response to an external signal to vary the mediation between the resources, for example to treat one additional resource (e.g. an additional processor unit, such as a processor suitable for installation in a game machine, or a writable memory) in place of one of the f irst resources.

The tool may for example be used in combination with a known computer terminal (and optionally at least one known output device operated by the coordinator unit) for testing game software, as discussed above.

In all aspects of the invention described above, each of the resources which are coordinated by the coordinator unit may he essentially unaware of the others (i.e. operate in a way which is substantially independent of the details of the operation of the other memory devices). Preferably, the coordinator unit mediates between the resources in such a way that its interaction with any one of them does not depend upon whether the coordinator unit is also interacting with any of the others. This may be achieved, for example, by exploiting knowledge about the timing of the interactions between the coordinator unit and the resources. For example, if it is known that the first processor unit does not exchange information with the coordinator unit during certain sections of the clock cycle, the interaction 17 between the coordinator unit and the other resources may be arranged to take place (e.g. predominantly) during those sections of the clock cycle.

In a seventh aspect the invention provides a game machine comprising:

a payment receiving mechanism; a memory for storing game software; a first processor for processing the game software; a second processor which stores a key; and a coordination unit for receiving the key from the second processor and being capable of verifying the key and controlling the processing of the game software by the first processor, the coordination unit only controlling the first processor to process the game software after it has verified the key.

The verification of the key by the coordinator unit can be by the coordinator unit storing the key, and matching the key received from the second processirig unit with its own stored key. we will call this "first level security". Preferably, the key is a string at least 10 byte5 long, and may be at least 30 bytes long.

Alternatively, the coordinator unit may contain an algorithm for generating a key, preferably a secret algorithm. For example, it may contain a secret algorithm for generating a key from the game software, e. g. reacting to a trigger signal from the second processor. The trigger signal may, for example, tell the coordinator 18 unit to use a section of the game software (e.g. a section specified by the trigger signal) in the algorithm- For example, the algorithm might be working out a sum of the bytes in the section of the game software. if the coordinator unit finds that the key it generates does not match the key transmitted by the second processor, the coordinator unit does not allow the first processor to process the game software. This is referred to here are the "second" level of security. The two levels of security are optionally combinable.

The second processor should preferably be made difficult to copy, and it should preferably send its key to the coordinator unit in a format which is hard to a third party to intercept and copy (e.g. at a high baud rate, and mixed with other data). The key is never transmitted by the coordinator unit, and, in cases when the second level of security is employed, the secret algorithm is preferably never transmitted.

Normally, when a game machine held by a customer is updated, the customer is sent one or more memory chips containing the new game and a corresponding second processor. Even it the customer can copy the memory chip(s), he or she cannot copy the second processor or extract f rom it the key, so that the copies of the memory chips cannot be used (i.e. without copy of the second processor, a game machine cannot generate a key for transmission to the coordinator unit which will cause the 19 coordinator unit to permit processing the game software). Thus, the first and second levels of security very much reduce the risk of game software being copied and used on other game machines from the same manufacturer.

if the customer was capable of extracting the key sent f rom the second processor, or indeed copying the second processor, this would make it possible in principle for him to run the new game on each of his existing game machines supplied with identical coordinator units. However, the second level of security prevents the customer from installing in the game machine a game developed by a second game machine manufacturer. This is because since the second game manufacturer does not know the secret algorithm, they cannot generate from their own game software a key which the coordinator unit will accept to allow the processor to run that game software.

Furthermore, tampering with the game software would normally change the key which the coordinator unit generates from the game software, and so make the software unusable.

Preferably, the second processor stores further information which is necessary for the first processor to process the game software. Vor example the second processor may store information which is required to set the first processor into a starting configuration for processing the game software. Thus, the coordinator unit, upon verifying the key, may control the second processor to transmit this data to the first processor (e.g. via the coordinator unit) as part of the boot up of the game.

if the verification of the key by the coordinator unit fails, the coordinator unit may permit the second processor to try again (e.g. retransmit the trigger signal and/or key), for example after a predetermined time interval.

An optional "third" level of security, freely combinable with the first and/or second levels of security, proposes arranging for the second processor to send the coordinator unit an address of a section of -volatile memory containing information required by the processor to process the game software. Preferably the second processor transfers to that section of memory (e.g. via the coordinator unit) data (e.g. vector program) required by the processor to process the game software. The coordinator unit remembers the address in the memory, and enables t I he processor to access the data stored there as and when required. Since a third party does not know the address of the section of memory, and since the address is never transmitted except between the second processor and the coordinator unit (both of which may be custom chips), it is almost impossible for the third party to determine the location of the section of memory, and thus gain access to the vital data stored there.

This technique, in which no key as such is required, constitutes an independent eighth aspect of the invention, according to which the invention provides a game machine comprising:

a payment receiving mechanism; a memory for storing game software; a first processor for processing the game software; a second processor which stores a memory location containing data required by the f irst processor to process the game software (e.g. the second processor may have stored the data to that location); and a coordination unit for receiving the memory location from the second processor and making available to the first processor data stored in the memory location.

As described, all three levels of security make reverse engineering of the game machine more difficult, and thus may address the problems of tampering with the game software and analysing innovations in its operation.

Although all the aspects of the invention above have been described in relation to a game machine in general, some or all are particularly valuable if the game machine is a gaming machine (e.g. a game machine further comprising money dispensing means which are controlled (e.g. via the coordinator unit) by the processor) For example, in the case of agaming machine the discrepancy between the processing power of the 22 processor of the gaming machine and the computing power of the PC on which the gaming software is developed is especially great, and therefore the first to sixth aspects of the invention, which have particular relevance to overloading of a processor and to designing of game software using a processor of higher power, are especially useful in the case that the game machine is a gaming machine and the game software is gaming software. The seventh and eighth aspects of the invention are also particularly relevant to gaming machines, to counter known competitive practices in that industry, and to prevent the evasion of the strict legal requirements relating to gaming machines by tampering with gaming software.

The above aspects of the invention can be combined with each other and the necessary arrangement will be apparent to a person skilled in the art. Thus, for example, the second aspect of the invention can be combined with the third and seventh aspects of the invention to provide a game machine in which the coordinator unit controls operation of the output devices, handles input signals from the input devices and administers a security system.

Further preferred features and aspects of the invention can be found in the claims.

Whilst the coordinator unit has been discussed in 23 relation to a game machine it is also applicable to other electronic apparatus having a processor and a memory.

Embodiments of the invention will now be described, for the sake of example only, with reference to the accompanying figures in which:

Figure I shows a schematically a game machine according to the invention.

Figure 2 illustrates schematically an arrangement according to the invention for designing game software.

Figure 3 illustrates time slicing of a clock cycle so that both a processor unit and a coordination unit can access a shared data bus in the same cycle.

Referring to Fig. 1, a game machine according to the present invention comprises a number of circuits mounted on a motherboard. These include a main processor unit I (such au a Hitachi 32 bit microprocessor from the family known as Super IIWI). Also present is a coordinator unit 3 (also known as a "gate,,) The motherhoard also carries a second processor 7 and a memory 8 (which in practice may include a number of separate memory chips of conventional form). in the game machine as sold as a commercial product, the memory is normally composed of a read-only memory and a volatile memory, but at certain momenta of game design the memory may include in place of the read-only memory (e.g. nonvolatile) writable memory.

The coordinator unit 3 may in principle one or more physical chips, but usually it will be a single custom chip. The coordinator unit 3 is a physically separate unit from the main processor 1 and the second processor 7 (i.e. neglecting their mutual connections to the motherboard). Although the coordinator unit 3 may -in principle contain a certain amount of volatile memory (which is therefore a part of the game machine), it is physically separate from the memory B. The coordinator unit 3 is in two way communication with the main processor unit 1, the second processor unit 2 and the memory 8 (of course, it need only be in one way communication with any read-only components of the memory). The main processor unit 1, second memory 7 and memory 8 are not in communication with each other except via the coordinator unit.

The mothez-board is connected via the coordinator unit 3 to a number of off -board devices. There is a mechanism ii for receiving money, counting money, and dispensing money. There is at least one (and normally more than one) device 12 for inputting information from the user. The device 12 may for example be a push button.

The gaming device also includes one or more (normally many) devices 13 for outputting information. These may include lights which can be made to flash, sounders for generating sound, or even a video screen.

The coordinator unit may address the output devices 13 through multiple channels, sending signals which are coordinated in time. For example, there may be one channel for each output device, or the output devices may in groups, each group receiving signals via a respective channel from the coordinator unit.

The gaming machine optionally further includes a connector 15 for receiving/ transmit t ing signals out of the game machine, f or example to a PC connected to the connector 15. This connector may be useful during the design of game software (as explained in detail below with reference to Fig. 2), or even once the game machine is in use for maintenance tasks on the game machine, for example for transmitting (e.g. statistical) information out of the game machine to verify that the game machine is functioning correctly.

In use, the processor I processes gaming software retrieved f rom the memory a, to allow the user to play a gambling game. The processor 1 does not itself generate input/output commands f or the output devices 13; instead it generates operating data indicative of the desired behaviour of the output device and stores the operating data in the memory 8 via the coordinator unit 3. The coordinator unit 3 reads the operating data f rom the memory and, taking into account the driving requirements of the output devices 12, generates and transmits output instructions to the output devices 12 which cause the 26 output devices 12 to perform the behaviour indicated by the operating data- For example, the operating instructions are at at least the refresh rate of the output devices.

When a user of the gaming machine inputs information using the information input device(s) 12, the input device(s) 12 transmit signals to the coordinator 3, which pre-procesoes them, for example to reduce or eliminate features of the signals which are dependent on the constitution of the input device rather than upon the intentions of the user (and which the processor I does not wish to see), or to sort the information in the signals into a format (e.g. vector format) which is particularly suited to input to the processor 1. The coordinator 7 stores the result in the memory 8, for subsequent access by the processor 1.

The secondary processor ? stores information required by the processor 1 to process the game software (for example defining the set-up configuration of the processor 1), and also a key (a string). A copy of the key is stored in the coordinator 7.

When the game machine is turned on, the key is transmitted from the second processor 7 to the coordinator 3, which verifies it.

An alternative or additional security level is provided by the second processor 7, after the game machine is turned on (and possibly in response to a 27 signal from the coordinator 3) sending a trigger to the coordinator 3- The coordinator 3 then performs an algorithm using data it reads from the memory 8, and generates a key for itself. The second processor sends a key to the coordinator 3 (either before or after the algorithm is run) and the coordinator 3 verifies that the keys are the same (i.e. exactly the same, or, optionally, the same within a predefined tolerance including trivial transfo=ations).

In either security level, if the verification is successful, the coordinator 3 allows the second processor 7 to configure the main processor 1.

A third possible security provision is for the second processor 7 to load data required by the processor I (e.g. set-up data) into a location in the memory 8 and tell the coordinator 3 the location, so that the coordinator 3 can thereafter allow the processor 1 to access the location (without the processor 1 knowing the location), The Fig. 2 shows how the motherboard described in relation to Fig. I can be used as a tool to design or test game software. The motherboard and components in Fig. 2 are identical to those of Fig. 1. They are connected (e.g. via a connector 15 which is not shown) to an external PC 20. Initially, the memory 6 may be RAM.

The software designer uses the PC 20 to input game software via the coordinator 3 to the memory S. To test 28 the software, the coordinator 3 is configured to turn the processor 1 off, treat the processor of the PC 20 as the main processor 1, and run the software in the memory by signalling back and forth to the PC 20. Any hugs in the software can be picked up by analysing in detail the processing by the PC processor.

Although not shown, the tool may further contain one or more of a money receiving and dispensing mechanism and information input/output devices(s) eguivalent to those of Fig. I and in communication with the coordinator 3. Alternatively, any of these may be simulated by the PC (with the coordinator 3 signalling back and forth to the PC instead).

When the software is debugged, the coordinator 3 can be controlled to turn on the main processor 1, and run the software again using the processor 1 in place of the processor of the PC.

If no further problems are detected, the coordinator unit is controlled to transmit the game software out of the memory 8 to be stored read-only chip(s). Alternatively, the writer may prepare read-only memory chips from a copy of the game software generated outside the game machine during the writing process. The read only chip(s) are installed in the game machine, replacing at least part of the writable memory 8, and the coordinator 3 is reconfigured, so that this replacement causes no change in the signals received by the 29 processors 1 and 7.

The motherboard thus functions as a tool for generating and testing software data.

The capacity of the coordinator unit 3 for flexible mediation between the resources is -useful even in the game machine of Fig. 1, since it cari be used for testing the resources of the game machine (e.g. at setup) to ensure that they are operating correctly, e.g by connecting any of the resources (e.g. the processor 1) to test software stored in the memory 8 and verifying that the resource operates correctly in response to the test software.

A further embodiment of the invention will now be described in detail. It is hereafter referred to as the EPOCH system.

SECTION 1: SYSTEM INTRODUCTION

11.."

t SYSTEM OVERVIEW The EPOCH system is designed for use in the garriling indusrr\-- ft sets neW standards in design inteeration, innovation and flexibility. The, design makes possible a single base unit that can perform Ll the tasks that thegaming industry requires from simple low tech. slot machines to the very highest tech- multimedia gaming consoles and all at low unit cost The systern incorporates the highest technical state of the arT desip f6atures making it the most Integrated and powerfUl 2aming computer cLuTentiv available- The system is designed by and copyright of DJf Design & Technology Limited and is licensed to Maygay Machines Limited- Many of its features are proprietary and give a definite technological advantage and lead over all other systems currentlv in use within the gaming industrv. Above all this 'EPOCH' has been designed to be themost reliable and easiest system to manufacture and operate- The almost infinitely adaptable Input and output structure allows for a new and far more efficient low cost approach to customer and engineering support.

The basic features are as fbllo%1,-s-,_ 32 bit primary microprocessor, 16 bit data bus optimised for'C' programming64 KBqytes of on-board battery backed high speed static RAMUp to 4 Nffiytes of stand alone socketed game EPROM_ Expandable to 8. NIBytes via adapterUp to 2 USYTES of dedicated socketed sound data EPROM. 64 KbIts of socketed F-EPROA 8 channel stereo ADPCN4/PCM sound system. Fully software controlled individual volume and pan settings. 8 -.1- 8 watt RMS stereo power amplifiersReal time clock with leap year and surnmer time support3 levels of security via dedicated micro and ASIC gate array provide protection from game copying, reverse engineering and multi user interchange. Power off door monitoring of up to 6 switch inputs. Power off external alarm triggers via 2 dedicated outputs. Inffared TX and RX communications capabilities4 channels of on-board DMA support all types of transfers8 channels of direct 10 bit precision analog to digital inputs. 8 bit TTL level direct access YO port with individual direction controls. On-board power rail monitoring circuits with brown-out detect. 3 independent hardware implemented watchdogs. 2 full RS2:32 serial channels supporting baud rates up to.38,400 bps. One of the serial channels also supports the data power connector for industry standard data logging add-ons- The other channel also supports RS2332 and TTL voltage level interfacing. Mull) speed 12C serial interface, Can control as many a$ 100 intelligent master;slave off-board sub-systems. Allowing for the connection of such things as, data loggers, expansion communications modules or even simply distributed game processing. On-board 16 option switches with direct write to RAMSupporu up to 512 fully hardware controlled lamps with direct read from RAM Six independent flash rate controllers, individual phase select, and individual dimmingOverload and lamp failure detection optional. Lamps are genlocked to the power line to give absolutely flicker free outpuL Supports up to 512 fully hardware controlled LED outputs with direct read from RAM- Six independent flash rate controllers, -individual phase select, and individual Inc, dimm' Supports up to 4096 direct inputs fully controlled by hardware with direct WrIte to RAM. Lnputs are read into RAM at up to 6,400/sec. All 'inputs have the ability to generaie individual interrupts under software control with selectable active level. Supports up to 4096 direct outputs fully controlled by hardware with direct read from RAM. Outputs are re&eshed from RAM at up to 6,400/sec. Current detection optional on any output. Any group of outputs may be dedicated to reet drive support givinge the potential for an extremely large number of units.

Basic Features conrd.

On-board support for configurable matrix display devices via dedicated c6nnector.

Two hardware controllcd display planes supported- All dot points have 4 levels Of independent aad 80 levels of collective brightness control.

LEDs moruitors for all power rails, reset activity and security warning Full diagnostic port for bardware manufacture and semice.

Full feawred built-in Emulator with hardware breakpoint and single step functions.

Connects directly to a standard PC via built-in.coanector- The EPOCH design comprises a base motherboard that incorporates the Power SUPPly.-The units major expansion point is a very flexible multi chwmel chairuing 1/0 link connector.

The Link Connector.

This unique fearue 93yes the rEPOCIT system its great YO fl&xibilitY and low cost This corin=or is simply a 10 pin DU, DD header that is routed to the heart of the design, the ASIC gate army. The basic principle of this interface is to provide a high speed multi element interchange interface for extemal YO -devices. The interface nins at 571KHz and can fully service all extemal resources in 128uS- The main system processor has no connectiou with this process, all awufers are peiforrrii-d by the ASIC and data is read or written directly to/from the main battery backed Static RANL There is no limitation on the connectivity of the external resources, each linked ilier-face simply has a link to the next. Any linked interfacc can have any combination of inputs, outputs, LEDs or lamps, These linked interfaces are very -simple in design and need no local intelligence as the main board controls all data sequencing- I., I The System Processors.

The EPOCH design has three microprocessors. At its heart is a member of the latest Hitachi 32 bit ml-CrOprOM50r family knovvri as Super'K the device used is the HD6413002FN16- The device is clocked at 16,\4Hz, as can be seen from the part number. This device has a 32 bit pro=sirig core operatin.- over an extemal 16 bit data interface. The device has an address range of 16 NMYTES. The processor interfaces directly to the ASIC and does not directly control either the on or off board resources.

The second processor controls the boot up sequence, system configuration and security tasks. The device is a member of the low cost p[C processor range from Microchip- Every game that runs on the 'EPOCIT system has it's own PIC which accompanies the game EPROMS. -Mis device can directly control and configure all system level interfaces including EPROM sizing.

Another of it's tasks is board level security. As mentioned previously there are three levels of protection. The first is to make it possible for the system to be customer specific so that one manufacturers garne will not be able run on a different manufacturers system- The second makes illegal changes to the game EPROM data areas impossible by using multi direction checksums and panem checks. The third is to protect the system &om reverse engineering, there are several methods employed which make the task of illegal system interrogation practically impossible. These methods are described more fully ul s=don 3, but fall information is not within the scope of this document and is provided under separate NDA.

The third processor provides all rea time clock functions and power off security supporL The aevice is another mtmber of the low cost PIC processor range ftom Microchip. The first of it's tasks is to keep a very comprehensive system real time clock that provides secs/hours/weekdays/days/months/years and adjusts for leap years. It's second task is- to provide application security such as door monitoring and alarm triggering when the power is turned offUp to $L-X switches can be monitored and two output devices triggered. This device is socketed to allow custom security requirements to be implemented.

General.

The EPOCIT system has a relatively small footprint of 6.725" x 5"_ The design is targeted to comply With the low voltage and EMC directives for full CE compliance- The component count is very low. This fact and the diagnostic interface capabilities makes servicing very easy- There are no links to be set as configuzation -is all performed via softivare at boot time. All software is written in V Ming one of the compilers available from an Hitachi software vendor. The ides, -t a f I system prov as standard, -in every ual ull featured in-circuir emulator. This feature -is further explained iti sect-Ion 2 and its full technical specification can be'found in section 3-

The basic structure of the EPOCH system makes it possible to step up with ea5e: to the n6xt seneratlon of super processors such as the SR range from Hitachi as used in Sega games consoles if super performance is required, This step up will gl%,e full 32 bit daWaddress buses as well as modular memory extensions.

Cost.

The ZPOCK system has been desiped to deliver the maximum performance for the lowest possible cost- As already stated this is achieved in several key ways, high integration, low component CoUnt and flexible 1/0 resources, This makes possible very low unit costs. Each System comprises the, main system board and power supply unit plus general purpose 1/0 modules that connect to the linked 1/0 resource- EMULATOR INTERFACE BO RD Ali'development software and game debugging is carried out on a standard PC. The EPOCH emulator interface i all that is required to enable the complete in-cirQuit emulation functions designed into the EPOCH system to be acomed- This interface is plugged irito a normal PC IS A slot and is linked to the EPOCH system by a standard RJ45 8 way cable that connects to a dedicated plug on the system board- This interface allows data. to be transferred between the PC and the system at a speed of 120KBytes/sec.

Unlike other ICE (1-n-circuit emulator) devices the one designed into the EPOCH can also eavesd-rop on memory and gate-army registers in rcal time. It is possible to continuously monitor any are--(s) of memory at the PC and see target programs accesses of them wiEhout interrupting the target in any way- Not only is it possible to mon'itor but also any location can be %%.-ntten to withour causing the target to be halted- TI-Lis real time interaction makes powerful functions such g as interactive source de-bugging, prog-rarn, monitoring and performance analysis easy- For a full description ofall the functions provided please refer to section three of this document.

SECTION 2: DETAILED SYSTEM OVERVIEW Follows are detailed feartire descriptions for the design-

The linked 1/0 r=urces laznp:s, LEDs, inputs, outputs, option switches and display port operate via a process called clirect RAm write/read. This is a function operated entirely by the ASIC and requires no support from any of the microprocessors other than the initial enabling of It's operation. Data is read and written to the static RAM by a sequence of burst bus mastering this means that the required access bandwidth to support the entire process. (which is approx. 1.21VMytes/sec) occupies less than 4% of the total memory access time available- The various uses of tWs process are given in each relevant sub section below.

1. PRIMARY MICROPROCESSOR.

The Flitachi f-ID6413002FN16 sets the master system clock speed of 16NIHz and is connected to the ASIC via a 16 bit data bus. Most of ies wxdc range of integrated features are used in the EPOCH design and are briefly explained (for a full description of these please refer to Hitach.i technical manual) in the various sub sections that follow- 'Me processor is enabled after the boot microprocessor has successfully configured the system for the game that -is to be run. The data and address buses are dciven to the main AStC and the vast majonity of the resources are handled via the ASIC. With this configgization maximurn memory pedon- nance can be reallsed. All linked I/Os are directly read or vaitten to the battery backed static RAN4 and this is done by bus master block accesses some of which, where possible, are hidden from the primary microprocessor to rnairitain ma;ximum CPU performance. In general the worst case loss of CPU access time will not exceed 4% of the total available. It is the primary microprocessor that initiates all DNIA actions between resources. The buses of the microprocessor are time sliced and m=ered bv the ASI( to Further increase available access time. Some functions of the microprocessor are controlled by the security microprocessor directly or via set-ups within the AS[C-deterynined during the boot period.

Resources that are directly driven from the microprocessor are identified in their paAlcular description'sub sections below.

2. STATIC MEMORY.

There are 64 KBytes of on-board static battery backed memory configured. as 32 KBytes x 16 bits. Accesses can be made as b%ies, words or double words. The access ofthis memory by the primary microprocessor takes 33 cycles, 187-SnS or 10.5 1,Mytes/sec, but ASIC accesses are single cycle, 62.5nS or 3 _2;\/Myte5,:sec_ As all linked 1/0 resources have their data sourced frorr, or wTitten to tNs memorv block the fast access possible via direct ASIC connection to the mernorv is one of the,%x7vs chat the potential access overhead is minimised to less than 4% (NB. the A-SIC accesses dam constantly at 1_2N4Byte&/sec) of the total available- The whole memory is battery backed and has two power interlocks to prevent cormptiors due to power fluctuation5.

3. GAME EPROM.

There are four game EPROLM sockets on the system. nese can be configured to be either 1/2/4/8 Mbit devices- The comfi-cruration is done by the boot microprocessor there are no links on the system that need to be set. Fuz-ther memory can be added up to a maximum of 8 lvcs via a special adaptor fitted -into the normal EPROM sockets which is configured by the ASIC. The devices are gmuped as tvvo 16 bit areas- The F-PRONis used are: standard access types, 120nS or better. This means that a 3 cycle access can be performed by the ASIC (the RPROM space is indirect to the pn-marv microprocessor) giving a data rate of approximately 10.6 MBytes/smThe EPROM space is tested by the boot microprocessor dun-no, power up and only when these tests have passed is the primary microprocessor allowed to -start. Other operations affecting the EPROM space are part of the security systems and are not discussed here- The EPROMs are replaced %ki[h SRAMs devices when operated in emulator mode. During this mode the sockets signals are reconfigured (see the emulator description later in this section)Another emulatoc mode allo%%s the lower EPROM socket pair to be operated as norrual and the upper pair to be configured for the SRAM. This mode allows several advantages. firstly allos;,the operation of on board standard libraries duringdevelopment and secondly allows the use of high level monitoring during emulation.

4. SOUND EPROM.

There are two sound EPROM sockets on the system- These can be configured to be either 1/2/4/8 Kbt't devices. The configiwarion is done by the boot microprocessor. The sound device -is connected directly to these SocketsMemory decode is performed by the ASIC. Data in these, EPROINts can be read back Into the main memory resources of the primary microprocessor. The EPRO'Nis used are standard access types ' 120nS or better. These devices can be configured for operation as SRAM's- This allo%vs PCM sound data to be dov-mlo-aded in the same way as game program data without the need for programing EPROM's. The download process is fu,,Y controlled by the ASIC and does not need the primary processor to be enabled.

5. EEPROM.

This is provided by a socket that accepts a 64 Kbit EEPROM of the rA!)e 24C65 ftom Nficrcchi-p and vaxious other veadors- This giVe5 long term parameter and game configuration storage and can be used to hold site relevant data as required by some applications. The device is direcTjy connected to the ASIC which provides all the necessary I2C interface functions. This 12C port is also passed off-board via the emulator connector for use with external devices, 6. SOUND SYSTEM.

This is provided by a Yamaha 8 charmel ADPCM/PCM sound processor. Thisdevice can gonerate up to 8 independent channels of audio that bave individual stereo Voltime/pan controlsAll channels can be looped and have a 255 level pitch control. The summed stereo audio is routed thiough a software controlled master volume control to the power amplifiers via a high perfoanance audio JDAC. The clock source for this device is from the combination clock generator that also provides all 6 system clock frequencies- The intearface control to this device is actioned by the ASIC.

7. POWER AMPLIFIERS.

ne!EPOCR system is fidly stereo capable. The audio is dziven out via txvo high quality povirer amplifiers. The continuous power output for both channels is 8 watts RMS. The audio SN'Slem is designed for high signal to noise operation, all analog audio circuitry is separated fro m the logic and power switching circUiES- 8. REAL TIME CLOCK.

Th6 real time functions are generated &om the third microproce.5:sor that is also responsible for power off sectirity functions. This device directly links to the primary microprocessor and provides all time counters including day of the week and full year (year 2000 supported). It also automatically adjusts for leap years.

9. SECURITY.

There are three levels of secun-ty provided by the second single chip preprogrammed microprocessor- This microprocessor is socketed and is partly user generated to be unique to every garne. The first level of security is provided to make it possible for the system to be operated by different manufacturers while maintaining total intellectual protection.. one manufactures game wil I be locked out from working on any other- This is accomplished by an ASIC signature and lock that must be opened by the microprocessor at boot tirrie.

Security contd.

The second level provides protection from illegal EPROM tampering- During boot time the EPROZ-4 space is configured then checked u-sing several different algorithms against JQjoVM values stored in the secondmicroprocessor- If any of these fall the systern does not boot and a warning is indicated- The d2ird level provides protection against attempted reverse engineering- This is accomplished by the use of three different techniques- The action of these techrdques ma-kes it virtually imp6ssible to gairL knowledge of the game or system operation by any intervention methods. While no technique can,guarantee to give 100% protection those techniques employed by the SPOCH design are ma.nv times more effective than any that current industry designs employ.

10. POWER OHSECUR(TY.

The TPOCI? design has the facility to monitor up to six switch inputs even when the power is removed from the board, This is a task pt-- fforined by the third pre-progranimed microprocessor. Any mordtored input can have a timed response and HI debou-nce- There are two trigger outputs that can be actioned by any single or combination of inputs. These triggeT Outputs can be connected to external sounders or signaling devices as required- The third processor is also socketed so that specific power off moniton-nrequirements can be easily implemented by changing the device_ 11. INFRARED INTERFACE.

A further function of the third microprocessor is to provide a means for driving a bi-directional infrared communications channel. This can be used for remote data logging and even access securirv. The structure for the interface is not fixed and can be tailored to suite a particular manufacturers requirement_ 12. DIRE CT MEMORY ACCESS.

Up to four channels of DMA are provided by the primary microprocessor. This allows unmonitored transfer of data from any area of memory to any other- The speed of the- transfer depends on the source and datination memory types, a Wical transfer from EPROM to static RAMu-ill del Liver greater than 8 NOytes/sec. There are many modes of DMA operation available including blocic, reload, demand, short and long. AR DVA channels are fully controlled by game software- The linked 110 resources are independent of the DMA structure.

13. ANALOG DIGITAL INPUTS.

The'EPOCIT design has a toml of eight channels of 10 bit precision analog to digital conversion inputs all provided by the primary rnicro processor. Seven of these channels are available as direct inputs on the special f/0 connector. The remain- g channel is used to providere ot, in rn voltage sensing over the 1/0 link interface- The conversion time for each channel is 8.4uS and can be operated in two main modes, single or se-umed- The ADC intefface has a sarnple and hold input for reliable conversion. Conversioa completion can be enabled to generate -interrupts. These inputs pro%,ide simple connection to such things as joysticks, tracker/roller balls, pressure sensors, ambient level detectors etc.

14. T'FL DIRECT 1/0 PORT.

This is an 9 bit TTL level inter-face that has individual direction controls for each bit. All 110s are resistively protected and have pullups' to the Sv supply. Corifigured as outputs they can sinWctrive a maximum of 10mA, as inputs they are pulled high internally and therefore can be operated by open collector/drain devices or by any normal T-1L s lignal. This port is direct to the primary microprocessor and can be operated at speeds of up to 8 million cps. Nonnal uses for this type of interface are logic interconnect, intelligent display modules and high speed parallel interfaces.

15. POWER MONITORING.

Tbe EPOCH design has several different power supply monitors. The first times the line supply period detecting missing cycle bursts and will initiate a power down if more than 4 cycles are lost in succession- A second monitors the power supplies good input signal. Another is riot aetually a power monitor but is the spark detect circuit This -,vril I measure the period of any air bome electro magnetic interference. And if this should fall outside a predetermined value cause a Po %ver down of the system, 16. WATCHDOG.

The design has 33 independent watchdog timers, The purpose of these is to detect any malfiinction in the software, for whatever reason, and reset as fast as possible to mirlimise any potential problems that this would cause- The first watchdog is operated by the primaly microprocessor. The second is implemented in the ASIC and can be isolated at boot tirne if not required- The third is implemented in the second microprocessor as one of ifs tasks is to monitor bus activity and if a certain event is not detected, withi n a predeirined time period, it will initiate a system reset- 17- SERIAL PORTS.

There are two full featured independent sedal communication channels provided via the prirnary microprocessor- These channels can be operated in async mode at baud rates up to 38.400 bpsBoth cbannels support selectable data length, stop bits, parity, multiprocessor bit and baud rate. Full error and break detection are performed. The first channel has a industry standard female 25 pin 'D' type connector with power supply pins as required by data logging ecILdpmerit.

The second is supplied throogh a special connector that has also the TTL direct drive lines for both seriaJ ports as welt &s the RS232 levels for the second channel- Also included on this connector are the 44-12v supplies_ 18. 12C INTERFACE.

This interface is arizahanced I2C two wire port which serves several different purposes'. It is capable of operating at not only the standard I OOkbps but aLso at 40OL-bps and even 1,000kbps. One of the on-board devices that uses this interface is the BEPROK The interface is made available to dx-ternal equipment via the combined matrix display and distributed processor connector. 1he M-C standard allows for a maximum of 126 addressed devices to be linked in the EPOCH system 100 of these are available externally- There are many standard parts that directly operate using this qW of interface these include such things as random access memory storage devices of all q-pes. data logging units, communication devices of any vanieties- Another use of this Interface Is to allol-v machine sub-Sy5tCMS to operated as independent units if required, For example reel processing could be operated by a discrete 12C processor device that accepts commands from the main systern board- However as the EPOCH system handles most of the normal g=ing support L/0 ffinctions without need of main processor support anyway this mode of operation as very little benefit- 19. CPU/OPTION SWITCHES.

There are 2 banks of 8 switches on-board the main -system, These are read as I-Epart of the'linked 1/0 resource through a. dedicated channel and the data is stored directly into a specific area of the static RAM using the direct %,#Tite RAM process-'These inputs are read at the frame rate of the link interface, approx. 100 times/sec. Also fitted to the main system board is a momentary action single pole push button called the, cpLi FLJNCnOM switch. This can be directly read by the primary microprocessor through the ASrC or linked at boot time to generate an interrupt to it. This interrupt is selectable as NM or MQ.

20. LAMPS.

The EP.OCH system has the ability to drive up to 512 individual lamps directly via the 1/0 link interface. Because the lamps are output over this inEerface only the reqUired nw-nber of jarnp drives to support a particular garne need to be fitted making possible great flexibility plus low unit costs, All activity is performed by the ASIC and requires no support from the prirnary microprocessor- Information for every possible larrip position is maintained in a specific, area of the static RAM This information is read by the ASIC and is used to control the linked 110 lamp resources.

The lamps can be individually dimmed, flashed at any of 6 possible software controlled timer rates, set to a particular flash pha--.-- or simply tumed on- The flash rate timer periodsare also setup by the direct read RAM process. the timers themselves axe fully maintained by the ASIC arid need no support from any microprocessor. Each lamp can be individually dimmed to one of 8 brightness levels- It is possible to have overload and lamp failure detection for any or all of the larnp outputs if required Information regarding the status of the lamps outputs can be rcad back via the linked input resource, sytem- The ASIC also provides fiiil safe protection in the event of software crash- The other important feature of the lamp driving process is the way flicker and pulse effects are eliminated. These have normal IN, t%vo possible causes, firstly irregular source refresh rates that cause individual strobes to have longer on periods than others. Secondly, as the power source for the laraps is never normally stabill5ed the ripple on the supply line varies the energy delivered to each strobe randomly chan ing its'lairips illumination output. In the EPOCH' design the first of these is corrected bv ha-rdware multiplexing that it precisely timed and the second is corrected by the use of partern line frequency synchronised refresh which makes sure that all strobes receive the same total energy independent of supply ripple. The use of these techniques also make dimmed [amps absolutely stable at all brightness levels.

21. LEOS.

The EPCCH system has the ability to drive up to 512 individual LEDs directly via the UO iirik interface. Because the LEDs are output over this interface only the required number of LED drives to support a particular gaxne need to be firted making possible great flexibility plus low unit co-sts. All activity is performed by the ASIC and requires no support from the primary rrucroprocessor, Wormation for every possible LED position is maintained in a specific uea of the stadc PLAM This information is read by the ASIC and is used to control the linked YO LED resourc4-s. The LED resource has no connection with the lamp resources and all if s functions are unique. The LEDs can be individually dimmed, flashed at any of 6 possible softwax-e controlled timer rates, set to a particular flash phase or simply turned on. The flash rate timer per-lads are also set-up by the direct read RAM process, the timers thernselves ax- e fully maintaiaed by the ASIC and need no support from any microprocessor. Each LED can be individualli dimmed to one of 8 brightness levels.

The LEDs can be coafigured in any way required such as 512 individual devices, 64 eight segment displays, 32 sixteen segment alphanumeric &5plays or a matrix display (no co'naaction with the dedicated mamix display part)- If LED drives are not required by a partliculaz garne the resource can be used to provide a finther 512 outputs.

Mere is also a futire mode that vvill allow the LED outputs to operated in 3D multiplexed mode that will provide 4096 element drive capability. This mode will not have brightness control but will be able to support tri-colour LED modules, 22. INPUTS- The 'EPOCH design provides support for up to 4096 direct inputs via the YO link interface. Becaus-- the inputs are read over tWs interface only the number of inputs required in a particulki-arne need be Fitted making possible great flexibility plus low unit costs. These inputs can be operated at any voltage that may be desired. All activity is performed by the ASIC and requires no supprt from the primary microprocessor. Input states read via the linked 1/0 interface are directly -written to a specific area of static RAM by the ASIC_ The inputs are operated in blocks of 64 (this is ordy the architectural block size not the number physically attached to the link interface, which is normally used in blocks of 8) and the number of blocks activated -15 fully controlled by software. Each block -is read in and Wnitten to RAM -in 156US (6,400 time's/sec). All inputs have the ability to generate an individual 'Interrupt to the primary microprocessor with selectable active state- It 15 also possible for analog 'input readings to be taktm over the input resource this feature is used during diagnostic testing- 23. OUTPUTS.

The 'EPOCH design provides support for up to 4096 direct outputs Via the L/O link interface. Because thcse outputs are written over this interface only the number of Outputs required in a Particular game need be fitted making possible great flexibility plus low unit costs- The C=ent and voltage ratings for any of these outputs are independent of the main system and can therefore drive any power device that may be desired. All activity is performed by the ASIC and requires no support from thepriaiary microprocessor. Output states are written via the linked jjo interface from a sp=lflc area of static RAM by the ASIC. T-be outputs are operated in blocks of 64 (this is only the architectural block size not the number physically attached to the link interface, which is normally used in blocks of 8) and the number of blocks activated is fully controlled bysoftware. Fach block is written ftorn the RAM in 156uS (6, 400 times/sec)- C=ent dete.crion is optional to any or all of the outputsAny group of outputs can be decticzhed to drive =1 phases. Interrupts are provided that are synchroriised to the 1/0 refresh and 1/0 ftame periods to support smooth reel control functions.

24. DISPLAY PORT.

A powerful feature of the F-POCW design is the provision of a d.i.rectly driven LED display port Ms port is configured at boot time and directly operates firom the ASIC. It requires no support from any of the microprocessors- Display data is directly read from specific areas of the static R-AM and output at high speed to the matrix display. -Me display port can be operated in several different reftsh modes. In single pass mode the display refresh rate is approx. 10014z giving flicker ftee outpur- The interface uses two data planes which allow fast sprit refresh. Each plane has two maps that provide 4 levels of individual pixel brightness control- 25. DIAGNOSTIC PORT.

There is support via the data link connector for a powerful diagnostic interface- Using this interface a test unit can control the various subsystems of the system board and action direct testing "Ithout the need for any microprocessor activity. This interface is described in section 3. The use of this feature makes the task of manufacture and service system exercising simple.

26. IN-CIRCUIT EMULATOR SUPPORT.

This is one of the most important fcatures of the MPOCH design. BLjlt into every Unit there is a full feature in-circuit emulator at no extra cost. This feature is activated by the boot microprocessor and re- configures the g2me EPROM signals.to allow- the EPROMs to be replaced with St:atic RAMs, and enables internal address and data s ignal.molui to ring and several special exception vector interrupts to the primary microprocessorThere are two. basic Memory modes of emulation, In. the first all four EPROM sockets can be replaced with SRAMs and in the second the lower positions are maintained as EPM& and only the.upper positions are op;erate as SRAM area, TWs makes possible the use of fixed l1brazies during development and also allows special monitor programs to be operated that can use the- upper SRAM area directly YArhout need for the emulator link In brief the user replaces the socketed boot microprocessor with a special version that enables the emulator functions U-1regrated -in the ASIC and disables any protection functions that do not compromise multi op.--rator protection (e.g. does not disable the features that maintain commercial protection between different companies who use the system). The EPROM sockets are loaded with the replacement static RAMs and a communications link cable fitted between the target 13POM systern and a starIdard PC A special PC add-in card is provided that provides all the necessary cominunications support between PC and EPOCH system. The PC can then control the system directly allo%,ing dowriload/upload of programs and microprocessor debug data- Data can be transferred o, -er this interface at up to 120KBytes/sec.

A hardware breakpoint controller, in che'EPOCIT system, can be configured via the PC link to break on any address and'or data and/or control sipal condition. It isf also possible to single step through the proo-Tarn, sequence or force a breakpoint at any time during program execution and change any or all of the primary microprocessor states at any time. Full reset control and illegal operation (e-g.. program attempt-Ing to wri-te to EPROM space etc,) monitoring is provided to generate exception reporting directly to the PC via the link.

DETAILED SYSTEM OVERVIEW The linked VO resources lamps, LEDs, inputs, outputs, option switches and display port operate via a process called direct RAM write/read. This is a function operated entirely by the ASIC and requires no support fxom any of the microprocessors other than the initial enabling of it's operation- Data is read and written to the static R" by a sequence of high speed burst bus mastering this means that the required access bandwidth to support the entire support process (which is approx. 1.2Mbyt&sec) under normal operation is hidden from the primary microprocessor resource- In the EPOCH' design described the primary processor is the 11itachi HD6413 002FNI 6 which sets the master system clock speed of 16MRz and is connected to the ASIC via a 16 bit data bus. The processor is enabled after the boot microprocessor has successfully configured the system for the Same that is to be run. The data and address buses are Mven to the main ASIC the majority of the resources are handled via the ASIC. With this configuration maximum memory performance can be realised. M linked I/Os are directly read or written to the battery backed static RAM and this is done by bus master block accesses which are hidden from the primary microprocessor to maintain maximum CPU performance. The buses of the microprocessor are time sliced and mastered by the ASIC to further increase available access time. Some functions of the microprocessor are controlled by the security microprocessor directly or via set-ups within the ASIC determined during the boot period, LINKED 1/0 RESOURCE.

General Operational Overview.

The majority of the I/O's of the 'EPOCH' system are operated over the linked 1/0 interface. This interface is connected across a number of 1/0 modules by a 10 way standard IDC ribbon cable. Within the cable are signals that carry the different types of 1/0 data serially around the linked modules. The 1/0 requirement is identified by five signal types as follows:- 1- Lamp data.

2. LED data, 3. Input data.

4- Output data.

5. Strobe data.

The data is clocked over the interfkce by a further signal the '1/0 Clock', and synchronised by the '110 Strobe' signal, There is also a Wobal '1/0 Enable' signal which is used to disable all output devices connected to the link during power-up and down. The remaining two signals are the logic power and groundAese are intended as reference supplies and no power is drawn ftom thern- There is one other data type and that is for tile option switches, This type is totally handled within the main systern board and does not appear on the 1/0 link mnnector. The option switch data is also operated in a unique way compared with all other types.

The 1/0 interface is globally enabled by the 'EIOLNK' bit -in the 'System Control Register'. This bit also forms the link signal '1/0 Enable' thus when the link is not enabled the '1/0 Enable' signal is inactive wMch forces all output devices connected to the link to be disabled.

The basic unit of serial 1/0 channel data is called a block and is formed by 2 bytes of data. Each block of such data is transmitted in approximately 39us when the system is operated on a 5OHz supply (the 1/0 interface can be synchronised to the supply rate, this is described later) - After each block period the gate array, on the system board, prepares the data for the next block period and repeats the process.

The blocks are grouped into fours to provide the basic update period called a refresh period. At the end of each refresh period, approximately 156us for 501-IZ supply, the 1/0 strobe is fired to load the data into (or from in the case of inputs) the target devices on the link. These eight bytes are transmitted for outputs and received for inputs. To get a good picture of this interface it is best to imagine that output data leaves the system board bit 63 (byte 7, MS bit) first and that input data arrives at the same time bit 0 (byte 0, LS bit) first. This produces, at the end of 64 clocks (all eight bytes delivered), an imaginary five rows of eight bytes matrix. Each row is formed by a data type and each column by incrementing bytes from zero to seven where zero is closest to the system board.

These basic 64 bits of 1/0 data are further expanded by the data delivered over the strobe signal line. The refresh periods are grouped into eights and this period is called the strobe period. These strobe periods are also grouped into eights and this total period is called a frame period. The eight data bytes within each refresh period of the strobe sigml are identical- Each strobe byte is formed by three bits of data that indicate the current refresh period number, three bits which indicate the current strobe period number and two bits that are called the global output bits. These two global bits are used fbr 1/0 test purposes and are controlled aoin the WO ControMatus Register' bits 0 & 1. The five data types of the 1/0 link use the refresh and strobe counts differently as is described in the following paragraphs.

Technical Description of the 1/0 Cycle.

The basic 1/0 cycle is synchronised to the line rate, 5016OH7, and takes 9.984/8.32mS to complete. Each cycle is divided into 8 strobe periods (1. 248/1.04ms), each strobe period has 8 refresh periods (156/130us), each refiresh period has 4 block periods (39/32.5us). Datato the 1/0 resources is clocked at 57 1 kHz- Therefore each 16 bit block of 1/0 data takes approx. 28us, or 448 clocks, to transmit over the link.

The display port is operated as 105 pixels by 28 rows by 7 plane times giving each pixel 4 brightness levels. To display this requires the data to be clocked at 820kbps therefore data needs to be read from RAM at two words per block period. This represents a matrix display loading of approx. 0.32/0.38%. However, as the VO resource link does not maintain constant output, as it is synched to the fine rate, the display port has to have its' own control system that behaves in the same way that the 110 resource controller does. The main board clock runs at 16hffh (62.5ns), 624/520 clocks gives one block period. All blocks of each refresh period have the same access requirements. Follows are the process period access requirements.

Linked IVO SRAM Access Descriptions.

First Strobe Period (4Block + 9Refresh - Strobe). The clock slice bus controller is requested to transfer the following word data. This takes a total of 26 clock periods out of 159744/133120 in each frame, which is a negligible time slice loading.

6 words Read timer compare values for lamp flash rates.

6 words Write back adjusted timer compare values for lamp flash rates.

6 words Read timer compare values for LED flash rates.

6 words Write back adjusted timer compare values for LED flash rates.

I word Read dimmer compare values for lamps and LEDs I word Write the 16 option switch states.

Each block period the bus controller is requested to transfer the following word data- This takes a total of 22 clock periods (there is a system overhead of 1) out of 624/520 in each block (3.52/4.23%) when operated in high speed RAM mode. Then timings given should be multiplied by 1.5 times when system configured for slow RAM devices.

I word - Write the last read 16 bits of input data.

I word - Read the interrupt masks for the last read 16 bits of input data.

8 words - Read the next 16 lamp data values.

8 words - Read the next 16 LED data values.

I word - Read the next 16 bits of output data.

2 words Read the next 32 bits of data for the matrix display.

Total data load for each block period is 42 bytes in 39/32-5uS. This gives a data usage rate of approx. 1.077Mbytes/sec- Time Slicing Controller Description

The system buses (the data bus, address bus and control bus etc) of the EPOCH system connect the various system resources (in/out resources, memories etc) to the primary processor and the coordinator unit. As the system buses in the EPOCH system have two masters (the primary processor and the coordinator unit - in this embodiment the Hitachi HD6413002FNI 6 and the ASIC), it is desirable to 'time slice' in order to ensure that the two bus masters do not attempt to simultaneously use the buses to access system resources, at least not so as to detrimentally affect the other. That is it is desirable to ensure that at any one time either the primary processor or the coordinator device, but not both, can act as a bus master.

Conventional personal computer systems achieve time slicing by halting the primary processor whenever a second bus master requires access to a resource which it shares with the primary processor. This disrupts the operation of the program running on the primary processor and also reduces the system bus (and therefore memory) access time available to the primary processor.

The EPOCH system uses a novel approach to time slicing which is unique not only in the game machine industry but also in the computer industry. The coordinator unit time slices by exploiting the access profile of the primary processor. The coordinator unit monitors the Timary processor's access cycle and splits into active and inactive portions. The coordinator unit then only accesses shared resources during the inactive portions of the primary processor-s access cycle- In this way the primary processor is unaffected: it runs at normal speed and does not need to be halted in order to enable the coordinator unit to access the system buses, The coordinator unit is able to access the system buses in the same access cycle as the primary processor, but during a different portion of the cycle.

By way of example the primary processor may have an enable clock access cycle of 8 MHZ as shown in Fig. 3. The enable clock generates a square wave; the high and low portions in every cycle of the wave are each approximately 67.5ns. The primary processor accesses the system buses during the high portion of each cycle and the coordinator unit accesses the system buses during the low portion of each cycle. As a safety measure to ensure that the two do not conflict the coordinator unit waits for a suitable period, e-g. I Ons, into the low portion of the cycle until it access the system buses and finishes accessing the system buses a suitable period, e.g. 10ns, before then end of the low portion of the cycle. As will be apparent to a person skilled in the art, other frequencies and waveforms could be used, as long as the cwrdinator unit always uses a different portion of the access cycle to the primary processor. During the high portion of each cycle the coordinator unit carries out its own internal operations and/or is available for addressing by the primary processor.

The time slicing used by the EPOCH system is thus very efficient and this has many advantages, particularly for a game machine. The 1/0 needs of a game machine require constant data access, typically at a rate greater than I Mbyte/sec and extensive data conversion work (as ran be seen from the above embodiments). Conventionally this work is done by an application runming on the primary processor, On the EPOCH design this work is carried out by the coordinator unit (the ASIC) during the inactive portions of the access cycles of the primary processor. This work is thus hidden from the primary processor which does not suffer any performance loss due to the servicing of these needs.

This form of time slicing is also advantageous when the EPOCH system is used as a game software development tool. In conventional emulation systems emulation facilities such as program monitoring and debugging cannot be carried out in real time and methods such as program step through have to be utilised. Furthermore conventional emulations systemshave to use a much faster processor d= the one being emulated in order to support the emulation facilities. With the EPOCH system the primary processor of the game machine itself is used for the emulation and it is possible to carry out emulation facilities in real time.

This is made possible because the coordinator unit (in this embodiment the ASIC via its incircuit emulation function) is able to master the system bus during inactive portions of the access cycle so as to provide monitoring, debugging and/or emulation facilities in real time while the primary processor is running. game software. Because the coordinator unit access the system buses during inactive portions of the access cycle it is possible to carry out these activities in real time and without disrupting the primary processor. Thus while the game software is running in real time, it is possible to monitor data in memory, and to use an external resource such as a development PC to influence the software by accessing the system resources (e.g. by writing data into an area of memory or simulating payment via the payment receiving mechanism).

The security functions of the EPOCH system likewise use the above mentioned time slicing facility of the coordinator unit.

A demonstration version of the EPOCH system exists in which efficient use of memory access time by the above time slicing method enables the coordinator unit to provide additional resource access to support a full TFT display, This required a steady bandwidth of over 32 Mbytes/sec.

Claims (1)

1. A game machine having a plurality of resources including a payment receiving means, a memory foj storing 5 game software and a processor unit for processing the game software; and a coordinator unit for interfacing with the resources and for controlling data passing between the resources.

2. A game machine according to claim 1 having a data bus connecting the coordinator -unit and the processor unit; a system clock for determining the operation of the processor unit, and is controller means for ensuring that the coordinator unit only accesses the data bus during a portion of each clock cycle.

3. The game machine of claim 2 wherein the system clock 20 sets an access cycle, and the processor unit accesses the data bus during an active portion of each access cycle and the coordinator unit only accesses resources during an inactive portion of each access cycle.

51 4. The game machine of claim 2 or 3 wherein the data bus connects the coordinator unit to a plurality of resources including the processor unit and one or more of the memories. 5 5. The ga-me machine of any one of the above claims wherein the resources further include one or more of the following: an input device, an output device, a second processor 10 unit and/or a PC external to the game machine.

6. A game machine according to any one of claims 3 - 5 wherein the controller means ensures that the coordinator unit waits in the inactive portion of the access cycle for 15 a period of time equal to at least 5% of the access cycle period before acce5sing a resource and finishes acce5sing the resource a like period of time before the end of the inactive portion of the access cycle.

20 7. A game machine according to any one of claims 2 - 6 wherein the controller means ensures that the processor unit accesses the data bus in a first half of each clock cycle and the coordinator unit only accesses resource5 and/oT the data bus in a second half of each clock cycle.

52 8. A game machine according to any one of the above claims wherein the clock cycle alternates between a high value and a low value and wherein the processor unit accesses the data bus when the clock cycle is high and the 5 coordinator unit only accesses the data bus when the clock cycle is low or vice versa.

9. A game machine according to any one of the above claims wherein the resources include one or more information output devices; and wherein the processor unit for processing the game software is configured to generate operating data for operating the output devices; and the coordinator unit is configured to receive the 15 operating data, and generate, based on the operating data and information about the requirements of the output devices, operating instructions for transmission to the output devices to control the output devices.

10. The game machine of claim 9 wherein; the information about the requirements of the output devices includes data defining the refresh requirements of the output devices; and wherein in use the coordinator unit responds to 25 operating data indicating that a particular output device 53 should be outputting in a certain period by generating and transmitting operating instructions to that device during that period at a rate which is at least the refresh rate of that output device.

11, The game machine of claim 9 or 10 wherein in use the processor unit or the coordinator unit writes the operating data to a memory which the coordinator unit can read so that the coordinator unit can generate successive operating 10 instructions without requiring operating data from the processor unit each time.

12. The game machine of any one of claims 9 - 11 wherein the operating data includes timing data defining the timing 15 according to which the output devices should be controlled.

13. The game machine of claim 12 wherein the coordinator unit incorporates the timing data into the operating instructions which it generates.

14. The game machine of any one of claims 9 - 13 wherein the coordinator unit transmits operating instructions to a plurality of output devices along a respective channel for each output device.

54 15. The game machine of claim 14 wherein the operating instructions sent along each channel are in a serial format.

5 16. The game machine of claim 14 or 15 wherein the times at which the operating instructions are transmitted along different channels are coordinated to produce simultaneous operation of output devices.

17. The game machirie of any one of claims 9 - 16 wherein the transmission rate of the operating instructions iu selected to be an odd multiple of the processor unit's clock frequency.

18. The game machine of any one of claims 9 - 17 wherein the game machine has an electrical power supply and the coordinator unit is arranged to send the operating irl5tructions, to the output devices in dependence on the waveform. of the power supply.

19. The game machine of claim 18 wherein the coordinator unit is arranged to send the operating instructions to the output devices in synchrony with parts of the power waveform in such a way as to ensure that the output device (s) receive the operating instructions when the power they receive is at an adequate level.

20. The game machine of claim 19 wherein the coordinator 5 unit transmits output instructions in bursts, each burst containing one or more operating instructions to each of the output devices.

21. The game machine of claim 20 wherein the burst are 10 slightly shorter than the period of the power supply and synchrondsed with the power supply.

22. The game machine of claim 20 or 21 wherein the coordinator unit is arranged to react to variations in the 15 regularity of the mains supply by varying the interval of the bursts.

23. The game machine of claim 22 wherein the coordinator unit is arranged so that a sufficiently great perturbation 20 of the power supply waveform leads to a burst being missed for a given cycle of the power supply.

24. A game machine according to any one of the above claims wherein the resources include one or more 25 information input devices; 56 and the coordinator unit is configured for receiving signals from the input devices, processing the signals to generate data based on requirements of the processor unit, arid making the data available to the processor unit. 5 25. The game machine of claim 24 wherein the input devices include one or more push buttons operable by the user.

10 26. The game machine of claim 24 or 25 wherein the information input devices are configured to transmit the signals to the coordinator, the coordinator unit is configured to process these signals into input data and to store the input data in a memory and the coordinator unit 15 is configured to transfer the input data from memory to the processor unit when it determine5 that the processor unit is not occupied, or in response to a signal from the processor -unit.

20 27. The game machine of claim 26 wherein the coordinator unit processes the information from the input devices into a format which is easier for the processor unit to handle.

28- The game machine of claim 27 wherein the coordinator 25 unit's processing of the information from the input 57 device(s) includes generating vector arrays in a predefined format.for storage in volatile memory.

29. A game machine according to any one of the above 5 claims wherein the coordinator unit has a testing configuration for testing the integrity of the game machine resources by connecting the processor unit to a certain section of memory and controlling the processor unit to process the data in that section of memory, the coordinator 10 unit verifying that the processor unit processes the data correctly.

30. A game machine according to claim 29 wherein the coordinator unit adopts the testing configuration when the 15 game machine is booted.

31. A game machine according to any one of the above claims wherein the coordinator unit has means for connecting to a personal computer external to the games 20 machine and means for mediating between the personal computer and other resources connected to the coordinator unit.

32. A game machine according to claim 31 wherein the 25 coordinator unit has a configuration in which it diverts 58 signals from the processor unit to an external personal computer and in which it treats signals received from the personal computer as if they had come from the processor unit.

33. A game machine according to claim 32 wherein the coordinator unit adopts said configuration in response to a signal sent by the personal computer.

10 34. The game machine of any one of claims 31 to 33 wherein the coordinator unit has a configuration in which it treats part of the external personal computer's memory as the memory for storing gaiue software.

15 35. The game machine of any one of claims 31 to 34 wherein, in response to a signal from a connected personal computer, the coordinator unit transfers game software held in the personal computer to memory to writeable memory in the game machine.

36. The game machine of claims 24 wherein the an external PC connected to the coordinator unit can influence the running of a program, processed by the processor uait, by transmitting signals to the coordinator unit.

59 37. The game machine of claim 36 wherein the signals transmitted by the PC to the coordinator unit instruct the game machine to functioii as if payment had been received via the payment means. 5 38. The game machine of claim 37 wherein the signals transmitted by the PC to the coordinator unit cause data to be stored in the game machine memory.

10 39. The game machine of any one of the above claims wherein the coordinator unit is capable of varying its mediation between resources so that a first resource can be substituted for a second resource without the other resources being affected, 40. The game machine of claim 39 wherein the coordinator unit is able to vary its mediation between resources so that volatile memory chips in the game machine memory may be replaced by ROM chips without affecting the other 20 resources or the running of the game machine software.

41. A method of testing game software comprising., providing two or more first resources, including a processor unit for processing game software and a memory for storing game software and a coordinator for mediating between the first resources; causing the gaine software to be processed by the first resources mediated by the coordinator, and 5 investigating the processing; controlling the coordinator to treat a second additional processor unit suitable for installation in a game machine or a read-only memory in place of one of the first resources; and 10 causing the game software to be processed again.

42. A method according to claim 41 wherein the coordinator unit is configured in relation to the other resources as described in any one of claims 2 - 40 above.

43. The method of claim 41 or 42 wherein the method is carried out when the processor unit is connected to at least one output device via the coordinator.

20 44. A tool for writing game software, the tool having:

a plurality of first resources including a processor unit for processing game software and suitable for installation in a game machine and a memory for storing game software; and 61 a coordinator unit for controlling data passing between the resources.

45- A tool for writing game software according to claim 5 44, wherein the coordinator unit is capable of varying its handling of data in response to an external signal so that it can mediate with an additional resource in place of one of he first resources.

10 46. A tool for writing game software further having the features of any one of claims 2 - 40.

47- A tool for writing game software according to claim 46 wherein the tool does not include a payment receiving 15 means.

48. A game machine comprising:

a payment receiving mechanism; a memory for storing game software; a first processor for processing the game software; a second processor which stores a key; and a coordination unit for receiving the key from the second processor and being capable of verifying the key and controlling the processing of the game software by the 25 first processor, the coordination unit only controlling the 62 first processor to process the game software after it has verified the key.

49. A game machine comprising:

a payment receiving mechanism; a memory for storing game software; a first processor for processing the game software; a second processor which stores a memory location containing data required by the first processor to process 10 the game software (e.g. the second processor may have stored the data to that location); and a coordination unit for receiving the memory location from the second processor and making available to the first processor data stored in the memory location.

50, A game machine substantially as herein described.

51. A tool for writing game software substantially as herein described.

52. A method of testing game software substantially as herein described.