GB2363519A - Trench MOSFET structure - Google Patents

Trench MOSFET structure Download PDF

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Publication number
GB2363519A
GB2363519A GB0114633A GB0114633A GB2363519A GB 2363519 A GB2363519 A GB 2363519A GB 0114633 A GB0114633 A GB 0114633A GB 0114633 A GB0114633 A GB 0114633A GB 2363519 A GB2363519 A GB 2363519A
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GB
United Kingdom
Prior art keywords
region
trench
trenches
conductivity type
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0114633A
Other versions
GB0114633D0 (en
Inventor
Adrian Finney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zetex PLC
Original Assignee
Zetex PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0014484A external-priority patent/GB0014484D0/en
Application filed by Zetex PLC filed Critical Zetex PLC
Priority to GB0114633A priority Critical patent/GB2363519A/en
Publication of GB0114633D0 publication Critical patent/GB0114633D0/en
Publication of GB2363519A publication Critical patent/GB2363519A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A trench MOSFET in which two first trenches (7) and a second trench (12) arranged between the first trenches (7) extend into a semiconductor structure through a first region (9) of a first conductivity type and a second region (10) of a second conductivity type into a third region (11) of the first conductivity type. The second trench (12) is separated from the third region (11) by a fourth regions (13) of the second conductivity type. The first trenches (7) receive gate-forming conductive material (4) insulated by layer (8) from the surrounding structure with material (4) connected to electrode (3), whereas the second trench receives metal (2) defining a source contact (1). The fourth region (13) is more highly doped than the second region (10), and extends to a depth no greater than the depth of the first trenches (7). The drain region (6) is situated below the third region (11) and is connected to electrode (5).

Description

2363519 TRANSISTOR DEVICE The present invention relates to a transistor
device and in particular to a transistor device of the type conventionally referred to as a trench MOSFET.
In a MOSFET device, a local electrical field generated in a semiconductor structure around a gate controls the flow of current between a source region of the structure and a drain region of the structure. In a trench MOSFET, the gate is formed in a trench extending into the semiconductor structure, the source being on one side of the structure and the drain on the other such that current flow is in the direction into which the trench extends into the structure. The current flows through a body region of opposite conductivity type to the source and drain regions.
Various proposals have been made to optimise performance. One such proposal is described in US patent 5072266 which describes the use of a deep body region to force voltage breakdown away from the trenches and into the bulk of the semiconductor material. The body region also extends to the surface of the structure on which the source is formed. Unfortunately, as the deep body region is formed by having a relatively heavily doped central portion of the body region it is necessary to allow a substantial area for the body region to allow for sideways diffusion. This has led the manufacturers of some trench MOSFETS incorporating deep body regions to provide deep body regions in only a proportion of the regions of the semiconductor structure between pairs of trenches.
As an alternative to having a body region extending to the surface of the structure on which the source is located, it has been proposed to provide contacts for both source and body regions in secondary trenches located between the gate trenches. Such an arrangement is described in "Ultra low specific on resistant UMOSFET with trench contacts for source and body regions realised by a selfaligned process" Electronics Letters, 29th August 199 1, number 18. That document describes an arrangement in which a secondary trench extends through a source layer of negative conductivity type into a body region of positive conductivity type, a P+ implant being made into the bottom of the secondary trench to ensure a good ohmic contact between a source electrode which fills the secondary trench and the P body region. Such an arrangement makes it possible to achieve a low on resistance but does not address the problem of breakdown addressed in US 5072266.
It is an object of the present invention to provide an improved transistor device.
According to the present invention, there is provided a transistor device comprising a semiconductor structure into which extend at least one pair of spaced apart first trenches and a second trench arranged between and spaced from the pair of first trenches, the first trenches extending into the structure through a first region of a first conductivity type and a second region of a second conductivity type located beneath the first region into a third region of the first conductivity type located beneath the second region, the second trench extending into the structure through the first region, each first trench receiving a first body of electrically conductive material insulated from the first, second and third regions by an insulating layer, the second trench receiving a second body of electrically conductive material electrically coupled to adjacent regions of the structure, and the first and second bodies of electrically conductive material being coupled to respective electrodes, wherein the second trench extends through the second region of the structure to a fourth region of the second conductivity type which is arranged between and contacts the third region and the second body of the conductive material within the second trench, the fourth region being more highly doped than the second region and extending to a depth no greater than the depth of the first trenches.
Preferably, the second trench extends to a depth greater than the depth of a boundary between the second and third regions adjacent the second trench. The electrode which is electrically coupled to the second body of electrically conductive material is preferably in electrical contact with a portion of a surface of the first region on the side of the first region remote from the second region, the region of contact with the surface portion extending from an edge of the second trench.
Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
Figure I is a schematic representation of a conventional trench MOSFET device; Figure 2 is a schematic illustration of a trench MOSFET device in accordance with the present invention; and Figures 3 to 6 illustrate successive stages in the manufacture of the structure shown in Figure 2.
Referring to Figure 1, the illustrated MOSFET device comprises a source electrode 1 connected to a metal layer 2, a gate electrode 3 connected to polysilicon gates 4, and a drain electrode 5 connected to an N+ drain region 6. The gate regions 4 are received within trenches having walls 7, the gate regions 4 being insulated from the trench walls by an insulating layer 8. Between the trenches are arranged a first region in the form of an N layer 9 defining a source, a second region in the form of a P layer 10 defining a body of the device, and a third region 11 which is of Ntype and also extends beneath the trenches.
A secondary trench defined by wall 12 extends through the source layer 9 into the body region 10. A fourth region 13 of P+ type is implanted into the bottom of the trench 12 so as to provide good ohmic contact between the metal layer 2 which extends into the secondary trench and the body region 10.
In use, current flows in the vertical direction between the source and drain through the body region 10. That current can be controlled by controlling the potential applied to the gate electrode 3, that potential generating a localised electric field which penetrates into the semiconductor structure around the trenches 7. When the device as illustrated in Figure 1 is operated in the forward blocking mode (drain positive and gate and source at ground) a depletion region adjacent the drain is pulled towards the bottom comers of the trenches 7. The boundaries of the depletion region are indicated schematically in Figure 1 by broken lines 14. It will be seen that the upper line 14 is relatively close to the source region 9. As a result punch-through breakdown can occur. The lower line 14 indicates that a high electric field will occur at the trench comers 15. As a result avalanche breakdown can occur at the trench comers.
The breakdown voltage could be improved by displacing a central portion of the junction between the body region 10 and the drain region 11 to a greater depth in the structure than the depth at which that junction approaches the trenches 7. This would require however a relative high dopant concentration in the body region 10 which could only by implemented if the spacing between the trenches 7 is relatively large.
Figure 2 illustrates an embodiment of the present invention which makes it possible to obtain an improved breakdown voltage whilst retaining the advantages achievable with a structure such as that shown in Figure 1. The same reference numerals are used in Figure 2 as in Figure I where appropriate. In the arrangement of Figure 2, it will be noted that the trench 12 extends through the source region 9 and the body region 10 into the drain region 11. Thus the relatively highly doped implanted region 13 at the bottom of the secondary trench 12 is inside the drain region 11 of N conductivity type in the arrangement of Figure 2 rather than in the body region 10 of P conductivity type in the embodiment of Figure 1. The region 13 forms an isolating function between the drain 11 and the metal 2.
As a result of the penetration of the secondary trench 12 greater than the depth of the boundary between the body 10 and drain region I I adjacent the trench 12, the lower boundary 14 of the depletion region which in Figure 1 extends upwards towards the trenches 7 can, given the same conditions, be maintained substantially planar as represented in Figure 2. This means that the depletion region does not approach the body 10 and as a result breakdown voltages improve without it being necessary to introduce a high P body dose into region 10. The upper boundary 14 is also displaced away from the source region, reducing the risk of punch- through breakdown.
The essential difference between the prior art structure of Figure 1 and that in accordance with the present invention of Figure 2 is the depth of the secondary trench 12. The region 13 may be shallower than or as deep as, but no deeper than, the main trenches 7. Since the region 13 extends to a depth no greater than the depth of the gate trenches 7 there is no degradation in the breakdown voltage which is controlled by the depth of the gate trenches. If the region 13 were to extend to a greater depth than the gate trenches this would have the effect of reducing the epitaxial thickness resulting in a lower breakdown voltage. Thus the present invention provides a structure with the advantageous shaping of the depletion region to inhibit punclithrough breakdown, providing a lower channel resistance and, if required, a lower threshold voltage, without any disadvantageous reduction in the breakdown voltage.
This difference is easy to implement as, apart from the depth of the second trench, the conventional processes now used to produce the structure shown in Figure 1 can be used to implement the structure in accordance with the present invention as shown in Figure 2.
A highly compact structure can be implemented. For example, the spacing between the closest adjacent walls of the trenches 7 can be of the order of 2.5 microns. The depth of the primary trenches 7 may be of the order of 1.5 microns.
Given that a relatively low P body dose can be used, this has the advantage of making it possible to produce devices with relatively low threshold voltages. Another advantage is that if the secondary trench 12 is sufficiently deep relative to the primary trenches 7, it will transfer the high electric fields which can result in breakdown from the bottom comers of the main trenches 7 to the bottom of the secondary trench 12. This may result in a reduction or elimination of hot carrier injection from high electric fields into the gate oxide layer 8 which is interposed between the gate regions 4 and the walls of the trenches 7. This can improve the gate oxide quality. It can also improve the avalanche capability by channelling the impact ionisation current away from the device channel region at the surface of the main trenches 7. This is particularly advantageous in N channel embodiments because of surface charge effects which make the gain of a parasitic bipolar N source (emitter), P body (base) and N drain (collector) particularly high at the walls of the main trench 7.
Referring now to Figures 3 to 6, successive stages in the production of the structure shown in Figure 2 will be described.
As shown in Figure 3, a semiconductor structure I I initially of N conductivity type has diffused into its upper surface a P region portions of which will form the body region 10 of Figure 2 and an N+ region which will form the drain contact 6. Thereafter, as illustrated in Figure 4, an N region 9 portions of which will form the source regions 9 of Figure 2 is formed over the region 10, trenches 7 are formed through the regions 9 and 10 into the region 11, a layer of oxide 8 is formed within the trenches, polysilicon gate regions 4 are deposited within the insulated trenches, and an insulating layer of oxide 16 is fortned over the upper surface of the structure.
Referring to Figure 5, a secondary trench 12 is cut into the structure between the two trenches 7 and a P+ implant into the trench 12 forms the isolating function region 13. A wet etch is then performed to etch back the edges of the layer 16 adjacent the trench 12, as shown in Figure 6, and a metal layer 2 is then deposited over the entire structure so as to fill the secondary trench 12. The overall structure is then functionally identical to that illustrated in Figure 2, although in the structure of Figure 6 the secondary trench 12 is of substantially the same depth as the trenches 7. It will be noted that the metal layer 2 contacts the surface of the source region remote from the body region, the area of contact extending from each edge of the secondary trench 12.

Claims (4)

1. A transistor device comprising a semiconductor structure into which extend at least one pair of spaced apart first trenches and a second trench arranged between and spaced from the pair of first trenches, the first trenches extending into the structure through a first region of a first conductivity type and a second region of a second conductivity type located beneath the first region into a third region of the first conductivity type located beneath the second region, the second trench extending into the structure through the first region, each first trench receiving a first body of electrically conductive material insulated from the first, second and third regions by an insulating layer, the second trench receiving a second body of electrically conductive material electrically coupled to adjacent regions of the structure, and the first and second bodies of electrically conductive material being coupled to respective electrodes, wherein the second trench extends through the second region of the structure to a fourth region of the second conductivity type which is arranged between and contacts the third region and the second body of the conductive material within the second trench, the fourth region being more highly doped than the second region and extending to a depth no greater than the depth of the first trenches.
2. A transistor device according to claim 1, wherein the second trench extends to a depth greater than the depth of a boundary between the second and third regions adjacent the second trench.
3. A transistor device according to claim I or 2, wherein the electrode which is electrically coupled to the second body of electrically conductive material is in electrical contact with a portion of a surface of the first region on the side of the first region remote from the second region, the said surface portion extending from an edge of the second trench.
4. A transistor device substantially as hereiribefore described with reference to Figures 2 to 6 of the accompanying drawings.
GB0114633A 2000-06-15 2001-06-15 Trench MOSFET structure Withdrawn GB2363519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0114633A GB2363519A (en) 2000-06-15 2001-06-15 Trench MOSFET structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0014484A GB0014484D0 (en) 2000-06-15 2000-06-15 Transistor
GB0114633A GB2363519A (en) 2000-06-15 2001-06-15 Trench MOSFET structure

Publications (2)

Publication Number Publication Date
GB0114633D0 GB0114633D0 (en) 2001-08-08
GB2363519A true GB2363519A (en) 2001-12-19

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047045A1 (en) * 1996-06-06 1997-12-11 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
EP0889511A2 (en) * 1997-06-30 1999-01-07 Harris Corporation Trench contact process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047045A1 (en) * 1996-06-06 1997-12-11 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
EP0889511A2 (en) * 1997-06-30 1999-01-07 Harris Corporation Trench contact process

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Publication number Publication date
GB0114633D0 (en) 2001-08-08

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