GB2357873B - A method and apparatus for performing cache segment flush operations - Google Patents

A method and apparatus for performing cache segment flush operations

Info

Publication number
GB2357873B
GB2357873B GB0105382A GB0105382A GB2357873B GB 2357873 B GB2357873 B GB 2357873B GB 0105382 A GB0105382 A GB 0105382A GB 0105382 A GB0105382 A GB 0105382A GB 2357873 B GB2357873 B GB 2357873B
Authority
GB
United Kingdom
Prior art keywords
cache segment
performing cache
flush operations
segment flush
operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0105382A
Other versions
GB0105382D0 (en
GB2357873A (en
Inventor
Lance Hacking
Shreekant S Thakkar
Thomas R Huff
Vladimir Pentkovski
Hsien-Cheng E Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/122,349 external-priority patent/US6978357B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0105382D0 publication Critical patent/GB0105382D0/en
Publication of GB2357873A publication Critical patent/GB2357873A/en
Application granted granted Critical
Publication of GB2357873B publication Critical patent/GB2357873B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0105382A 1998-07-24 1999-07-15 A method and apparatus for performing cache segment flush operations Expired - Fee Related GB2357873B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/122,349 US6978357B1 (en) 1998-07-24 1998-07-24 Method and apparatus for performing cache segment flush and cache segment invalidation operations
GB9916637A GB2343029B (en) 1998-07-24 1999-07-15 Method and apparatus for performing cache segment flush and cache segment invalidation operations

Publications (3)

Publication Number Publication Date
GB0105382D0 GB0105382D0 (en) 2001-04-18
GB2357873A GB2357873A (en) 2001-07-04
GB2357873B true GB2357873B (en) 2002-01-09

Family

ID=26315769

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0105382A Expired - Fee Related GB2357873B (en) 1998-07-24 1999-07-15 A method and apparatus for performing cache segment flush operations

Country Status (1)

Country Link
GB (1) GB2357873B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6802057B1 (en) 2000-05-03 2004-10-05 Sun Microsystems, Inc. Automatic generation of fortran 90 interfaces to fortran 77 code

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6546359B1 (en) 2000-04-24 2003-04-08 Sun Microsystems, Inc. Method and apparatus for multiplexing hardware performance indicators
US6647546B1 (en) 2000-05-03 2003-11-11 Sun Microsystems, Inc. Avoiding gather and scatter when calling Fortran 77 code from Fortran 90 code

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0210384A1 (en) * 1985-06-28 1987-02-04 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
GB2210480A (en) * 1987-10-02 1989-06-07 Sun Microsystems Inc Flush support
US5524233A (en) * 1993-03-31 1996-06-04 Intel Corporation Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations
WO1997022933A1 (en) * 1995-12-19 1997-06-26 Advanced Micro Devices, Inc. System and apparatus for partially flushing cache memory
EP0817081A2 (en) * 1996-07-01 1998-01-07 Sun Microsystems, Inc. Flushing of cache memory in a computer system
US5778432A (en) * 1996-07-01 1998-07-07 Motorola, Inc. Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0210384A1 (en) * 1985-06-28 1987-02-04 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
GB2210480A (en) * 1987-10-02 1989-06-07 Sun Microsystems Inc Flush support
US5524233A (en) * 1993-03-31 1996-06-04 Intel Corporation Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations
WO1997022933A1 (en) * 1995-12-19 1997-06-26 Advanced Micro Devices, Inc. System and apparatus for partially flushing cache memory
EP0817081A2 (en) * 1996-07-01 1998-01-07 Sun Microsystems, Inc. Flushing of cache memory in a computer system
US5778432A (en) * 1996-07-01 1998-07-07 Motorola, Inc. Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6802057B1 (en) 2000-05-03 2004-10-05 Sun Microsystems, Inc. Automatic generation of fortran 90 interfaces to fortran 77 code

Also Published As

Publication number Publication date
GB0105382D0 (en) 2001-04-18
GB2357873A (en) 2001-07-04

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20130715

S28 Restoration of ceased patents (sect. 28/pat. act 1977)

Free format text: APPLICATION FILED

S28 Restoration of ceased patents (sect. 28/pat. act 1977)

Free format text: RESTORATION ALLOWED

Effective date: 20140409

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20170715