GB2356272A

GB2356272A - Low jitter fractional divider

Info

Publication number: GB2356272A
Application number: GB9926751A
Authority: GB
Inventors: Wen-Chang Lin
Original assignee: Sunplus Technology Co Ltd
Current assignee: Sunplus Technology Co Ltd
Priority date: 1999-11-10
Filing date: 1999-11-10
Publication date: 2001-05-16
Anticipated expiration: 2019-11-10
Also published as: GB2356272B; GB9926751D0

Abstract

A low jitter fractional divider with low circuit speed constraint comprising a divider 11 for dividing the frequency of an input first clock signal ck by an integer number, c, to obtain a second clock signal ck' and a fractional divider 12 for dividing the second clock signal ck' by a fraction number, b/a, to obtain an output voltage signal ov, a compensation circuit 13 for receiving the output voltage signal ov and generating an output clock signal cka with low jitter. The circuit 13 comprises an adjust buffer 131 for generating an adjust signal based on the output voltage signal ov and a feedback of the output clock signal cka, wherein the buffer 131 has a value which is decreased when the output voltage signal ov asserts a pulse until reaching a predetermined minimum and is increased when the output clock signal cka asserts a pulse until reaching a predetermined maximum, and a down-counter 132 which performs a counting operation for generating the output clock signal cka wherein the down-counter 132 is loaded with a count value determined by a, b and c based on the adjust signal and the feedback of the output clock signal cka when a zero value is reached in said down-counter, thereby adjusting the output clock signal to reduce jitter.

Description

2356272 LOW JITTER FRACTIONAL DIVIDER WITH LOW CIRCUIT SPEED CONSTRAINT

BACKGROLTND OF THE INVENTION

1. Field of the Invention

The present invention relates to a fractional divider and, more particularly, to a low jitter fractional divider with low circuit speed constraint.

2. Description of Related Art

Conventionally, a fractional divider is provided to divide the frequency of a clock signal by a fraction number '%N', wherein b>a. Such a fractional divider is implemented by employmg an accumulator to add the value of "a" to the value stored in the accumulator in each operation cycle. The accumulated value is compared with the value of "b". In case of a>b, the accumulated value is subtracted by the value of "b" and restored to the accumulator, and an overflow flag is generated. Otherwise, the accumulated value is simply re-stored to the accumulator. This overflow flag is provided to be the output of the fractional divider. FIG. 4 shows that such a fractional divider 41 is used to divide a clock signal "ck" by 5/3 to generate a divided clock signal "ck"'. Based on the operating manner of the fractional divider 41 as described above, a timing diagram is obtained, which illustrates that five continuous pulses of the clock signal "ck" are applied to the fractional divider 41 to generate three continuous pulses of clock signal "ck"'. Therefore, a divide-by-5/3 operation is performed.

However, the pulses of the clock signal "ck... generated by the fractional divider 41 are not uniformly distributed, which is known as a jitter phenomenon in the art. Such jitter is especially obvious if the clock frequency to be divided is low. To overcome this jitter problem, the conventional technique employs a high frequency base clock signal and an accumulator for implementing a fractional divider to obtain a low jitter I clock signal. However, when the stages of the accumulators are increased and the frequency of the base clock signal goes higher, the accumulator will not be able to finish the required accumulation operation in a short operation cycle, due to the limitation imposed by the current integrated circuit manufacturing process. Accordingly, a bottleneck is encountered with the increase of a clock signal. In addition, it may be applicable to reduce the frequency of a high-frequency clock signal prior to performing the fractional division operation, thereby avoiding the bottleneck. Unfortunately, this will increase the jitter as described above. Therefore there is a. need to have a fractional divider which can mitigate and/or obviate the aforementioned problems.

SUMMARY OF TIHE R4WNTION

The object of the present invention is to provide a low jitter fractional divider with low circuit speed constraint, -which is triggered- by a clock signal with a relatively low frequency to perform a fractional division process, such that the bottleneck in circuit speed can be eliminated and a lowjitter as achieved in a high frequency fractional division process can be maintained.

To achieve the object, the low jitter fractional divider with low circuit speed constraint in accordance with the present invention includes a divider, a fractional divider, and a compensation circuit. The divider is provided to divide the frequency of an input first clock signal by an integer number c to obtain a second clock signal. The fractional divider divides the frequency of the second clock signal by a fraction number b/a to obtain an output voltage signal. The compensation circuit has an adjust buffer and a down-counter for receiving the output voltage signal to generate an output clock signal with low jitter. The adjust buffer generates an adjust signal based on the output voltage signal and the feedback of the output clock signail, wherein the adjust buffer has a value which is decreased when the 2 output voltage signal asserts a pulse, until reaching a predetermined minimum value, and a value which is increased when the output clock signal asserts a pulse until reaching a predetermined maximum value. The down-counter is driven by the first clock signal to perform a counting operation for generating the output clock signal, wherein the down- counter is loaded with a count value determined by c, a, and b, based on the adjust signal and the feedback of the output clock signal when a zero value is reached in the down-counter, thereby adjusting the output clock signal to reduce j itter.

Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system block diagram of a low jitter fractional divider with low circuit speed constraint in accorda4ce with the present invention; FIG. 2 shows the conditions to load a down-counter of the low jitter fractional divider with low circuit speed constraint in accordance with the present invention; FIG. 3 is a timing diagram showing an exemplary operation of the low j itter fractional divider with low circuit speed constraint in accordance with the present invention; and FIG. 4 shows a conventional fractional divider and an exemplary timing diagram thereof DETAILED DESCRIPTION OF TBE PREFERRED EMBODIMENT

With reference to FIG. 1, the system block diagram of a low jitter fractional divider with low circuit speed constraint in accordance with the present invention is shown, which includes a divider 11, a fractional divider 12, and a compensation circuit 13. The divider 11 is provided to divide the frequency of an input clock signal "ck7 by an integer number "c" to obtain a frequency-divided clock signal "ck/c". The fractional divider 12 divides the frequency of the frequency-divided clock signal "ck/c" by a fraction number "b/a" to obtain an output voltage signal "ov". This output voltage signal "ov" has a higher jitter because it is obtained by dividing "b/a" in low frequency. Tbus, the output voltage signal "ov" must be subsequently processed by the compensation circuit 13 in order to have a jitter approximately equal to that occurred in high frequency.

The compensation Circuit 13 includes an adjust buffer 131 and a downcounter 132 for receiving the output voltage signal "ov" to generate an output clock signal."cka" with low jitter. The adjust buffer 131 is provided to count the number of pulses in the output voltage signal "ov" and the feedback of the output clock signal "cka" for generating an adjust signal "adjust". The counting manner is such that the value of the adjust buffer 131 is increased by 1, whenever a puls e in the output clock signal ('cka" is present, until reaching a predetermined maximum value An,., and the value of the adjust buffer 13 1 is decreased by 1, whenever a pulse in the output voltage signal "ov" is present, until reaching a predetermined minimum value Amin- After reaching the maximum value Am,,, or minimum value Amin) the adjust buffer 131 will not be increased or decreased even if there are pulses present in the output clock signal "cka" or output voltage signal rcov".

When the value of the adjust buffer 131 is equal to the minimum value Amin5 the adjust signal "adjust" generated by the adjust buffer 131 is at a low logic level. On the contrary, when the value of the adjust buffer 131 is a value other than the minimum value Amini the adjust signal "adjust" is at a high logic level.

The down-counter 132 is driven by the input clock signal "ck" for performing a counting operation to generate an internal adjusted signal "adjusted" and a count zero signal "countZ", which are provided to 4 indicate that the output clock signal "cka" has been adjusted in a specific operation cycle and the down-counter 132 has counted to zero, respectively.

In general, the down-counter 132 is driven by the input clock signal 4'ck" to count downwardly. When the down-counter 132 counts to zero and the count zero signal "countZ" is at high logic level, a load operation is conducted based on the condition as shown in FIG. 2. That is, under the condition of the count zero signal "countT' being at a high logic level, the adjust signal "adjust" being at a high logic level, the output clock signal "cka" being at low logic level, and the adjusted signal "adjusted" being at low logic level, the down-counter 132 is loaded with zero and the adjusted signal "adjusted" is set to high logic level, while the output clock signal "cka" remains unchanged. Under the condition of the count zero signal "countZ" being at high logic level, the output clock signal "cka" being at low logic level, and the adjusted signal "Adjusted" being at high logic level, the down-counter 132 is loaded with a high logic level count value ('countIT' and the adjusted signal "adjusted" is set to low logic level, while the output clock signal "cka" is set to high logic level. Furthermore, under the condition of the count zero signal "countZ" being at high logic level and the output clock signal "cka" being also at high logic level, the downcounter 132 is loaded with a low logic level count value "countL" and the output clock signal "cka" is set to low logic level, while the adjusted signal "adjusted" remains unchanged.

The aforementioned high logic level count value "countIT' and low logic level count value "countL" can be determined by the following expression:

countL = L L (cb)/aJ /2J, countH = L (cb)/aj - countL, or countH = L L (c b)/al /2J, countL = L (c b)/aJ - countH, wherein LXJ represents a function of taking the integer portion of X.

- The low jitter fractional divider with low circuit speed constraint in accordance with the present invention performs a jitter compensation with the use of the adjust buffer 13 1 and the down-counter 132. Practically, with reference to FIG. 1 and FIG. 2, the output voltage signal "ov" is the output of fractional divider 12, and the output clock signal "cka" is a clock signal of the output voltage signal "ov" after being j itter-compensated. Therefore, each pulse in the output voltage signal "ov" must have a corresponding pulse in the output clock signal "cka". Accordingly, the value of the adjust buffer 131 is zero if the numbers of these two pulses are equal. Otherwise, the value of the adjust buffer 131 is a positive integer number. When the adjust signal "adjust" is at low logic level, the duration of the output clock signal "cka" at high logic level is equal to the value of "countIT' times the cycle time of the input. clock signal "ck". If such a status is kept, the number of pulses in the output clock signal "cka" will gradually exceed that in the output voltage signal "ov", because (cb)/a > countH+countL.

In other words, the value of the adjust buffer 131 becomes non-zero and the adjust signal "adjust" becomes high logic level. At this time, an adjustment is performed on the output clock signal "cka", in which the duration of the output clock signal "cka" at high logic level is still equal to the value of "countH" times the cycle of the input clock signal "ck", and the duration of the output clock signal "cka" at low'logic level is equal to the value of "countU + 1 times the cycle time of the input clock signal "ck". Such adjustment will increase the number of pulses in the output voltage signal &4ovil, thereby decreasing the value of the adjust buffer 13 1.

The adjusted signal "adjusted" provided to control the adjusted duration of the output clock signal "cka" at low logic level is obtained from a value of ("countU + 1), instead of ("countl," + i), where i > 1, so that the jitter of the output clock signal "cka" can be limited to one cycle of the input clock signal ck'.

6 FIG. 3 is an exemplary timing diagram for the low jitter fractional divider with low circuit speed constraint in accordance with the present invention, wherein c = 5, b = 5and a = 3. The adjust buffer 131 is preferred to be a two-bit buffer, such that Aa,,= 3, Amin = 0, countH =LL (55)/3j/2j= 4, and countL = 4. It is shown that, after being adjusted, the jitter of the output clock signal "cka" has been significantly decreased, thereby completely eliminating the problems in speed and jitter of a fractional divider.

While the invention herein disclosed has been described by means of 10 specific embodiments, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope of the invention set forth in the claims.

7

Claims

1 A low jitter fractional divider with low circuit speed constraint, comprising:

a divider for dividing the frequency of an input first clock signal by an integer number c to obtain a second clock signal; a fractional divider for dividing said frequency of said second clock signal by a fraction number b/a to obtain an output voltage signal; a compensation circuit for receiving said output voltage signal to generate an output clock signal with relatively low jitter, said compensation circuit comprising:

an adjust buffer for generating an adjust signal based on said output voltage signal and a feedback of said output clock signal, wherein said adjust buffer has a value which is decreased when said output voltage signal asserts a pulse until reaching a predetermined minimum value, and which is increased when said output clock signal asserts a pulse until reaching a predetermined maximum value; and a down-counter driven by said first clock signal to perform a counting operation for generating said output clock signal, wherein said down-counter is loaded with a count value determined by said c, a, and b, based on said adjust signal and the feedback of said output clock signal when a zero value is reached in said down-counter, thereby adjusting said output clock to signal a reduce jitter.

2. A low jitter fractional divider with low circuit speed constraint as claimed in claim 1, wherein said adjust signal is at a first logic level when the value of said adjust buffer is equal to said minimum value, and otherwise, said adjust signal is at a second logic level.

8 3. A low jitter fractional divider with low circuit speed constraint as claimed in claim 2, wherein said down-counter generates an internal adjusted signal and a count zero signal to indicate that said output clock signal has been adjusted and said down-counter has counted to zero, respectively, thereby performing a load operation in such a manner that under a condition of said count zero signal being at second logic level, said adjust signal being at second logic level, said output clock signal being at first logic level, and said adjusted signal being at second logic level, said down-counter is loaded with a zero and said adjusted signal is set to second logic level; under a condition of said count zero signal being at second logic level, said output clock signal being at first logic level, and said adjusted signal being at second logic level, said down-counter is loaded with a second logic level count value determined by said a, b, and c and said adjusted signal and said output clock signal are set to first logic level and second logic level, respectively; and under a condition of said count zero signal being at second logic level and said output clock signal being at second logic level, said down-counter is loaded with a first logic level count value determined by said a, b, and c, and said output clock signal is set to first logic level; while said count zero signal is set to second logic level when the value of said down-counter is zero.

4. A low jitter fractional divider with low circuit speed constraint as claimed in claim 3, wherein said first logic level count value is equal to LL (cb)/aJ/21 and said second logic level count value is equal to L(cb)/al subtracted by said first logic level count value, while LI represents a function of taking an integer value.

5. A low jitter fractional divider with low circuit speed constraint as claimed in claim 3, wherein said second logic level count value is equal to L L (cb)/al/21 and said first logic level count value is equal to L(cb)/al 9 subtracted by said second logic level count value, while LI represents a function of taking an integer value.

6. A low jitter fractional divider with low circuit speed constraint as claimed in claim 4, wherein said first logic level is a low logic level and said second logic level is a high logic level.

7. A low jitter fractional divider with low circuit speed constraint as claimed in claim 5, wherein said first logic level is a low logic level and 10 said second logic level is a high logic level, 8. A low jitter fractional divider with low circuit speed constraint as claimed in claim 4, wherein said adjust buffer is an N-bit buffer.

9. A low jitter fractional divider with low circuit speed constraint as claimed in claim 5, wherein said adjust buffer is an N-bit buffer.

10. A low jitter fractional divider with low circuit speed constraint as claimed in claim 8, wherein said predetermined minimum value is zero 20 and said predetermined maximum value is 2 N_l.

11. A low jitter fractional divider with low circuit speed constrain as claimed in claim 9, wherein said predetermined minimum value is zero and said predetermiend maximum value is 2 N_J.

12. A low jitter fractional divider with low circuit speed constraint substantially as described herein with reference to Figs. 1 to 3 of the accompanying drawings.

Amendments to the claims have been filed as follows 1. A low jitter fractional divider with low circuit speed constraint, comprising:

an adjust buffer for generating an adjust signal based on said output voltage signal and a feedback of said output clock signal, wherein said adjust buffer has a value which is decreased when said output voltage signal asserts a pulse until reaching a predetermined minimum value, and which is increased when said output clock signal asserts a pulse until reaching a predetermined maximum value; and a down-counter driven by said first clock signal to perform a counting operation for generating said output clock signal, wherein said down-counter is loaded with a count value determined by said c, a, and b, based on said adjust signal and the feedback of said output clock signal when a zero value is reached in said down-counter, thereby adjusting said output clock signal to reduce jitter.

3. A low jitter fractional divider with low circuit speed constraint as claimed in claim 2, wherein said down-counter generates an internal adjusted signal and a count zero signal to indicate that said output clock signal has been adjusted and said down-counter has counted to zero, respectively, thereby performing a load operation in such a manner that under a condition of said count zero signal being at second logic level, said adjust signal being at second logic level, said output clock signal being at first logic level, and said adjusted signal being at second logic level, said down-counter is loaded with a zero and said adjusted signal is set to second logic level; under a condition of said count zero signal being at second logic level, said output clock signal being at first logic level, and said adjusted signal being at second logic level, said down-counter is loaded with a second logic level count value determined by said a, b, and c and said adjusted signal and said output clock signal are set to first logic level and second logic level, respectively; and under a condition of said count zero signal being at second logic level and said output clock signal being at second logic level, said down-counter is loaded with a first logic level count value determined by said a, b, and c, and said output clock signal is set to first logic level; while said count zero signal is set to second logic level when the value of said down-counter is zero.

4. A low jitter fractional divider with low circuit speed constraint as claimed in claim 3, wherein said first logic level count value is equal to LL (cb)/aJ/2J and said second logic level count value is equal to L(cb)/aJ subtracted by said first logic level count value, while LJ represents a function of taking an integer value.

5. A low jitter fractional divider with low circuit speed constraint as claimed in claim 3, wherein said second logic level count value is equal to L L (cb)/aJ/2J and said first logic level count value is equal to L(cb)fal subtracted by said second logic level count value, while LJ represents a function of taking an integer value.

10. A low jitter fractional divider with low circuit speed constraint as claimed in claim 8, wherein said predetermined minimum value is zero 20 and said predetermined maximum value is 21-1.

11. A low jitter fractional divider with low circuit speed constrain as claimed in claim 9, wherein said predetermined minimum value is zero and said predetermiend maximum value is 21-1.

I'b