GB2338826A

GB2338826A - Mounting semiconductor devices for cooling

Info

Publication number: GB2338826A
Application number: GB9813383A
Authority: GB
Inventors: Stephen Mark Iskander; Robert Richardson
Original assignee: EEV Ltd
Current assignee: Teledyne UK Ltd
Priority date: 1998-06-23
Filing date: 1998-06-23
Publication date: 1999-12-29
Anticipated expiration: 2018-06-23
Also published as: GB9813383D0; GB2338826B

Abstract

MOSFET 8 is bonded via an edge surface 9b to a ceramic plate 10 which in turn is bonded to a copper bar 11 which acts as a heat sink. Thermal energy is dissipated via the edge surface 9b which because of its relatively small area compared to the major surfaces 8a and 8b of the component presents a lower capacitance than in a conventional arrangement in which the component is mounted via its major surface. The arrangement is particularly suitable for high frequency applications.

Description

1 2338826 Semi!zonductoi-Arrangenic.nt This invention relates to a

semiconductor arrangement and more particularly to the provision of a heat sink for a semiconductor component.

Semiconductor components, such as FETs, are generally packaged in housings which 1 1 may have a rectangular cross-section or be cylindrical, for example. During use, such Z> semiconductor components become hot and an important aspect of circuit design is the provision for removal of excess heat which might otherwise affect the performance characteristics of the device.

Figure 1 is a schematic diagram of a conventional semiconductor arrangement in which an FET or other circuit component 1 is mounted on a ceramic support plate 2 which in turn is fixed to a metal heat sink 3. The FET 1 is connected via leads 4 to other ci.rcuitry 5 located remotely from it. The FET 1 is packaged in a housing having a rectangular or square cross-section with major faces I a and I b and a smaller area edge surface around its periphery.

One of the major surfaces l b of the housing is arranged to lie immediately adjacent the ceramic plate 2 so that the area of the housing of the FET 1 in contact with the ceramic plate 2 is maximised to give a large area for thermal conduction to the heat sink 3. The FET 1 may be fixed to the ceramic plate 2 by an adhesive or by mechanical fixing means such as screws or clamps, for example.

The present invention arose through seeking to provide an improved semiconductor arrangement.

1\ 2 According to the invention, there is provided a semiconductor arrangement comprising a semiconductor component having a major surface of relatively large area and an 0 edge surface of relatively small area, the component being fixed at its edge surface to a Z> thermally conductive, electrically insulating member which is fixed to an electrically conductive member which acts as a heat sink.

The inventors have realised that, although using the edge surface rather than the major surface as in the conventional arrangement to conduct heat from a semiconductor component, providing that the join between the component and the insulating member is sufficiently good, it is possible to remove an acceptable amount of heat from the component interior by thermal conduction. In conventional arrangements, a large surface area of the component is placed adjacent the ceramic or other electrically insulating member on which it is mounted, because the abutting surfaces are never completely flat and thermal conduction thus occurs through point contacts between those two surfaces, the amount of heat transferred.by the major surface with this type of arrangement is often less than one might imagine, particularly where mechanical fixing means are used.

A significant advantage which arises from using the present invention is that because a relatively small area of the component is in contact with the insulating member, a correspondingly small capacitance exists between the component and the electrically conductive member which acts a heat sink. This makes an arrangement in accordance with the invention particularly suitable for arrangements in which switching of the semiconductor component occurs. In a power FET, for example, in a conventionally mounted configuration, a significant proportion of the power supplied to the component is used to charge and I- 3 discharge the capacitance existing between the device and the heat sink, placin 4 a limits on the performance which can be achieved. In contrast, with the present invention, the capacitance is much reduced and performance accordingly improved. Thus, even if the join between the edge surface and the insulating member is not significantly better at conducting thermal energy than the join achieved in a conventional configuration, benefits still arise from using the invention. Also, as the capacitance is small, less heat is generated in any case.

The electrically insulating member may be, for example, of aluminium nitride. This material has much better thermal conductivity than alumina and although it is marginally inferior compared to beryllium oxide, it does not have the associated safety hazards.

Preferably, the surface of the electrically insulating member which contacts the semiconductor component is of larger area than the edge surface of the component. Thermal energy is then conducted not only in a direction normal to the edge surface of the component but also in a direction which is more parallel to it. This maximises heat flow from the component edge surface. In one embodiment, the electrically insulating member is an elongate slab with the edge surface of the component being fixed to it towards its centre along one edge. In one embodiment of the invention, the electrically conductive member is also in the form of an elongate bar which preferably is fixed for a considerable portion of its length to the insulating member. As the capacitance between the component and the heat sink is governed by the area of the component edge surface, the volume of the electrically conductive member may be maximised, within given space constraints, without adversely affecting switching characteristics or performance of the component.

4 Preferably, the component is bonded to the electrically insulating member. For example, the component may be soldered to metallisation on one side of the insulating member, giving an intimate bond to provide good heat conduction across the join. To minimize capacitance, the metallisation preferably conforms to the shape and extent of the component edge surface.

1 The semiconductor component may include a housing which is of metal, ceramic or plastic. In the latter two cases, the housing material itself may form part of the dielectric material of the capacitor formed by electrically conductive parts within the device and the heat sink. The invention is particularly applicable to a "flat-pack" type housing in which the major surfaces are square or rectangular in section. However, it may also be applied to cylindrical housings which normally would be attached via a base plate on an end face to a substrate in a conventional arrangement. In this case, the electrically insulating member is preferably shaped to conform closely with a small area of the cylindrical wall of the housing.

One way in which the invention may be performed is now described with reference to Figure 2 which schematically illustrates a semiconductor arrangement in accordance with the invention.

With reference to Figure 2, a high frequency pulse modulator includes circuitry 6 which is connected electrically via leads 7 to a power MOSFET 8 which includes a housing having square section major faces 8a and 8b and four edge surfaces 9a, 9b, 9c and 9d, each edge surface being of relatively small area compared to the areas of the major surfaces 8a 1 and 8b. One of the edge surfaces 9b is bonded to a elongate ceramic plate 10 which in this embodiment is of aluminium nitride. The housing of the MOSFET 8 is brazed or soldered onto a metallised region of the ceramic plate 10 shown by the shading. The opposite face of the ceramic plate 10 is metallised and the copper bar 11 bonded to the metallisation.

During use, heat generated at the MOSFET 8 is conducted out through the housing 1 and via the ceramic plate 10 to the copper bar 11 which acts as a heat sink, the direction of heat flow being indicated by the arrows in the Figure. Increased thermal conduction may be obtained, if necessary, by increasing the volume of the ceramic plate 10 and/or copper bar 11.

The arrangement is particularly suitable for high frequency applications, for example for frequencies of about 750 kHz and with voltage supplies of several kilovolts. The 0 invention may also be of benefit with frequencies which are significantly greater.

If additional thermal dissipation is required, a similar arrangement may also be attached to one of the other edge surfaces of the semiconductor component, for example, the edge surface 9d opposite the edge surface 9b. This still permits easy access to the semiconductor component for connection to the circuitry 6 and increases the capability of thermal conduction from the component. However, such a modification increases the component costs, the volume occupied and the capacitance and hence in most cases would not be justified.

6

Claims

1. A semiconductor arrangement comprising a semiconductor component having a major surface of relatively large area and an edge surface of relatively small area, the component being fixed at its edge surface to a thermally conductive, electrically insulating member which is fixed to an electrically conductive member which acts as a heat sink.

2. An arrangement as claimed in claim 1 wherein the edge surface is bonded to the insulating material.

3. An arrangement as claimed in claim 1 or 2 wherein the edge surface is soldered or brazed to metallisation on the electrically insulating member.

is

4. An arrangement as claimed in any preceding claim wherein the electrically conductive member is bonded to the electrically insulating member.

5. An arrangement as claimed in claim 4 wherein the electrically conductive member i brazed or soldered to metallisation on the electrically insulating member.

6. An arrangement as claimed in any preceding claim wherein the semiconductor component comprises a power FET.

1 i

7 7. An arrangement as claimed in any preceding claim wherein the semiconductor component includes a housing having a square or rectangular major surface.

0 It)

8. An arrangement as claimed in any preceding claim wherein the insulating member is of aluminium nitride.

9. An arrangement as claimed in any preceding claim wherein the conductive member is of ZD copper,

10. A switching circuit including a semiconductor arrangement as claimed in any preceding claim.

11. A circuit as claimed in claim 10 for switching at ftequencies of about 750 kHz.

12. A semiconductor arrangement substantially as illustrated in and described with reference to the Figure 2 of the accompanying drawings.