GB2336452A - Spatially pipelined arithmetic logic unit - Google Patents

Spatially pipelined arithmetic logic unit

Info

Publication number
GB2336452A
GB2336452A GB9915230A GB9915230A GB2336452A GB 2336452 A GB2336452 A GB 2336452A GB 9915230 A GB9915230 A GB 9915230A GB 9915230 A GB9915230 A GB 9915230A GB 2336452 A GB2336452 A GB 2336452A
Authority
GB
United Kingdom
Prior art keywords
bit
adder
block
carry
logic unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9915230A
Other versions
GB9915230D0 (en
GB2336452B (en
Inventor
David L Harris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB9915230D0 publication Critical patent/GB9915230D0/en
Publication of GB2336452A publication Critical patent/GB2336452A/en
Application granted granted Critical
Publication of GB2336452B publication Critical patent/GB2336452B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)

Abstract

The present invention provides a 64-bit adder having 4 spatially pipelined, 16-bit adder blocks (310). Each adder block includes 16-bit sum and carry-out logic configured in parallel. The sum logic (320) of an adder block provides a 16-bit result (326) to an associated block output, according to 16-bit operands (312) and a carry-in signal (314) input to the adder block. The carry-out logic (340) of an adder block determines a carry-in signal (318) for an adjacent adder block. The first adder block provides a 16-bit result to its associated block output at a speed determined by the latency of the 16-bit sum logic. The 16-bit results from the next three adder blocks are determined sequentially, as the carry In from each preceding 16-bit block becomes available.
GB9915230A 1996-12-31 1997-11-24 Spatially pipelined arithmetic logic unit Expired - Fee Related GB2336452B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77758796A 1996-12-31 1996-12-31
PCT/US1997/021899 WO1998029800A1 (en) 1996-12-31 1997-11-24 Spatially pipelined arithmetic logic unit

Publications (3)

Publication Number Publication Date
GB9915230D0 GB9915230D0 (en) 1999-09-01
GB2336452A true GB2336452A (en) 1999-10-20
GB2336452B GB2336452B (en) 2002-05-15

Family

ID=25110666

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9915230A Expired - Fee Related GB2336452B (en) 1996-12-31 1997-11-24 Spatially pipelined arithmetic logic unit

Country Status (4)

Country Link
AU (1) AU5367298A (en)
DE (2) DE19782228T1 (en)
GB (1) GB2336452B (en)
WO (1) WO1998029800A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10244738B3 (en) * 2002-09-25 2004-03-04 Infineon Technologies Ag Dual-rail input conversion device providing one-hot output used for cryptographic applications operated in data mode or pre-charge or pre-discharge mode via control device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4761760A (en) * 1984-08-17 1988-08-02 Nec Corporation Digital adder-subtracter with tentative result correction circuit
US4949297A (en) * 1987-09-08 1990-08-14 Ricoh Company, Ltd. Adder having means for reducing propagation time of carry bit
US5487025A (en) * 1993-11-15 1996-01-23 Intergraph Corporation Carry chain adder using regenerative push-pull differential logic

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285406A (en) * 1990-04-02 1994-02-08 Advanced Micro Devices, Inc. High speed mixed radix adder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4761760A (en) * 1984-08-17 1988-08-02 Nec Corporation Digital adder-subtracter with tentative result correction circuit
US4949297A (en) * 1987-09-08 1990-08-14 Ricoh Company, Ltd. Adder having means for reducing propagation time of carry bit
US5487025A (en) * 1993-11-15 1996-01-23 Intergraph Corporation Carry chain adder using regenerative push-pull differential logic

Also Published As

Publication number Publication date
DE19782228T1 (en) 1999-12-23
WO1998029800A1 (en) 1998-07-09
GB9915230D0 (en) 1999-09-01
GB2336452B (en) 2002-05-15
AU5367298A (en) 1998-07-31
DE19782228C2 (en) 2001-10-31

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20101124