GB2333197A - Folded cascode OTA with improved output voltage range - Google Patents

Abstract

A fast-settling operational transconductance amplifier comprises folded-cascode sections A1,A2,B1,B2 (see figures 2 and 3) in which the cascoding effect is enhanced by amplifiers in each section. The amplifiers comprise level shifters 14 at their input so that the cascode nodes SX,SY and the output nodes ON,OP can be at levels near each rail. The OTA may be used in a bandpass Sigma-Delta filter, a digital car radio, or a GSM mobile handset. The OTA uses complementary NMOS and PMOS differential input stages.

Description

OPERATIONAL TRANSCONDUCTANCE AMPLIFIER Field of the Invention The present invention relates to operational transconductance amplifiers (OTA) and, more particularly to the manufacture of OTAs as integrated circuits for incorporation in equipment such as digital communication devices like car radio or GSM mobile handsets. The invention is especially concerned with providing a design of OTA which can be manufactured using CMOS technology in order to reduce power dissipation and provide a high signal-to-noise ratio (SNR).

Background of the Invention In digital communication applications, the OTA typically forms part of a band-pass Sigma/Delta converter which is implemented as a switched capacitor network whose performance is limited by thermal (KT/c) noise. In order to keep the SNR large, it is important to design the OTA with a large output voltage range, preferably +1-2. lv and to have a fast settling characteristic, probably settling to 0.1% within 30 ns.

In the IEEE Journal of Solid-State Circuits VOL 25 No 6 December 1990, an article entitled "A Fast-Settling CMOS OP Amp for SC Circuits with 90dB DC Gain" by Bult and Geelen at pp 1379-1384 describes a fast settling single-stage operational amplifier (op amp) having the high gain of a multistage design This is achieved by the use of so-called cascoding to enhance the dc gain of the amplifier without degrading its high-frequency performance.

A "regulated" cascode circuit is discussed in IEEE Journal of Solid State Circuits Vol 25 No 1 February 1990 entitled "A HighSwing, High Impedance MOS Cascode Circuit" by Sackinger and Guggenbuhl at pp 289298.

A disadvantage of this prior art circuit is that the threshold voltage of a third transistor which forms part of an amplifier feedback loop is such that the circuit will not operate at the low voltage level, typically around 3v, of the power supply that is relevant to the applications with which the present invention is concerned.

In their text book entitled "Analog Circuit Design" Johan H Huijsing, Rudy J van der Plasche and W Sansen (editors) ;Kiuwer Academic Publishers 1993, Bult and Geelen describe, in the chapter at pp 87-108, a gain boosting technique which employs cascoding. The disclosure in the paper referred to earlier overlaps to some extent with the contents of this text book but includes further detailed analysis of the gain boost amplifier.

In the text book on pages 91-92 there is shown in FIG. 2 a cascoded gain-stage with gain enhancement. The FIG. 2 shows an arrangement for increasing the cascoding effect by adding an additional gain stage, which has the effect of further reducing the feedback from the output to the drain of the input transistor, thus further increasing the output impedance of the circuit.

In the same text book, the settling behaviour of the previously described gain-enhanced cascoded amplifier stage is discussed.

More particularly in Section 6, there is discussed and shown in FIG. 8 the complete op amp circuit implementation in which the main stage is a folded-cascode amplifier.

For more background information concerning folded-cascode amplifiers reference is made to IEEE Journal of Solid-State Circuits vol 29 no 2, February 1994 page 130 at an article by Vallee and El-Masry entitled "A Very High Frequency CMOS Complimentary Folded Cascode Amplifier".

That article describes a wide band fast settling CMOS complimentary folded cascode (CFC) tranconductance amplifier in use in analog VLSI high frequency signal processing applications and demonstrates the advantages of a CFC over a folded cascode (FC) or mirrored cascode (MC) and concludes that "the excellent settling characteristics and wide-band performance of the CFC amplifier demonstrate that this is the architecture of choice for implementing high frequency CMOS VLSI amplifiers".

However, a disadvantage of this Bult and Geelan circuit is that it has secondary poles in the gain boost amplifier which adversely affects the settling characteristics.

The present invention is concerned with making use of the above discussed types of prior art arrangements to produce a fast settling operational transconductance amplifier (OTA) which overcomes the disadvantages of the above discussed Bult and Geelan circuit arrangements.

Summary of the Invention According to the present invention a fast settling operational tranconductance amplifier (OTA) comprises a single pole gain boost amplifier (GBA) in combination with a level shifter which enables optimum large output voltage range/swing to be achieved.

According to one aspect of the present invention, the OTA employs two complimentary differential pairs at the gain stage.

Brief Description of the Drawings How the invention may be carried out will now be described, by way of example only, and with reference to the accompanying drawings in which: FIG.1 is a circuit diagram of the complete OTA in accordance with the present invention made up of a gain stage, a common mode amplifier stage and a bias stage; FIG.2 shows those parts of FIG.1, marked A, in more detail, these being active current sinks in the gain stage; FIG.3 shows those parts of FIG.1 marked B in more detail, these being active current sources in the gain stage; FIG.4 shows that part of FIG.1 marked C in more detail and is in the bias stage; FIG.5 shows that part of FIG.1 marked D in more detail and is in the bias stage; FIG. shows that part of FIG.1 marked E in more detail and is in the bias stage; FIG.7 is a bode plot of the current sink gain boost amplifier of FIG.2 at typical process characteristics at a nominal temperature of 27 deg.

Centigrade and nominal power supply of 3.3V.

FIG.8 is a bode plot of the current source GBA of FIG.3 at typical process characteristics (TYP); FIG.9 is a graph of the simulated error voltage versus the input voltage of the OTA in unity-gain configuration; FIG.lO is a graph showing the AC small-signal characteristics of the OTA at TYP; FIG.ll is a graph showing the simulated settling characteristics of the OTA for TYP, at Worst Case Speed (WCS) and Best Case Speed (BCS) and; FIG. 12 is a bode diagram of the OTA behaviour model.

Detailed Description of the Drawings Referring to FIG.1, the OTA comprises a gain stage I, a common-mode amplifier stage II and a bias stage III.

The gain stage I incorporates the present invention, whereas the common-mode amplifier stage II is known. The bias stage III is shown in FIG.s 4,5 and 6, but will not be described further.

The gain boosting amplifier (GBA) of stage I consists essentially of first and second complimentary input differential pairs shown generally at 1,2 and 3 4. Device 5 is the current source of the differential pair (1,2); device 6 is the current sink of differential pair (3,4) respectively.

The current sinks of the differential pairs 1,2,3,4 are controlled by circuits Al, A2 and the current sources of the differential pairs 1,2,3,4 by circuits B1 and B2. The circuits B1, B2 are a mirror image of the circuits Al, A2 and both circuits A and B operate on basically the same principles.

Therefore, only circuit Al will now be described in more detail with reference to FIG. 2.

Circuit Al itself consists essentially of three sub-circuits: an open drain gain stage Aa, a level shifter Ab and a cascoded current sink Ac.

An advantage of using an open drain gain stage results in a simplified amplifier structure with no second-pole frequency. This provides improved settling performance when compared with the prior art of Bult and Geelan discussed earlier.

The level shifter circuit Ab provides means to operate the current sink device 12, of the cascoded current sink circuit, as the intended Vd, voltage, which will be set marginally above its saturation voltage VdSL The amount of the DC-shift is determined by the bias circuit which controls the current source device 11 of the level shifter Ab.

As indicated earlier, circuits A and B are basically the same in structure in that the cascoded current sources B1 and B2 are identical to the cascoded current sinks Al and A2. However, PMOS devices are used in A whereas NMOS devices are used in B in order to adapt the two circuits to the required complimentary polarities.

The characteristics of the gain-boosting amplifiers at TYP are: Characteristics Current Sink Current Source Units Gain at DC 49 46 dB First-pole Frequency 0.52 - 0.38 MHz Unity-Gain Bandwidth 120 52 MHz Phase Margin 80 72 deg The AC simulations results are shown in FIGs. 7 and 8.

To obtain optimisation of noise (i.e., maximum SNR), the starting point was to design the cascoded current sinks and sources of the gain stage with the objective of achieving the intended output voltage range. For a first estimate it is assumed that the current sinks and sources as well as the cascoded devices have equal saturation voltages. With this assumption the maximum saturation voltage can be determined to be: VDDmin -4V SAT-max V RNG VSAT -max =(VDDmin ~ VRNGV4 = (3.1V-2. 1V)/4 =250 m V where VRNG is the target output voltage range I Von -VOP I To achieve this low saturation voltage, the devices of the cascoded current sinks and sources become very wide and consequently have a large transconductance which unfortunately increases the total output noise voltage of the amplifier.

Noise investigations have shown that the current sinking and sourcing devices are the dominant noise sources of this amplifier. For this reason, the available output voltage range of the amplifier output was traded for a reduced amplifier output noise until the SNR reached a maximum. This was done by increasing the saturation voltage of the current sinks and sources.

During the noise optimisation process it must be further considered that the cascoding devices contribute approximately 3-5 times less noise than the current sinks and sources. Hence the cascoding devices were designed for a smaller saturation voltage than the current sink and source devices in order to optimise the output voltage range.

After some experimentation the following maximum saturation voltages were chosen: Device VDSAT max VDS- Units Current sink, device 12 360 470 mV Current, sink, device 13 150 mV Current source, device 12 440 560 V Current source, device 13 270 mV The output voltage range of the amplifier can be calculated to be: VRNG-min=VDDmin-VDs-N-min -VDS-P-min -VDSAT-N-max -VDSAT-P-max= 1.65v The differential output voltage range of the OTA was verified by DC simulations. Results in FIG. 9 have been obtained for TYP, WCS and BCS according to the following conditions: Simulation Corner TYP WCS BCS Units Power supply voltage 3.3 3.1 3.5 V Analog Ground Voltage 1.50 1.41 1.59 V Bias current 100 115 85 % Junction temperature 90 140 0 C Processing typ slow fast The simulated AC small-signal characteristics of the gain stage at TYP is given in FIG. 10. This bode plot contains the characteristics of the gain stage with the gain-boost amplifier activated (Atot, Ptot ) and also the deactivated gain-boost amplifier (Ag, P or ). As can be noted, the gain enhancement by the gain-boosting amplifier is 45dB and increases the DCgain of the amplifier from 58dB to 103dB. The large DC-gain is beneficial to reduce the gain-dependant settling errors.

The pole frequencies of the amplifiers are shown in FIG. 10. They have been determined to: Pole Frequency Frequency Units Pole frequency of the total gain stage with GBA 2.0 kHz Pole frequency of the Gain-Boost-Amplifier (GBA) ' 220 kHz Pole frequency of the orig.gain stage (without GBA) 340 kllz Unity-gain frequency of the Gain-Boost-Amplifier 70 Unity-gain frequency of gain stage with/without GBA 250 Second-pole frequency of the original gain stage 700 The simulated settling characteristics of the OTA for TYP, WCS and BCS are given in FIG. 11, which illustrates the excellent single-pole settling characteristics of the OTA up to a differential output voltage of 1.7V. For larger output voltages the settling error increases rapidly. This degradation of the settling characteristics is expected, since for this simulation corner the MOS devices of the cascoded current sinks and sources are gradually leaving saturation.

The settling characteristics of OTAs are primarily determined by the positions of the pole frequencies. The influence of the second-pole frequency of the GBA were studied by a behaviour model of the OTA. The pole frequencies of the behaviour mode were set according to the pole frequencies referred to earlier with regard to FIG. 10. The settling characteristics were simulated with a further pole frequency, the second pole of the GBA, set to 100MHz, 200MHz, and 500MHz. The bode diagram of the behaviour model is shown in FIG. 12 and the simulated settling characteristics in FIG. 13. The simulation results obtained from the behaviour model are not in agreement with the circuit simulation results since the limited slew-rate limitation as well as the limited output voltage range of the OTA have not been built into this model.

These simulations show that the second-pole frequency of the GBA are deteriorating the settling time when this pole frequency moves towards lower frequencies. This is because the GBA forms, together with the cascoded current sink, a negative feedback arrangement such that the second-pole frequency affects the stability of this network. The second-pole frequency has a minor effect on the AC characteristics of the amplifier which are shown in FIG. 12.

In contrast to the behaviour model discussed above the GBA of the present invention has no second-pole and hence improves the stability of the current sink arrangement, and results in improved settling performance.

Claims (9)

1. CLAIMS 1. A fast settling operational transconductance amplifier (OTA) comprises a single pole gain boost amplifier (GBA) in combination with a level shifter which enables an optimum large output voltage range/swing to be achieved.
2. 2. An OTA as claimed in claim 1 which employs two complimentary differential pairs at the gain stage.
3. 3. A circuit substantially as hereinbefore described with reference to and as shown in I in FIG. 1 and in FIG. 2 of the accompanying drawings.
4. 4. A circuit substantially as hereinbefore described with reference to and as shown in FIG. 1 as a whole of the accompanying drawings.
5. 5. A circuit as claimed in any previous claim and manufactured as an integrated circuit
6. 6. A band pass Sigma-Delta filter including the circuit as claimed in any previous claim.
7. 7. A digital radio including the arrangements as claimed in any previous claim.
8. 8. A digital car radio including the arrangements of any one of the claims 1-6.
9. 9. A GSM mobile handset including the arrangements as claimed in any one of the claims 1 to 6.