GB2322964B - Polysilicon CMP process for high-density DRAM cell structures - Google Patents
Polysilicon CMP process for high-density DRAM cell structuresInfo
- Publication number
- GB2322964B GB2322964B GB9704722A GB9704722A GB2322964B GB 2322964 B GB2322964 B GB 2322964B GB 9704722 A GB9704722 A GB 9704722A GB 9704722 A GB9704722 A GB 9704722A GB 2322964 B GB2322964 B GB 2322964B
- Authority
- GB
- United Kingdom
- Prior art keywords
- cmp process
- cell structures
- dram cell
- density dram
- polysilicon cmp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title 1
- 229920005591 polysilicon Polymers 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9704722A GB2322964B (en) | 1997-03-07 | 1997-03-07 | Polysilicon CMP process for high-density DRAM cell structures |
JP9060243A JPH10256502A (en) | 1997-03-07 | 1997-03-14 | Polysilicon cmp process for high-density dram cell |
DE19710961A DE19710961C2 (en) | 1997-03-07 | 1997-03-17 | Method of manufacturing a semiconductor device with a capacitor |
FR9703423A FR2761198B1 (en) | 1997-03-07 | 1997-03-20 | POLYSILICON CMP PROCESS FOR HIGH DENSITY DRAM CELL STRUCTURES |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9704722A GB2322964B (en) | 1997-03-07 | 1997-03-07 | Polysilicon CMP process for high-density DRAM cell structures |
JP9060243A JPH10256502A (en) | 1997-03-07 | 1997-03-14 | Polysilicon cmp process for high-density dram cell |
DE19710961A DE19710961C2 (en) | 1997-03-07 | 1997-03-17 | Method of manufacturing a semiconductor device with a capacitor |
FR9703423A FR2761198B1 (en) | 1997-03-07 | 1997-03-20 | POLYSILICON CMP PROCESS FOR HIGH DENSITY DRAM CELL STRUCTURES |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9704722D0 GB9704722D0 (en) | 1997-04-23 |
GB2322964A GB2322964A (en) | 1998-09-09 |
GB2322964B true GB2322964B (en) | 2001-10-17 |
Family
ID=27438574
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9704722A Expired - Fee Related GB2322964B (en) | 1997-03-07 | 1997-03-07 | Polysilicon CMP process for high-density DRAM cell structures |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPH10256502A (en) |
DE (1) | DE19710961C2 (en) |
FR (1) | FR2761198B1 (en) |
GB (1) | GB2322964B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100270210B1 (en) * | 1998-04-25 | 2000-10-16 | 윤종용 | DRAM cell capacitor and method of manufacturing the same |
KR100301370B1 (en) * | 1998-04-29 | 2001-10-27 | 윤종용 | Method for manufacturing dram cell capacitor |
FR2835970B1 (en) * | 2002-02-11 | 2005-02-25 | Memscap | ELECTRONIC COMPONENT INCLUDING A CAPACITIVE STRUCTURE |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5150276A (en) * | 1992-01-24 | 1992-09-22 | Micron Technology, Inc. | Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings |
WO1994000873A1 (en) * | 1992-06-30 | 1994-01-06 | Siemens Aktiengesellschaft | Process for producing a semiconductor storage device |
US5292677A (en) * | 1992-09-18 | 1994-03-08 | Micron Technology, Inc. | Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts |
US5480824A (en) * | 1992-06-18 | 1996-01-02 | Goldstar Electron Co., Ltd. | Semiconductor memory cell capacitor and fabrication method thereof |
WO1996026544A1 (en) * | 1995-02-22 | 1996-08-29 | Micron Technology, Inc. | Method of forming a dram bit line contact |
US5604146A (en) * | 1996-06-10 | 1997-02-18 | Vanguard International Semiconductor Corporation | Method to fabricate a semiconductor memory device having an E-shaped storage node |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5164337A (en) * | 1989-11-01 | 1992-11-17 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a semiconductor device having a capacitor in a stacked memory cell |
DD299990A5 (en) * | 1990-02-23 | 1992-05-14 | Dresden Forschzentr Mikroelek | One-transistor memory cell arrangement and method for its production |
US5084405A (en) * | 1991-06-07 | 1992-01-28 | Micron Technology, Inc. | Process to fabricate a double ring stacked cell structure |
DE4221431A1 (en) * | 1992-06-30 | 1994-01-05 | Siemens Ag | Manufacturing process for a key capacitor |
KR960005246B1 (en) * | 1992-10-21 | 1996-04-23 | 현대전자산업주식회사 | Storage electrode manufacture of capacitor |
US5539230A (en) * | 1995-03-16 | 1996-07-23 | International Business Machines Corporation | Chimney capacitor |
JP2682509B2 (en) * | 1995-04-28 | 1997-11-26 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1997
- 1997-03-07 GB GB9704722A patent/GB2322964B/en not_active Expired - Fee Related
- 1997-03-14 JP JP9060243A patent/JPH10256502A/en active Pending
- 1997-03-17 DE DE19710961A patent/DE19710961C2/en not_active Expired - Fee Related
- 1997-03-20 FR FR9703423A patent/FR2761198B1/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5150276A (en) * | 1992-01-24 | 1992-09-22 | Micron Technology, Inc. | Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings |
US5480824A (en) * | 1992-06-18 | 1996-01-02 | Goldstar Electron Co., Ltd. | Semiconductor memory cell capacitor and fabrication method thereof |
WO1994000873A1 (en) * | 1992-06-30 | 1994-01-06 | Siemens Aktiengesellschaft | Process for producing a semiconductor storage device |
US5292677A (en) * | 1992-09-18 | 1994-03-08 | Micron Technology, Inc. | Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts |
WO1996026544A1 (en) * | 1995-02-22 | 1996-08-29 | Micron Technology, Inc. | Method of forming a dram bit line contact |
US5604146A (en) * | 1996-06-10 | 1997-02-18 | Vanguard International Semiconductor Corporation | Method to fabricate a semiconductor memory device having an E-shaped storage node |
Also Published As
Publication number | Publication date |
---|---|
FR2761198B1 (en) | 1999-04-30 |
GB9704722D0 (en) | 1997-04-23 |
DE19710961C2 (en) | 2002-02-28 |
FR2761198A1 (en) | 1998-09-25 |
GB2322964A (en) | 1998-09-09 |
DE19710961A1 (en) | 1998-09-24 |
JPH10256502A (en) | 1998-09-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20030307 |